Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T14,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T14,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T14,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T17
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T17
0	1	Covered	T17,T93,T94
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T14,T17
1	-	Covered	T17,T93,T94

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T17
DetectSt	168	Covered	T1,T14,T17
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T14,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T17
DebounceSt->IdleSt	163	Covered	T91,T161,T92
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T14,T17
IdleSt->DebounceSt	148	Covered	T1,T14,T17
StableSt->IdleSt	206	Covered	T14,T17,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T14,T17
0	1	Covered	T1,T14,T17
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T17
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T161
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T17
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T14,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T93,T94
StableSt	-	-	-	-	-	-	0	Covered	T1,T14,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	69	0	0
CntIncr_A	9116158	64192	0	0
CntNoWrap_A	9116158	8448489	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	66327	0	0
DetectedPulseOut_A	9116158	33	0	0
DisabledIdleSt_A	9116158	8114868	0	0
DisabledNoDetection_A	9116158	8117233	0	0
EnterDebounceSt_A	9116158	36	0	0
EnterDetectSt_A	9116158	33	0	0
EnterStableSt_A	9116158	33	0	0
PulseIsPulse_A	9116158	33	0	0
StayInStableSt	9116158	66274	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	69	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	2	0	0
T17	0	4	0	0
T22	0	2	0	0
T23	0	2	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T57	0	2	0	0
T93	0	4	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	64192	0	0
T1	215137	62252	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	51	0	0
T17	0	76	0	0
T22	0	84	0	0
T23	0	16	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	16	0	0
T55	0	20	0	0
T57	0	22	0	0
T93	0	200	0	0
T183	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448489	0	0
T1	215137	214734	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	66327	0	0
T1	215137	63923	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	41	0	0
T17	0	142	0	0
T22	0	123	0	0
T23	0	40	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	40	0	0
T55	0	70	0	0
T57	0	61	0	0
T93	0	197	0	0
T183	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T93	0	2	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8114868	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8117233	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	36	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T93	0	2	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T93	0	2	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T93	0	2	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	33	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	1	0	0
T17	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T93	0	2	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	66274	0	0
T1	215137	63921	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T14	0	39	0	0
T17	0	140	0	0
T22	0	121	0	0
T23	0	38	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T54	0	38	0	0
T55	0	68	0	0
T57	0	59	0	0
T93	0	194	0	0
T183	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	13	0	0
T17	783	2	0	0
T18	32165	0	0	0
T70	2343	0	0	0
T75	491	0	0	0
T93	0	1	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T12,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T12,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T17
0	1	Covered	T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T17
0	1	Covered	T12,T17,T21
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T17
1	-	Covered	T12,T17,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T17
DetectSt	168	Covered	T10,T12,T17
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T17
DebounceSt->IdleSt	163	Covered	T10,T17,T24
DetectSt->IdleSt	186	Covered	T94
DetectSt->StableSt	191	Covered	T10,T12,T17
IdleSt->DebounceSt	148	Covered	T10,T12,T17
StableSt->IdleSt	206	Covered	T10,T12,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T17
0	1	Covered	T10,T12,T17
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T17
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T17,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T17
DetectSt	-	-	-	-	1	-	-	Covered	T94
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T17,T21
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	128	0	0
CntIncr_A	9116158	29519	0	0
CntNoWrap_A	9116158	8448430	0	0
DetectStDropOut_A	9116158	1	0	0
DetectedOut_A	9116158	18527	0	0
DetectedPulseOut_A	9116158	60	0	0
DisabledIdleSt_A	9116158	8367337	0	0
DisabledNoDetection_A	9116158	8369703	0	0
EnterDebounceSt_A	9116158	68	0	0
EnterDetectSt_A	9116158	61	0	0
EnterStableSt_A	9116158	60	0	0
PulseIsPulse_A	9116158	60	0	0
StayInStableSt	9116158	18437	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	3146	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	128	0	0
T10	18817	3	0	0
T12	0	4	0	0
T17	0	5	0	0
T21	0	4	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	2	0	0
T56	0	4	0	0
T57	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	29519	0	0
T10	18817	158	0	0
T12	0	174	0	0
T17	0	114	0	0
T21	0	134	0	0
T22	0	39	0	0
T23	0	16	0	0
T24	0	138	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	48	0	0
T56	0	176	0	0
T57	0	22	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448430	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1	0	0
T94	9654	1	0	0
T189	2122	0	0	0
T190	979	0	0	0
T191	522	0	0	0
T192	431	0	0	0
T193	550	0	0	0
T194	739	0	0	0
T195	666	0	0	0
T196	493	0	0	0
T197	492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	18527	0	0
T10	18817	169	0	0
T12	0	231	0	0
T17	0	54	0	0
T21	0	214	0	0
T22	0	97	0	0
T23	0	45	0	0
T24	0	348	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	129	0	0
T56	0	88	0	0
T57	0	40	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	60	0	0
T10	18817	1	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8367337	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8369703	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	3	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	61	0	0
T10	18817	1	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	60	0	0
T10	18817	1	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	60	0	0
T10	18817	1	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	18437	0	0
T10	18817	167	0	0
T12	0	228	0	0
T17	0	51	0	0
T21	0	211	0	0
T22	0	95	0	0
T23	0	44	0	0
T24	0	347	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	127	0	0
T56	0	85	0	0
T57	0	39	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3146	0	0
T1	215137	1	0	0
T2	27744	10	0	0
T3	17023	0	0	0
T4	2290	14	0	0
T5	419	2	0	0
T6	444	3	0	0
T25	492	6	0	0
T26	507	6	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	0	2	0	0
T31	0	3	0	0
T32	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	30	0	0
T12	944	1	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	1562	0	0	0
T183	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T12,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T12,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T12,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T12,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T17
0	1	Covered	T58,T100,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T17
0	1	Covered	T1,T12,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T17
1	-	Covered	T1,T12,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T17
DetectSt	168	Covered	T1,T12,T17
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T12,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T17
DebounceSt->IdleSt	163	Covered	T17,T199,T91
DetectSt->IdleSt	186	Covered	T58,T100,T101
DetectSt->StableSt	191	Covered	T1,T12,T17
IdleSt->DebounceSt	148	Covered	T1,T12,T17
StableSt->IdleSt	206	Covered	T1,T12,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T17
0	1	Covered	T1,T12,T17
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T17
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T199,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T17
DetectSt	-	-	-	-	1	-	-	Covered	T58,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T17
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	119	0	0
CntIncr_A	9116158	187880	0	0
CntNoWrap_A	9116158	8448439	0	0
DetectStDropOut_A	9116158	3	0	0
DetectedOut_A	9116158	31864	0	0
DetectedPulseOut_A	9116158	53	0	0
DisabledIdleSt_A	9116158	8014675	0	0
DisabledNoDetection_A	9116158	8017037	0	0
EnterDebounceSt_A	9116158	63	0	0
EnterDetectSt_A	9116158	56	0	0
EnterStableSt_A	9116158	53	0	0
PulseIsPulse_A	9116158	53	0	0
StayInStableSt	9116158	31789	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	119	0	0
T1	215137	4	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	4	0	0
T17	0	3	0	0
T20	0	2	0	0
T21	0	2	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	2	0	0
T58	0	4	0	0
T93	0	8	0	0
T199	0	1	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	187880	0	0
T1	215137	124504	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	174	0	0
T17	0	76	0	0
T20	0	74	0	0
T21	0	67	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	20	0	0
T58	0	118	0	0
T93	0	391	0	0
T199	0	40	0	0
T200	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448439	0	0
T1	215137	214732	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3	0	0
T45	1107	0	0	0
T57	600	0	0	0
T58	739	1	0	0
T84	30988	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T201	522	0	0	0
T202	18758	0	0	0
T203	521	0	0	0
T204	506	0	0	0
T205	506	0	0	0
T206	486	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	31864	0	0
T1	215137	26344	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	102	0	0
T17	0	9	0	0
T20	0	291	0	0
T21	0	164	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	68	0	0
T58	0	5	0	0
T93	0	574	0	0
T198	0	65	0	0
T200	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	53	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T93	0	4	0	0
T198	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8014675	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8017037	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	63	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	2	0	0
T17	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T58	0	2	0	0
T93	0	4	0	0
T199	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	56	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T58	0	2	0	0
T93	0	4	0	0
T198	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	53	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T93	0	4	0	0
T198	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	53	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T93	0	4	0	0
T198	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	31789	0	0
T1	215137	26341	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	100	0	0
T17	0	8	0	0
T20	0	290	0	0
T21	0	163	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	67	0	0
T58	0	4	0	0
T93	0	569	0	0
T198	0	64	0	0
T200	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	31	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T12	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T58	0	1	0	0
T93	0	3	0	0
T94	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T17,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T17,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T12,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T17,T23
0	1	Covered	T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T17,T23
0	1	Covered	T12,T17,T57
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T17,T23
1	-	Covered	T12,T17,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T17,T23
DetectSt	168	Covered	T12,T17,T23
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T17,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T17,T23
DebounceSt->IdleSt	163	Covered	T91,T207,T92
DetectSt->IdleSt	186	Covered	T93
DetectSt->StableSt	191	Covered	T12,T17,T23
IdleSt->DebounceSt	148	Covered	T12,T17,T23
StableSt->IdleSt	206	Covered	T12,T17,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T17,T23
0	1	Covered	T12,T17,T23
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T17,T23
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T17,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T17,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T207
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T17,T23
DetectSt	-	-	-	-	1	-	-	Covered	T93
DetectSt	-	-	-	-	0	1	-	Covered	T12,T17,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T17,T57
StableSt	-	-	-	-	-	-	0	Covered	T12,T17,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	65	0	0
CntIncr_A	9116158	61639	0	0
CntNoWrap_A	9116158	8448493	0	0
DetectStDropOut_A	9116158	1	0	0
DetectedOut_A	9116158	2387	0	0
DetectedPulseOut_A	9116158	30	0	0
DisabledIdleSt_A	9116158	8234579	0	0
DisabledNoDetection_A	9116158	8236954	0	0
EnterDebounceSt_A	9116158	34	0	0
EnterDetectSt_A	9116158	31	0	0
EnterStableSt_A	9116158	30	0	0
PulseIsPulse_A	9116158	30	0	0
StayInStableSt	9116158	2337	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6762	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	65	0	0
T12	944	4	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	4	0	0
T23	0	2	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	2	0	0
T62	1562	0	0	0
T91	0	1	0	0
T93	0	6	0	0
T133	0	2	0	0
T154	0	2	0	0
T181	0	4	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	61639	0	0
T12	944	174	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	76	0	0
T23	0	16	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	22	0	0
T62	1562	0	0	0
T91	0	25	0	0
T93	0	291	0	0
T133	0	52	0	0
T154	0	38	0	0
T181	0	112	0	0
T199	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448493	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1	0	0
T93	20902	1	0	0
T156	493	0	0	0
T181	1026	0	0	0
T182	8938	0	0	0
T198	345921	0	0	0
T208	13241	0	0	0
T209	507	0	0	0
T210	415	0	0	0
T211	522	0	0	0
T212	879	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2387	0	0
T12	944	81	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	227	0	0
T23	0	43	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	58	0	0
T62	1562	0	0	0
T93	0	257	0	0
T133	0	41	0	0
T154	0	99	0	0
T179	0	39	0	0
T181	0	85	0	0
T199	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	30	0	0
T12	944	2	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	2	0	0
T23	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	1	0	0
T62	1562	0	0	0
T93	0	2	0	0
T133	0	1	0	0
T154	0	1	0	0
T179	0	1	0	0
T181	0	2	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8234579	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8236954	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T12	944	2	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	2	0	0
T23	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	1	0	0
T62	1562	0	0	0
T91	0	1	0	0
T93	0	3	0	0
T133	0	1	0	0
T154	0	1	0	0
T181	0	2	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	31	0	0
T12	944	2	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	2	0	0
T23	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	1	0	0
T62	1562	0	0	0
T93	0	3	0	0
T133	0	1	0	0
T154	0	1	0	0
T179	0	1	0	0
T181	0	2	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	30	0	0
T12	944	2	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	2	0	0
T23	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	1	0	0
T62	1562	0	0	0
T93	0	2	0	0
T133	0	1	0	0
T154	0	1	0	0
T179	0	1	0	0
T181	0	2	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	30	0	0
T12	944	2	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	2	0	0
T23	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	1	0	0
T62	1562	0	0	0
T93	0	2	0	0
T133	0	1	0	0
T154	0	1	0	0
T179	0	1	0	0
T181	0	2	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2337	0	0
T12	944	78	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	224	0	0
T23	0	41	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	57	0	0
T62	1562	0	0	0
T93	0	254	0	0
T133	0	39	0	0
T154	0	97	0	0
T179	0	37	0	0
T181	0	82	0	0
T199	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6762	0	0
T1	215137	1	0	0
T2	27744	18	0	0
T3	17023	28	0	0
T4	2290	14	0	0
T5	419	2	0	0
T6	444	3	0	0
T7	0	12	0	0
T25	492	7	0	0
T26	507	6	0	0
T27	405	0	0	0
T28	768	0	0	0
T30	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	10	0	0
T12	944	1	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T17	0	1	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T57	0	1	0	0
T62	1562	0	0	0
T93	0	1	0	0
T170	0	2	0	0
T181	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T12
0	1	Covered	T10,T17,T56
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T12
1	-	Covered	T10,T17,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T12
DetectSt	168	Covered	T1,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T12
DebounceSt->IdleSt	163	Covered	T94,T137,T91
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T10,T12
IdleSt->DebounceSt	148	Covered	T1,T10,T12
StableSt->IdleSt	206	Covered	T10,T17,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T12
0	1	Covered	T1,T10,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T137,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T17,T56
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	123	0	0
CntIncr_A	9116158	71568	0	0
CntNoWrap_A	9116158	8448435	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	159465	0	0
DetectedPulseOut_A	9116158	58	0	0
DisabledIdleSt_A	9116158	8198099	0	0
DisabledNoDetection_A	9116158	8200469	0	0
EnterDebounceSt_A	9116158	65	0	0
EnterDetectSt_A	9116158	58	0	0
EnterStableSt_A	9116158	58	0	0
PulseIsPulse_A	9116158	58	0	0
StayInStableSt	9116158	159381	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	123	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	4	0	0
T12	0	2	0	0
T17	0	4	0	0
T21	0	2	0	0
T22	0	2	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	71568	0	0
T1	215137	62252	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	158	0	0
T12	0	87	0	0
T17	0	76	0	0
T21	0	67	0	0
T22	0	84	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	88	0	0
T57	0	22	0	0
T58	0	59	0	0
T154	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448435	0	0
T1	215137	214734	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	159465	0	0
T1	215137	152475	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	170	0	0
T12	0	42	0	0
T17	0	53	0	0
T21	0	119	0	0
T22	0	123	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	64	0	0
T57	0	21	0	0
T58	0	45	0	0
T154	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	2	0	0
T12	0	1	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T154	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8198099	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8200469	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	65	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	2	0	0
T12	0	1	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	2	0	0
T12	0	1	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T154	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	2	0	0
T12	0	1	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T154	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	2	0	0
T12	0	1	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T154	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	159381	0	0
T1	215137	152473	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T10	0	167	0	0
T12	0	40	0	0
T17	0	50	0	0
T21	0	117	0	0
T22	0	121	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	63	0	0
T57	0	20	0	0
T58	0	43	0	0
T154	0	101	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T10	18817	1	0	0
T17	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	1	0	0
T138	417	0	0	0
T154	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T198	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T23,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T17,T23,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T23,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T17,T23,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T57
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T57
0	1	Covered	T17,T23,T181
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T23,T57
1	-	Covered	T17,T23,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T23,T57
DetectSt	168	Covered	T17,T23,T57
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T17,T23,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T23,T57
DebounceSt->IdleSt	163	Covered	T91,T187,T89
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T23,T57
IdleSt->DebounceSt	148	Covered	T17,T23,T57
StableSt->IdleSt	206	Covered	T17,T23,T181

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T23,T57
0	1	Covered	T17,T23,T57
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T23,T57
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T23,T57
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T23,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T187,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T23,T57
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T23,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T23,T181
StableSt	-	-	-	-	-	-	0	Covered	T17,T23,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	72	0	0
CntIncr_A	9116158	2227	0	0
CntNoWrap_A	9116158	8448486	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	2797	0	0
DetectedPulseOut_A	9116158	34	0	0
DisabledIdleSt_A	9116158	8268760	0	0
DisabledNoDetection_A	9116158	8271125	0	0
EnterDebounceSt_A	9116158	38	0	0
EnterDetectSt_A	9116158	34	0	0
EnterStableSt_A	9116158	34	0	0
PulseIsPulse_A	9116158	34	0	0
StayInStableSt	9116158	2745	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6129	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	72	0	0
T17	783	2	0	0
T18	32165	0	0	0
T23	0	2	0	0
T57	0	2	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	2	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	2	0	0
T182	0	2	0	0
T184	0	2	0	0
T200	0	2	0	0
T214	0	2	0	0
T215	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2227	0	0
T17	783	38	0	0
T18	32165	0	0	0
T23	0	16	0	0
T57	0	22	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	56	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	56	0	0
T182	0	84	0	0
T184	0	96	0	0
T200	0	36	0	0
T214	0	69	0	0
T215	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448486	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2797	0	0
T17	783	100	0	0
T18	32165	0	0	0
T23	0	46	0	0
T57	0	124	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	40	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	46	0	0
T182	0	41	0	0
T184	0	270	0	0
T200	0	51	0	0
T214	0	9	0	0
T215	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T17	783	1	0	0
T18	32165	0	0	0
T23	0	1	0	0
T57	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T200	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8268760	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8271125	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	38	0	0
T17	783	1	0	0
T18	32165	0	0	0
T23	0	1	0	0
T57	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T200	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T17	783	1	0	0
T18	32165	0	0	0
T23	0	1	0	0
T57	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T200	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T17	783	1	0	0
T18	32165	0	0	0
T23	0	1	0	0
T57	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T200	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T17	783	1	0	0
T18	32165	0	0	0
T23	0	1	0	0
T57	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T200	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2745	0	0
T17	783	99	0	0
T18	32165	0	0	0
T23	0	45	0	0
T57	0	122	0	0
T70	2343	0	0	0
T75	491	0	0	0
T94	0	38	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	45	0	0
T182	0	39	0	0
T184	0	269	0	0
T200	0	49	0	0
T214	0	8	0	0
T215	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6129	0	0
T1	215137	0	0	0
T2	27744	21	0	0
T3	17023	32	0	0
T4	2290	9	0	0
T5	419	3	0	0
T6	444	4	0	0
T7	0	12	0	0
T25	492	8	0	0
T26	507	4	0	0
T27	405	0	0	0
T28	768	0	0	0
T31	0	6	0	0
T32	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	16	0	0
T17	783	1	0	0
T18	32165	0	0	0
T23	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T88	0	1	0	0
T100	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T184	0	1	0	0
T187	0	1	0	0
T214	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0