Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T12,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T12,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T14
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T14
0	1	Covered	T10,T14,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T14
1	-	Covered	T10,T14,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T14
DetectSt	168	Covered	T10,T12,T14
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T14
DebounceSt->IdleSt	163	Covered	T10,T94,T137
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T12,T14
IdleSt->DebounceSt	148	Covered	T10,T12,T14
StableSt->IdleSt	206	Covered	T10,T14,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T14
0	1	Covered	T10,T12,T14
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T14
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T14
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T94,T137
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T14
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T14,T23
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	76	0	0
CntIncr_A	9116158	2519	0	0
CntNoWrap_A	9116158	8448482	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	4166	0	0
DetectedPulseOut_A	9116158	34	0	0
DisabledIdleSt_A	9116158	8435117	0	0
DisabledNoDetection_A	9116158	8437495	0	0
EnterDebounceSt_A	9116158	42	0	0
EnterDetectSt_A	9116158	34	0	0
EnterStableSt_A	9116158	34	0	0
PulseIsPulse_A	9116158	34	0	0
StayInStableSt	9116158	4114	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	76	0	0
T10	18817	3	0	0
T12	0	2	0	0
T14	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	4	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	6	0	0
T138	417	0	0	0
T154	0	2	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2519	0	0
T10	18817	158	0	0
T12	0	87	0	0
T14	0	51	0	0
T22	0	39	0	0
T23	0	16	0	0
T24	0	93	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	40	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	282	0	0
T138	417	0	0	0
T154	0	38	0	0
T199	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448482	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	4166	0	0
T10	18817	126	0	0
T12	0	189	0	0
T14	0	145	0	0
T22	0	38	0	0
T23	0	45	0	0
T24	0	360	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	83	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	548	0	0
T138	417	0	0	0
T154	0	102	0	0
T199	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T10	18817	1	0	0
T12	0	1	0	0
T14	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	3	0	0
T138	417	0	0	0
T154	0	1	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8435117	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8437495	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	42	0	0
T10	18817	2	0	0
T12	0	1	0	0
T14	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	3	0	0
T138	417	0	0	0
T154	0	1	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T10	18817	1	0	0
T12	0	1	0	0
T14	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	3	0	0
T138	417	0	0	0
T154	0	1	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T10	18817	1	0	0
T12	0	1	0	0
T14	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	3	0	0
T138	417	0	0	0
T154	0	1	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	34	0	0
T10	18817	1	0	0
T12	0	1	0	0
T14	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	3	0	0
T138	417	0	0	0
T154	0	1	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	4114	0	0
T10	18817	125	0	0
T12	0	187	0	0
T14	0	144	0	0
T22	0	36	0	0
T23	0	44	0	0
T24	0	359	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	80	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	544	0	0
T138	417	0	0	0
T154	0	101	0	0
T199	0	73	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	16	0	0
T10	18817	1	0	0
T14	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T50	492	0	0	0
T52	8539	0	0	0
T55	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T93	0	2	0	0
T94	0	1	0	0
T138	417	0	0	0
T154	0	1	0	0
T182	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T17,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T17,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T17,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T17,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T56
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T56
0	1	Covered	T17,T56,T181
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T17,T56
1	-	Covered	T17,T56,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T17,T56
DetectSt	168	Covered	T1,T17,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T17,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T17,T56
DebounceSt->IdleSt	163	Covered	T91,T92
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T17,T56
IdleSt->DebounceSt	148	Covered	T1,T17,T56
StableSt->IdleSt	206	Covered	T17,T56,T183

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T17,T56
0	1	Covered	T1,T17,T56
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T56
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T17,T56
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T56
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T17,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T56,T181
StableSt	-	-	-	-	-	-	0	Covered	T1,T17,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	54	0	0
CntIncr_A	9116158	68821	0	0
CntNoWrap_A	9116158	8448504	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	131860	0	0
DetectedPulseOut_A	9116158	26	0	0
DisabledIdleSt_A	9116158	8136048	0	0
DisabledNoDetection_A	9116158	8138419	0	0
EnterDebounceSt_A	9116158	28	0	0
EnterDetectSt_A	9116158	26	0	0
EnterStableSt_A	9116158	26	0	0
PulseIsPulse_A	9116158	26	0	0
StayInStableSt	9116158	131818	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6323	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	54	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	2	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	2	0	0
T57	0	2	0	0
T94	0	4	0	0
T137	0	2	0	0
T181	0	2	0	0
T183	0	2	0	0
T198	0	2	0	0
T214	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68821	0	0
T1	215137	62252	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	38	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	88	0	0
T57	0	22	0	0
T94	0	94	0	0
T137	0	75	0	0
T181	0	56	0	0
T183	0	84	0	0
T198	0	82	0	0
T214	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448504	0	0
T1	215137	214734	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	131860	0	0
T1	215137	126219	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	22	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	133	0	0
T57	0	61	0	0
T94	0	64	0	0
T137	0	43	0	0
T181	0	147	0	0
T183	0	37	0	0
T198	0	40	0	0
T214	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T94	0	2	0	0
T137	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T198	0	1	0	0
T214	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8136048	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8138419	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	28	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T94	0	2	0	0
T137	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T198	0	1	0	0
T214	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T94	0	2	0	0
T137	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T198	0	1	0	0
T214	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T94	0	2	0	0
T137	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T198	0	1	0	0
T214	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T94	0	2	0	0
T137	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T198	0	1	0	0
T214	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	131818	0	0
T1	215137	126217	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T17	0	21	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T56	0	132	0	0
T57	0	59	0	0
T94	0	61	0	0
T137	0	41	0	0
T181	0	146	0	0
T183	0	35	0	0
T198	0	38	0	0
T214	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6323	0	0
T1	215137	1	0	0
T2	27744	21	0	0
T3	17023	29	0	0
T4	2290	12	0	0
T5	419	3	0	0
T6	444	4	0	0
T7	0	12	0	0
T25	492	7	0	0
T26	507	5	0	0
T27	405	0	0	0
T28	768	0	0	0
T31	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	10	0	0
T17	783	1	0	0
T18	32165	0	0	0
T56	0	1	0	0
T70	2343	0	0	0
T75	491	0	0	0
T87	0	1	0	0
T94	0	1	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T128	425	0	0	0
T181	0	1	0	0
T185	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T56,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T14,T56,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T56,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T56
1	0	Covered	T4,T5,T6
1	1	Covered	T14,T56,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T56,T58
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T56,T58
0	1	Covered	T14,T56,T58
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T56,T58
1	-	Covered	T14,T56,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T56,T58
DetectSt	168	Covered	T14,T56,T58
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T14,T56,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T56,T58
DebounceSt->IdleSt	163	Covered	T56,T154,T91
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T14,T56,T58
IdleSt->DebounceSt	148	Covered	T14,T56,T58
StableSt->IdleSt	206	Covered	T14,T56,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T56,T58
0	1	Covered	T14,T56,T58
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T56,T58
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T56,T58
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T56,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T154,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T56,T58
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T56,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T56,T58
StableSt	-	-	-	-	-	-	0	Covered	T14,T56,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	125	0	0
CntIncr_A	9116158	4187	0	0
CntNoWrap_A	9116158	8448433	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	5704	0	0
DetectedPulseOut_A	9116158	58	0	0
DisabledIdleSt_A	9116158	8431360	0	0
DisabledNoDetection_A	9116158	8433725	0	0
EnterDebounceSt_A	9116158	67	0	0
EnterDetectSt_A	9116158	58	0	0
EnterStableSt_A	9116158	58	0	0
PulseIsPulse_A	9116158	58	0	0
StayInStableSt	9116158	5620	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	125	0	0
T14	7559	4	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	4	0	0
T56	0	3	0	0
T58	0	2	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	10	0	0
T154	0	3	0	0
T181	0	4	0	0
T183	0	2	0	0
T198	0	6	0	0
T199	0	2	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	4187	0	0
T14	7559	102	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	40	0	0
T56	0	176	0	0
T58	0	59	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	473	0	0
T154	0	76	0	0
T181	0	112	0	0
T183	0	84	0	0
T198	0	182	0	0
T199	0	40	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448433	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	5704	0	0
T14	7559	185	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	19	0	0
T56	0	64	0	0
T58	0	166	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	479	0	0
T154	0	40	0	0
T181	0	194	0	0
T183	0	128	0	0
T198	0	189	0	0
T199	0	39	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T14	7559	2	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	5	0	0
T154	0	1	0	0
T181	0	2	0	0
T183	0	1	0	0
T198	0	3	0	0
T199	0	1	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8431360	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8433725	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	67	0	0
T14	7559	2	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T58	0	1	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	5	0	0
T154	0	2	0	0
T181	0	2	0	0
T183	0	1	0	0
T198	0	3	0	0
T199	0	1	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T14	7559	2	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	5	0	0
T154	0	1	0	0
T181	0	2	0	0
T183	0	1	0	0
T198	0	3	0	0
T199	0	1	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T14	7559	2	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	5	0	0
T154	0	1	0	0
T181	0	2	0	0
T183	0	1	0	0
T198	0	3	0	0
T199	0	1	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	58	0	0
T14	7559	2	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	5	0	0
T154	0	1	0	0
T181	0	2	0	0
T183	0	1	0	0
T198	0	3	0	0
T199	0	1	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	5620	0	0
T14	7559	182	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	17	0	0
T56	0	63	0	0
T58	0	165	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T93	0	473	0	0
T154	0	38	0	0
T181	0	191	0	0
T183	0	126	0	0
T198	0	185	0	0
T199	0	37	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T14	7559	1	0	0
T15	1939	0	0	0
T39	819	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T58	0	1	0	0
T62	1562	0	0	0
T63	2253	0	0	0
T87	0	2	0	0
T93	0	4	0	0
T181	0	1	0	0
T182	0	1	0	0
T184	0	2	0	0
T198	0	2	0	0
T222	426	0	0	0
T223	434	0	0	0
T224	855	0	0	0
T225	405	0	0	0
T226	442	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T57,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T20,T57,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T54,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T53
1	0	Covered	T4,T5,T6
1	1	Covered	T20,T57,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T54,T55
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T54,T55
0	1	Covered	T20,T55,T93
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T54,T55
1	-	Covered	T20,T55,T93

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T57,T54
DetectSt	168	Covered	T20,T54,T55
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T20,T54,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T54,T55
DebounceSt->IdleSt	163	Covered	T57,T91,T92
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T20,T54,T55
IdleSt->DebounceSt	148	Covered	T20,T57,T54
StableSt->IdleSt	206	Covered	T20,T54,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T57,T54
0	1	Covered	T20,T57,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T54,T55
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T57,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T54,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T57
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T57,T54
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T20,T54,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T55,T93
StableSt	-	-	-	-	-	-	0	Covered	T20,T54,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	89	0	0
CntIncr_A	9116158	2889	0	0
CntNoWrap_A	9116158	8448469	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	3048	0	0
DetectedPulseOut_A	9116158	43	0	0
DisabledIdleSt_A	9116158	8013963	0	0
DisabledNoDetection_A	9116158	8016325	0	0
EnterDebounceSt_A	9116158	46	0	0
EnterDetectSt_A	9116158	43	0	0
EnterStableSt_A	9116158	43	0	0
PulseIsPulse_A	9116158	43	0	0
StayInStableSt	9116158	2981	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6368	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	89	0	0
T20	7026	4	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	2	0	0
T55	0	4	0	0
T57	0	1	0	0
T66	22070	0	0	0
T90	31182	0	0	0
T91	0	1	0	0
T93	0	4	0	0
T105	640	0	0	0
T133	0	2	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	2	0	0
T184	0	4	0	0
T198	0	4	0	0
T227	404	0	0	0
T228	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2889	0	0
T20	7026	148	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	16	0	0
T55	0	40	0	0
T57	0	22	0	0
T66	22070	0	0	0
T90	31182	0	0	0
T91	0	25	0	0
T93	0	200	0	0
T105	640	0	0	0
T133	0	52	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	84	0	0
T184	0	192	0	0
T198	0	164	0	0
T227	404	0	0	0
T228	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448469	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3048	0	0
T20	7026	81	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	67	0	0
T55	0	83	0	0
T66	22070	0	0	0
T87	0	346	0	0
T90	31182	0	0	0
T93	0	95	0	0
T105	640	0	0	0
T133	0	21	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	40	0	0
T184	0	81	0	0
T185	0	186	0	0
T198	0	79	0	0
T227	404	0	0	0
T228	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	43	0	0
T20	7026	2	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T66	22070	0	0	0
T87	0	2	0	0
T90	31182	0	0	0
T93	0	2	0	0
T105	640	0	0	0
T133	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T198	0	2	0	0
T227	404	0	0	0
T228	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8013963	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8016325	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	46	0	0
T20	7026	2	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T57	0	1	0	0
T66	22070	0	0	0
T90	31182	0	0	0
T91	0	1	0	0
T93	0	2	0	0
T105	640	0	0	0
T133	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	1	0	0
T184	0	2	0	0
T198	0	2	0	0
T227	404	0	0	0
T228	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	43	0	0
T20	7026	2	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T66	22070	0	0	0
T87	0	2	0	0
T90	31182	0	0	0
T93	0	2	0	0
T105	640	0	0	0
T133	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T198	0	2	0	0
T227	404	0	0	0
T228	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	43	0	0
T20	7026	2	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T66	22070	0	0	0
T87	0	2	0	0
T90	31182	0	0	0
T93	0	2	0	0
T105	640	0	0	0
T133	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T198	0	2	0	0
T227	404	0	0	0
T228	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	43	0	0
T20	7026	2	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T66	22070	0	0	0
T87	0	2	0	0
T90	31182	0	0	0
T93	0	2	0	0
T105	640	0	0	0
T133	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T198	0	2	0	0
T227	404	0	0	0
T228	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2981	0	0
T20	7026	78	0	0
T21	828	0	0	0
T22	12721	0	0	0
T54	0	65	0	0
T55	0	80	0	0
T66	22070	0	0	0
T87	0	342	0	0
T90	31182	0	0	0
T93	0	92	0	0
T105	640	0	0	0
T133	0	20	0	0
T162	424	0	0	0
T163	996	0	0	0
T182	0	38	0	0
T184	0	78	0	0
T185	0	183	0	0
T198	0	76	0	0
T227	404	0	0	0
T228	522	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6368	0	0
T1	215137	0	0	0
T2	27744	21	0	0
T3	17023	25	0	0
T4	2290	9	0	0
T5	419	2	0	0
T6	444	5	0	0
T7	0	13	0	0
T25	492	8	0	0
T26	507	5	0	0
T27	405	0	0	0
T28	768	0	0	0
T31	0	4	0	0
T32	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	19	0	0
T20	7026	1	0	0
T21	828	0	0	0
T22	12721	0	0	0
T55	0	1	0	0
T66	22070	0	0	0
T90	31182	0	0	0
T93	0	1	0	0
T105	640	0	0	0
T133	0	1	0	0
T157	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T172	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T198	0	1	0	0
T216	0	1	0	0
T227	404	0	0	0
T228	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T12,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T12,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T17
0	1	Covered	T218,T229,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T17
0	1	Covered	T10,T12,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T17
1	-	Covered	T10,T12,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T17
DetectSt	168	Covered	T10,T12,T17
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T17
DebounceSt->IdleSt	163	Covered	T24,T199,T91
DetectSt->IdleSt	186	Covered	T218,T229,T171
DetectSt->StableSt	191	Covered	T10,T12,T17
IdleSt->DebounceSt	148	Covered	T10,T12,T17
StableSt->IdleSt	206	Covered	T10,T12,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T17
0	1	Covered	T10,T12,T17
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T17
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T199,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T17
DetectSt	-	-	-	-	1	-	-	Covered	T218,T229,T171
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T17
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	114	0	0
CntIncr_A	9116158	43928	0	0
CntNoWrap_A	9116158	8448444	0	0
DetectStDropOut_A	9116158	3	0	0
DetectedOut_A	9116158	26963	0	0
DetectedPulseOut_A	9116158	52	0	0
DisabledIdleSt_A	9116158	8329468	0	0
DisabledNoDetection_A	9116158	8331837	0	0
EnterDebounceSt_A	9116158	60	0	0
EnterDetectSt_A	9116158	55	0	0
EnterStableSt_A	9116158	52	0	0
PulseIsPulse_A	9116158	52	0	0
StayInStableSt	9116158	26891	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	114	0	0
T10	18817	4	0	0
T12	0	4	0	0
T17	0	4	0	0
T21	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	4	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	43928	0	0
T10	18817	158	0	0
T12	0	174	0	0
T17	0	76	0	0
T21	0	67	0	0
T22	0	84	0	0
T23	0	16	0	0
T24	0	231	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	48	0	0
T57	0	22	0	0
T58	0	59	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448444	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3	0	0
T88	1162	0	0	0
T171	0	1	0	0
T213	715	0	0	0
T218	801	1	0	0
T229	0	1	0	0
T230	1914	0	0	0
T231	502	0	0	0
T232	1266	0	0	0
T233	435	0	0	0
T234	524	0	0	0
T235	499	0	0	0
T236	27431	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26963	0	0
T10	18817	170	0	0
T12	0	102	0	0
T17	0	30	0	0
T21	0	351	0	0
T22	0	43	0	0
T23	0	61	0	0
T24	0	120	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	36	0	0
T57	0	62	0	0
T58	0	166	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	52	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8329468	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8331837	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	60	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	3	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	55	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	52	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	52	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	2	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26891	0	0
T10	18817	168	0	0
T12	0	100	0	0
T17	0	28	0	0
T21	0	349	0	0
T22	0	42	0	0
T23	0	60	0	0
T24	0	118	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	35	0	0
T57	0	60	0	0
T58	0	165	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T138	417	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T10	18817	2	0	0
T12	0	2	0	0
T17	0	2	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	2	0	0
T50	492	0	0	0
T52	8539	0	0	0
T53	0	1	0	0
T58	0	1	0	0
T61	710	0	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T133	0	1	0	0
T138	417	0	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T22,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T22,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T22,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T22,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T22,T53
0	1	Covered	T1,T55,T93
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T22,T53
1	-	Covered	T1,T55,T93

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T22,T53
DetectSt	168	Covered	T1,T22,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T22,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T22,T53
DebounceSt->IdleSt	163	Covered	T91,T217,T237
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T22,T53
IdleSt->DebounceSt	148	Covered	T1,T22,T53
StableSt->IdleSt	206	Covered	T1,T22,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T22,T53
0	1	Covered	T1,T22,T53
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T22,T53
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T22,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T22,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T217,T237,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T22,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T22,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T55,T93
StableSt	-	-	-	-	-	-	0	Covered	T1,T22,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	69	0	0
CntIncr_A	9116158	104808	0	0
CntNoWrap_A	9116158	8448489	0	0
DetectStDropOut_A	9116158	0	0	0
DetectedOut_A	9116158	4246	0	0
DetectedPulseOut_A	9116158	32	0	0
DisabledIdleSt_A	9116158	8113869	0	0
DisabledNoDetection_A	9116158	8116232	0	0
EnterDebounceSt_A	9116158	37	0	0
EnterDetectSt_A	9116158	32	0	0
EnterStableSt_A	9116158	32	0	0
PulseIsPulse_A	9116158	32	0	0
StayInStableSt	9116158	4194	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9116158	6991	0	0
gen_low_level_sva.LowLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	69	0	0
T1	215137	2	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	2	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	2	0	0
T55	0	4	0	0
T56	0	2	0	0
T91	0	1	0	0
T93	0	4	0	0
T133	0	2	0	0
T181	0	2	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	104808	0	0
T1	215137	62252	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	84	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	48	0	0
T55	0	40	0	0
T56	0	88	0	0
T91	0	25	0	0
T93	0	200	0	0
T133	0	52	0	0
T181	0	56	0	0
T199	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8448489	0	0
T1	215137	214734	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	4246	0	0
T1	215137	1628	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	123	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	43	0	0
T55	0	81	0	0
T56	0	45	0	0
T87	0	431	0	0
T93	0	187	0	0
T133	0	114	0	0
T181	0	44	0	0
T199	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T87	0	2	0	0
T93	0	2	0	0
T133	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8113869	0	0
T1	215137	3	0	0
T2	27744	25685	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8116232	0	0
T1	215137	3	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	37	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T91	0	1	0	0
T93	0	2	0	0
T133	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T87	0	2	0	0
T93	0	2	0	0
T133	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T87	0	2	0	0
T93	0	2	0	0
T133	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	32	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	1	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T87	0	2	0	0
T93	0	2	0	0
T133	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	4194	0	0
T1	215137	1627	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T22	0	121	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T53	0	41	0	0
T55	0	78	0	0
T56	0	43	0	0
T87	0	427	0	0
T93	0	184	0	0
T133	0	112	0	0
T181	0	43	0	0
T199	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	6991	0	0
T1	215137	1	0	0
T2	27744	17	0	0
T3	17023	28	0	0
T4	2290	11	0	0
T5	419	2	0	0
T6	444	4	0	0
T7	0	13	0	0
T25	492	7	0	0
T26	507	5	0	0
T27	405	0	0	0
T28	768	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	12	0	0
T1	215137	1	0	0
T2	27744	0	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T25	492	0	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T55	0	1	0	0
T93	0	1	0	0
T100	0	1	0	0
T161	0	2	0	0
T171	0	2	0	0
T181	0	1	0	0
T185	0	1	0	0
T216	0	1	0	0
T218	0	1	0	0