Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T52
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T52
0	1	Covered	T33,T66,T80
1	0	Covered	T66,T111,T115

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T52
0	1	Covered	T3,T9,T52
1	0	Covered	T238

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T52
1	-	Covered	T3,T9,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T52
DetectSt	168	Covered	T3,T9,T52
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T9,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T52
DebounceSt->IdleSt	163	Covered	T239,T91,T240
DetectSt->IdleSt	186	Covered	T33,T66,T80
DetectSt->StableSt	191	Covered	T3,T9,T52
IdleSt->DebounceSt	148	Covered	T3,T9,T52
StableSt->IdleSt	206	Covered	T3,T9,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T52
0	1	Covered	T3,T9,T52
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T52
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T52
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T52
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T239,T91,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T52
DetectSt	-	-	-	-	1	-	-	Covered	T33,T66,T80
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T52
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T52
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T52
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T52
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	2980	0	0
CntIncr_A	9116158	107726	0	0
CntNoWrap_A	9116158	8445578	0	0
DetectStDropOut_A	9116158	356	0	0
DetectedOut_A	9116158	69556	0	0
DetectedPulseOut_A	9116158	851	0	0
DisabledIdleSt_A	9116158	7982786	0	0
DisabledNoDetection_A	9116158	7985003	0	0
EnterDebounceSt_A	9116158	1520	0	0
EnterDetectSt_A	9116158	1460	0	0
EnterStableSt_A	9116158	851	0	0
PulseIsPulse_A	9116158	851	0	0
StayInStableSt	9116158	68597	0	0
gen_high_event_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	738	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2980	0	0
T3	17023	52	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	32	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	24	0	0
T51	711	0	0	0
T52	0	22	0	0
T59	0	28	0	0
T60	0	38	0	0
T66	0	32	0	0
T67	0	56	0	0
T80	0	28	0	0
T81	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	107726	0	0
T3	17023	2158	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	720	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	796	0	0
T51	711	0	0	0
T52	0	605	0	0
T59	0	714	0	0
T60	0	2223	0	0
T66	0	929	0	0
T67	0	1708	0	0
T80	0	708	0	0
T81	0	5184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8445578	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16531	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	356	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T33	5966	12	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T66	0	9	0	0
T80	0	14	0	0
T98	0	20	0	0
T111	0	3	0	0
T112	0	9	0	0
T113	0	8	0	0
T114	0	15	0	0
T115	0	7	0	0
T241	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	69556	0	0
T3	17023	961	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	1249	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	378	0	0
T59	0	277	0	0
T60	0	4065	0	0
T67	0	1657	0	0
T81	0	4155	0	0
T96	0	1616	0	0
T202	0	560	0	0
T242	0	650	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	851	0	0
T3	17023	26	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	11	0	0
T59	0	14	0	0
T60	0	19	0	0
T67	0	28	0	0
T81	0	18	0	0
T96	0	15	0	0
T202	0	14	0	0
T242	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7982786	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	11155	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7985003	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	11155	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1520	0	0
T3	17023	26	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	12	0	0
T51	711	0	0	0
T52	0	11	0	0
T59	0	14	0	0
T60	0	19	0	0
T66	0	16	0	0
T67	0	28	0	0
T80	0	14	0	0
T81	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1460	0	0
T3	17023	26	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	12	0	0
T51	711	0	0	0
T52	0	11	0	0
T59	0	14	0	0
T60	0	19	0	0
T66	0	16	0	0
T67	0	28	0	0
T80	0	14	0	0
T81	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	851	0	0
T3	17023	26	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	11	0	0
T59	0	14	0	0
T60	0	19	0	0
T67	0	28	0	0
T81	0	18	0	0
T96	0	15	0	0
T202	0	14	0	0
T242	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	851	0	0
T3	17023	26	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	11	0	0
T59	0	14	0	0
T60	0	19	0	0
T67	0	28	0	0
T81	0	18	0	0
T96	0	15	0	0
T202	0	14	0	0
T242	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68597	0	0
T3	17023	931	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	1233	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	367	0	0
T59	0	263	0	0
T60	0	4046	0	0
T67	0	1629	0	0
T81	0	4135	0	0
T96	0	1598	0	0
T202	0	545	0	0
T242	0	644	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	738	0	0
T3	17023	22	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	11	0	0
T59	0	14	0	0
T60	0	19	0	0
T67	0	28	0	0
T81	0	16	0	0
T96	0	12	0	0
T202	0	13	0	0
T242	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T16,T116,T117
1	0	Covered	T91,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Covered	T92

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T7,T8,T10
DetectSt->IdleSt	186	Covered	T16,T116,T117
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T8,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T16,T116,T117
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	905	0	0
CntIncr_A	9116158	43770	0	0
CntNoWrap_A	9116158	8447653	0	0
DetectStDropOut_A	9116158	65	0	0
DetectedOut_A	9116158	13460	0	0
DetectedPulseOut_A	9116158	338	0	0
DisabledIdleSt_A	9116158	8109864	0	0
DisabledNoDetection_A	9116158	8111559	0	0
EnterDebounceSt_A	9116158	501	0	0
EnterDetectSt_A	9116158	406	0	0
EnterStableSt_A	9116158	338	0	0
PulseIsPulse_A	9116158	338	0	0
StayInStableSt	9116158	13098	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	905	0	0
T2	27744	14	0	0
T3	17023	6	0	0
T7	27126	21	0	0
T8	0	14	0	0
T9	0	2	0	0
T10	0	3	0	0
T13	0	2	0	0
T16	0	4	0	0
T18	0	8	0	0
T19	0	2	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	43770	0	0
T2	27744	399	0	0
T3	17023	213	0	0
T7	27126	1761	0	0
T8	0	670	0	0
T9	0	52	0	0
T10	0	70	0	0
T13	0	118	0	0
T16	0	211	0	0
T18	0	344	0	0
T19	0	25	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8447653	0	0
T1	215137	214736	0	0
T2	27744	25671	0	0
T3	17023	16577	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	65	0	0
T16	21770	2	0	0
T17	783	0	0	0
T18	32165	0	0	0
T106	523	0	0	0
T107	426	0	0	0
T108	505	0	0	0
T109	11802	0	0	0
T110	891	0	0	0
T116	0	3	0	0
T117	0	1	0	0
T118	0	6	0	0
T119	0	1	0	0
T120	0	5	0	0
T121	0	2	0	0
T122	0	4	0	0
T123	0	4	0	0
T124	0	5	0	0
T127	503	0	0	0
T128	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	13460	0	0
T2	27744	360	0	0
T3	17023	167	0	0
T7	27126	48	0	0
T8	0	399	0	0
T9	0	49	0	0
T18	0	189	0	0
T19	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	420	0	0
T65	0	3	0	0
T90	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	338	0	0
T2	27744	7	0	0
T3	17023	3	0	0
T7	27126	9	0	0
T8	0	6	0	0
T9	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T65	0	1	0	0
T90	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8109864	0	0
T1	215137	214736	0	0
T2	27744	22737	0	0
T3	17023	15626	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8111559	0	0
T1	215137	214737	0	0
T2	27744	22740	0	0
T3	17023	15627	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	501	0	0
T2	27744	7	0	0
T3	17023	3	0	0
T7	27126	12	0	0
T8	0	8	0	0
T9	0	1	0	0
T10	0	3	0	0
T13	0	2	0	0
T16	0	2	0	0
T18	0	4	0	0
T19	0	1	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	406	0	0
T2	27744	7	0	0
T3	17023	3	0	0
T7	27126	9	0	0
T8	0	6	0	0
T9	0	1	0	0
T16	0	2	0	0
T18	0	4	0	0
T19	0	1	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T65	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	338	0	0
T2	27744	7	0	0
T3	17023	3	0	0
T7	27126	9	0	0
T8	0	6	0	0
T9	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T65	0	1	0	0
T90	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	338	0	0
T2	27744	7	0	0
T3	17023	3	0	0
T7	27126	9	0	0
T8	0	6	0	0
T9	0	1	0	0
T18	0	4	0	0
T19	0	1	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T65	0	1	0	0
T90	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	13098	0	0
T2	27744	353	0	0
T3	17023	164	0	0
T7	27126	39	0	0
T8	0	393	0	0
T9	0	48	0	0
T18	0	185	0	0
T19	0	2	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	414	0	0
T65	0	2	0	0
T90	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	311	0	0
T2	27744	7	0	0
T3	17023	3	0	0
T7	27126	9	0	0
T8	0	6	0	0
T9	0	1	0	0
T18	0	3	0	0
T19	0	1	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T65	0	1	0	0
T90	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T52
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T52
0	1	Covered	T33,T80,T112
1	0	Covered	T96,T243,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T52
0	1	Covered	T3,T9,T52
1	0	Covered	T96,T98,T91

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T52
1	-	Covered	T3,T9,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T52
DetectSt	168	Covered	T3,T9,T52
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T9,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T52
DebounceSt->IdleSt	163	Covered	T239,T91,T240
DetectSt->IdleSt	186	Covered	T33,T80,T112
DetectSt->StableSt	191	Covered	T3,T9,T52
IdleSt->DebounceSt	148	Covered	T3,T9,T52
StableSt->IdleSt	206	Covered	T3,T9,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T52
0	1	Covered	T3,T9,T52
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T52
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T52
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T52
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T239,T91,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T52
DetectSt	-	-	-	-	1	-	-	Covered	T33,T80,T112
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T52
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T52
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T52
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T52
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	2968	0	0
CntIncr_A	9116158	101483	0	0
CntNoWrap_A	9116158	8445590	0	0
DetectStDropOut_A	9116158	338	0	0
DetectedOut_A	9116158	103165	0	0
DetectedPulseOut_A	9116158	1008	0	0
DisabledIdleSt_A	9116158	7955956	0	0
DisabledNoDetection_A	9116158	7958149	0	0
EnterDebounceSt_A	9116158	1509	0	0
EnterDetectSt_A	9116158	1460	0	0
EnterStableSt_A	9116158	1008	0	0
PulseIsPulse_A	9116158	1008	0	0
StayInStableSt	9116158	102025	0	0
gen_high_event_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	872	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2968	0	0
T3	17023	50	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	26	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	16	0	0
T51	711	0	0	0
T52	0	10	0	0
T59	0	52	0	0
T60	0	22	0	0
T66	0	54	0	0
T67	0	8	0	0
T80	0	22	0	0
T81	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	101483	0	0
T3	17023	1825	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	455	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	533	0	0
T51	711	0	0	0
T52	0	265	0	0
T59	0	1092	0	0
T60	0	1540	0	0
T66	0	1215	0	0
T67	0	256	0	0
T80	0	558	0	0
T81	0	3808	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8445590	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16533	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	338	0	0
T12	944	0	0	0
T13	16310	0	0	0
T14	7559	0	0	0
T15	1939	0	0	0
T33	5966	8	0	0
T34	502	0	0	0
T35	406	0	0	0
T36	403	0	0	0
T37	493	0	0	0
T38	729	0	0	0
T80	0	11	0	0
T91	0	1	0	0
T98	0	15	0	0
T112	0	9	0	0
T113	0	26	0	0
T114	0	10	0	0
T241	0	24	0	0
T243	0	4	0	0
T244	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	103165	0	0
T3	17023	1704	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	733	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	180	0	0
T59	0	1909	0	0
T60	0	982	0	0
T66	0	2732	0	0
T67	0	222	0	0
T81	0	2269	0	0
T111	0	1805	0	0
T242	0	1914	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1008	0	0
T3	17023	25	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	13	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	5	0	0
T59	0	26	0	0
T60	0	11	0	0
T66	0	27	0	0
T67	0	4	0	0
T81	0	14	0	0
T111	0	18	0	0
T242	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7955956	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	10655	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7958149	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	10658	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1509	0	0
T3	17023	25	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	13	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	8	0	0
T51	711	0	0	0
T52	0	5	0	0
T59	0	26	0	0
T60	0	11	0	0
T66	0	27	0	0
T67	0	4	0	0
T80	0	11	0	0
T81	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1460	0	0
T3	17023	25	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	13	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	8	0	0
T51	711	0	0	0
T52	0	5	0	0
T59	0	26	0	0
T60	0	11	0	0
T66	0	27	0	0
T67	0	4	0	0
T80	0	11	0	0
T81	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1008	0	0
T3	17023	25	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	13	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	5	0	0
T59	0	26	0	0
T60	0	11	0	0
T66	0	27	0	0
T67	0	4	0	0
T81	0	14	0	0
T111	0	18	0	0
T242	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1008	0	0
T3	17023	25	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	13	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	5	0	0
T59	0	26	0	0
T60	0	11	0	0
T66	0	27	0	0
T67	0	4	0	0
T81	0	14	0	0
T111	0	18	0	0
T242	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	102025	0	0
T3	17023	1678	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	718	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	175	0	0
T59	0	1883	0	0
T60	0	971	0	0
T66	0	2698	0	0
T67	0	218	0	0
T81	0	2255	0	0
T111	0	1787	0	0
T242	0	1904	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	872	0	0
T3	17023	24	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	11	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	5	0	0
T59	0	26	0	0
T60	0	11	0	0
T66	0	20	0	0
T67	0	4	0	0
T81	0	14	0	0
T111	0	18	0	0
T242	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T90,T199,T93
1	0	Covered	T91,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
1	0	Covered	T91

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T7
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T7,T8,T13
DetectSt->IdleSt	186	Covered	T90,T199,T93
DetectSt->StableSt	191	Covered	T2,T3,T7
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T8,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T90,T199,T93
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	951	0	0
CntIncr_A	9116158	49365	0	0
CntNoWrap_A	9116158	8447607	0	0
DetectStDropOut_A	9116158	42	0	0
DetectedOut_A	9116158	18088	0	0
DetectedPulseOut_A	9116158	402	0	0
DisabledIdleSt_A	9116158	8078522	0	0
DisabledNoDetection_A	9116158	8080250	0	0
EnterDebounceSt_A	9116158	504	0	0
EnterDetectSt_A	9116158	448	0	0
EnterStableSt_A	9116158	402	0	0
PulseIsPulse_A	9116158	402	0	0
StayInStableSt	9116158	17647	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	360	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	951	0	0
T2	27744	12	0	0
T3	17023	12	0	0
T7	27126	7	0	0
T8	0	25	0	0
T9	0	4	0	0
T13	0	15	0	0
T16	0	14	0	0
T18	0	12	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T59	0	1	0	0
T109	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	49365	0	0
T2	27744	396	0	0
T3	17023	516	0	0
T7	27126	407	0	0
T8	0	1907	0	0
T9	0	90	0	0
T13	0	845	0	0
T16	0	588	0	0
T18	0	762	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T59	0	13	0	0
T109	0	351	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8447607	0	0
T1	215137	214736	0	0
T2	27744	25673	0	0
T3	17023	16571	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	42	0	0
T21	828	0	0	0
T22	12721	0	0	0
T43	24485	0	0	0
T66	22070	0	0	0
T90	31182	8	0	0
T93	0	2	0	0
T105	640	0	0	0
T120	0	6	0	0
T123	0	1	0	0
T162	424	0	0	0
T163	996	0	0	0
T164	657	0	0	0
T165	7242	0	0	0
T199	0	6	0	0
T245	0	3	0	0
T246	0	4	0	0
T247	0	2	0	0
T248	0	9	0	0
T249	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	18088	0	0
T2	27744	258	0	0
T3	17023	244	0	0
T7	27126	193	0	0
T8	0	65	0	0
T9	0	110	0	0
T13	0	113	0	0
T16	0	151	0	0
T18	0	37	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T66	0	598	0	0
T109	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	402	0	0
T2	27744	6	0	0
T3	17023	6	0	0
T7	27126	3	0	0
T8	0	12	0	0
T9	0	2	0	0
T13	0	5	0	0
T16	0	7	0	0
T18	0	6	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T66	0	7	0	0
T109	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8078522	0	0
T1	215137	214736	0	0
T2	27744	22737	0	0
T3	17023	14880	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8080250	0	0
T1	215137	214737	0	0
T2	27744	22740	0	0
T3	17023	14884	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	504	0	0
T2	27744	6	0	0
T3	17023	6	0	0
T7	27126	4	0	0
T8	0	13	0	0
T9	0	2	0	0
T13	0	10	0	0
T16	0	7	0	0
T18	0	6	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T59	0	1	0	0
T109	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	448	0	0
T2	27744	6	0	0
T3	17023	6	0	0
T7	27126	3	0	0
T8	0	12	0	0
T9	0	2	0	0
T13	0	5	0	0
T16	0	7	0	0
T18	0	6	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T90	0	8	0	0
T109	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	402	0	0
T2	27744	6	0	0
T3	17023	6	0	0
T7	27126	3	0	0
T8	0	12	0	0
T9	0	2	0	0
T13	0	5	0	0
T16	0	7	0	0
T18	0	6	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T66	0	7	0	0
T109	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	402	0	0
T2	27744	6	0	0
T3	17023	6	0	0
T7	27126	3	0	0
T8	0	12	0	0
T9	0	2	0	0
T13	0	5	0	0
T16	0	7	0	0
T18	0	6	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T66	0	7	0	0
T109	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	17647	0	0
T2	27744	252	0	0
T3	17023	238	0	0
T7	27126	190	0	0
T8	0	53	0	0
T9	0	108	0	0
T13	0	108	0	0
T16	0	144	0	0
T18	0	30	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T66	0	591	0	0
T109	0	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	360	0	0
T2	27744	6	0	0
T3	17023	6	0	0
T7	27126	3	0	0
T8	0	12	0	0
T9	0	2	0	0
T13	0	5	0	0
T16	0	7	0	0
T18	0	5	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T66	0	7	0	0
T109	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T52
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T52
0	1	Covered	T9,T33,T66
1	0	Covered	T3,T9,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T52,T59,T60
0	1	Covered	T52,T59,T60
1	0	Covered	T250,T92

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T52,T59,T60
1	-	Covered	T52,T59,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T52
DetectSt	168	Covered	T3,T9,T52
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T52,T59,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T52
DebounceSt->IdleSt	163	Covered	T239,T91,T240
DetectSt->IdleSt	186	Covered	T3,T9,T33
DetectSt->StableSt	191	Covered	T52,T59,T60
IdleSt->DebounceSt	148	Covered	T3,T9,T52
StableSt->IdleSt	206	Covered	T52,T59,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T52
0	1	Covered	T3,T9,T52
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T52
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T52
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T52
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T239,T91,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T52
DetectSt	-	-	-	-	1	-	-	Covered	T3,T9,T33
DetectSt	-	-	-	-	0	1	-	Covered	T52,T59,T60
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T52
StableSt	-	-	-	-	-	-	1	Covered	T52,T59,T60
StableSt	-	-	-	-	-	-	0	Covered	T52,T59,T60
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	3124	0	0
CntIncr_A	9116158	108771	0	0
CntNoWrap_A	9116158	8445434	0	0
DetectStDropOut_A	9116158	309	0	0
DetectedOut_A	9116158	98723	0	0
DetectedPulseOut_A	9116158	1059	0	0
DisabledIdleSt_A	9116158	7960120	0	0
DisabledNoDetection_A	9116158	7962303	0	0
EnterDebounceSt_A	9116158	1578	0	0
EnterDetectSt_A	9116158	1547	0	0
EnterStableSt_A	9116158	1059	0	0
PulseIsPulse_A	9116158	1059	0	0
StayInStableSt	9116158	97521	0	0
gen_high_event_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	911	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	3124	0	0
T3	17023	14	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	32	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	32	0	0
T51	711	0	0	0
T52	0	20	0	0
T59	0	36	0	0
T60	0	38	0	0
T66	0	54	0	0
T67	0	44	0	0
T80	0	18	0	0
T81	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	108771	0	0
T3	17023	605	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	906	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	1062	0	0
T51	711	0	0	0
T52	0	670	0	0
T59	0	846	0	0
T60	0	2375	0	0
T66	0	1575	0	0
T67	0	1386	0	0
T80	0	455	0	0
T81	0	6630	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8445434	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16569	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	309	0	0
T9	10798	4	0	0
T10	18817	0	0	0
T33	0	16	0	0
T50	492	0	0	0
T52	8539	0	0	0
T61	710	0	0	0
T66	0	14	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T80	0	9	0	0
T112	0	26	0	0
T113	0	5	0	0
T114	0	26	0	0
T239	0	1	0	0
T241	0	8	0	0
T242	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	98723	0	0
T11	1537	0	0	0
T12	944	0	0	0
T33	5966	0	0	0
T52	8539	229	0	0
T59	0	419	0	0
T60	0	3913	0	0
T61	710	0	0	0
T67	0	2757	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T81	0	7161	0	0
T96	0	1414	0	0
T111	0	1620	0	0
T115	0	420	0	0
T138	417	0	0	0
T202	0	3308	0	0
T243	0	1243	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1059	0	0
T11	1537	0	0	0
T12	944	0	0	0
T33	5966	0	0	0
T52	8539	10	0	0
T59	0	18	0	0
T60	0	19	0	0
T61	710	0	0	0
T67	0	22	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T81	0	26	0	0
T96	0	15	0	0
T111	0	18	0	0
T115	0	6	0	0
T138	417	0	0	0
T202	0	27	0	0
T243	0	32	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7960120	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	12042	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7962303	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	12046	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1578	0	0
T3	17023	7	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	16	0	0
T51	711	0	0	0
T52	0	10	0	0
T59	0	18	0	0
T60	0	19	0	0
T66	0	27	0	0
T67	0	22	0	0
T80	0	9	0	0
T81	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1547	0	0
T3	17023	7	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	16	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	16	0	0
T51	711	0	0	0
T52	0	10	0	0
T59	0	18	0	0
T60	0	19	0	0
T66	0	27	0	0
T67	0	22	0	0
T80	0	9	0	0
T81	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1059	0	0
T11	1537	0	0	0
T12	944	0	0	0
T33	5966	0	0	0
T52	8539	10	0	0
T59	0	18	0	0
T60	0	19	0	0
T61	710	0	0	0
T67	0	22	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T81	0	26	0	0
T96	0	15	0	0
T111	0	18	0	0
T115	0	6	0	0
T138	417	0	0	0
T202	0	27	0	0
T243	0	32	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1059	0	0
T11	1537	0	0	0
T12	944	0	0	0
T33	5966	0	0	0
T52	8539	10	0	0
T59	0	18	0	0
T60	0	19	0	0
T61	710	0	0	0
T67	0	22	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T81	0	26	0	0
T96	0	15	0	0
T111	0	18	0	0
T115	0	6	0	0
T138	417	0	0	0
T202	0	27	0	0
T243	0	32	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	97521	0	0
T11	1537	0	0	0
T12	944	0	0	0
T33	5966	0	0	0
T52	8539	219	0	0
T59	0	401	0	0
T60	0	3894	0	0
T61	710	0	0	0
T67	0	2734	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T81	0	7132	0	0
T96	0	1395	0	0
T111	0	1601	0	0
T115	0	413	0	0
T138	417	0	0	0
T202	0	3277	0	0
T243	0	1210	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	911	0	0
T11	1537	0	0	0
T12	944	0	0	0
T33	5966	0	0	0
T52	8539	10	0	0
T59	0	18	0	0
T60	0	19	0	0
T61	710	0	0	0
T67	0	21	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T81	0	23	0	0
T96	0	11	0	0
T111	0	17	0	0
T115	0	5	0	0
T138	417	0	0	0
T202	0	23	0	0
T243	0	31	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T8
0	1	Covered	T7,T251,T199
1	0	Covered	T91,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T10
0	1	Covered	T2,T8,T10
1	0	Covered	T91

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T10
1	-	Covered	T2,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T8
DetectSt	168	Covered	T2,T7,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T8
DebounceSt->IdleSt	163	Covered	T7,T8,T13
DetectSt->IdleSt	186	Covered	T7,T252,T251
DetectSt->StableSt	191	Covered	T2,T8,T10
IdleSt->DebounceSt	148	Covered	T2,T7,T8
StableSt->IdleSt	206	Covered	T2,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T8,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T7,T251,T199
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	888	0	0
CntIncr_A	9116158	47252	0	0
CntNoWrap_A	9116158	8447670	0	0
DetectStDropOut_A	9116158	26	0	0
DetectedOut_A	9116158	17454	0	0
DetectedPulseOut_A	9116158	386	0	0
DisabledIdleSt_A	9116158	8085115	0	0
DisabledNoDetection_A	9116158	8086834	0	0
EnterDebounceSt_A	9116158	474	0	0
EnterDetectSt_A	9116158	417	0	0
EnterStableSt_A	9116158	386	0	0
PulseIsPulse_A	9116158	386	0	0
StayInStableSt	9116158	17030	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	347	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	888	0	0
T2	27744	4	0	0
T3	17023	0	0	0
T7	27126	15	0	0
T8	0	7	0	0
T10	0	2	0	0
T13	0	9	0	0
T16	0	8	0	0
T18	0	6	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	12	0	0
T67	0	2	0	0
T90	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	47252	0	0
T2	27744	206	0	0
T3	17023	0	0	0
T7	27126	1296	0	0
T8	0	314	0	0
T10	0	101	0	0
T13	0	552	0	0
T16	0	388	0	0
T18	0	306	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	798	0	0
T67	0	89	0	0
T90	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8447670	0	0
T1	215137	214736	0	0
T2	27744	25681	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	26	0	0
T7	27126	7	0	0
T8	33137	0	0	0
T9	10798	0	0	0
T10	18817	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T68	408	0	0	0
T116	0	1	0	0
T199	0	2	0	0
T249	0	4	0	0
T251	0	2	0	0
T253	0	3	0	0
T254	0	1	0	0
T255	0	2	0	0
T256	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	17454	0	0
T2	27744	11	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T8	0	221	0	0
T10	0	17	0	0
T13	0	21	0	0
T16	0	34	0	0
T18	0	94	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	304	0	0
T67	0	44	0	0
T81	0	212	0	0
T90	0	134	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	386	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T8	0	3	0	0
T10	0	1	0	0
T13	0	3	0	0
T16	0	3	0	0
T18	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T67	0	1	0	0
T81	0	3	0	0
T90	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8085115	0	0
T1	215137	214736	0	0
T2	27744	22737	0	0
T3	17023	16583	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8086834	0	0
T1	215137	214737	0	0
T2	27744	22740	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	474	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	8	0	0
T8	0	4	0	0
T10	0	1	0	0
T13	0	6	0	0
T16	0	5	0	0
T18	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T67	0	1	0	0
T90	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	417	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	7	0	0
T8	0	3	0	0
T10	0	1	0	0
T13	0	3	0	0
T16	0	3	0	0
T18	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T67	0	1	0	0
T90	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	386	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T8	0	3	0	0
T10	0	1	0	0
T13	0	3	0	0
T16	0	3	0	0
T18	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T67	0	1	0	0
T81	0	3	0	0
T90	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	386	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T8	0	3	0	0
T10	0	1	0	0
T13	0	3	0	0
T16	0	3	0	0
T18	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T67	0	1	0	0
T81	0	3	0	0
T90	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	17030	0	0
T2	27744	9	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T8	0	218	0	0
T10	0	16	0	0
T13	0	18	0	0
T16	0	31	0	0
T18	0	91	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	298	0	0
T67	0	43	0	0
T81	0	207	0	0
T90	0	132	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	347	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T8	0	3	0	0
T10	0	1	0	0
T13	0	3	0	0
T16	0	3	0	0
T18	0	3	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T60	0	6	0	0
T67	0	1	0	0
T81	0	1	0	0
T90	0	2	0	0