Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T52
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T52
0	1	Covered	T9,T33,T60
1	0	Covered	T9,T60,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T52,T59
0	1	Covered	T3,T52,T59
1	0	Covered	T97

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T52,T59
1	-	Covered	T3,T52,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T52
DetectSt	168	Covered	T3,T9,T52
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T52,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T52
DebounceSt->IdleSt	163	Covered	T239,T91,T240
DetectSt->IdleSt	186	Covered	T9,T33,T60
DetectSt->StableSt	191	Covered	T3,T52,T59
IdleSt->DebounceSt	148	Covered	T3,T9,T52
StableSt->IdleSt	206	Covered	T3,T52,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T52
0	1	Covered	T3,T9,T52
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T52
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T52
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T52
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T239,T91,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T52
DetectSt	-	-	-	-	1	-	-	Covered	T9,T33,T60
DetectSt	-	-	-	-	0	1	-	Covered	T3,T52,T59
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T52
StableSt	-	-	-	-	-	-	1	Covered	T3,T52,T59
StableSt	-	-	-	-	-	-	0	Covered	T3,T52,T59
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	2965	0	0
CntIncr_A	9116158	108371	0	0
CntNoWrap_A	9116158	8445593	0	0
DetectStDropOut_A	9116158	363	0	0
DetectedOut_A	9116158	75967	0	0
DetectedPulseOut_A	9116158	813	0	0
DisabledIdleSt_A	9116158	7975443	0	0
DisabledNoDetection_A	9116158	7977647	0	0
EnterDebounceSt_A	9116158	1501	0	0
EnterDetectSt_A	9116158	1464	0	0
EnterStableSt_A	9116158	813	0	0
PulseIsPulse_A	9116158	813	0	0
StayInStableSt	9116158	75033	0	0
gen_high_event_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	686	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	2965	0	0
T3	17023	28	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	22	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	54	0	0
T51	711	0	0	0
T52	0	48	0	0
T59	0	30	0	0
T60	0	54	0	0
T66	0	34	0	0
T67	0	4	0	0
T80	0	22	0	0
T81	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	108371	0	0
T3	17023	952	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	622	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	1814	0	0
T51	711	0	0	0
T52	0	1608	0	0
T59	0	690	0	0
T60	0	6136	0	0
T66	0	988	0	0
T67	0	118	0	0
T80	0	558	0	0
T81	0	6910	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8445593	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	16555	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	363	0	0
T9	10798	3	0	0
T10	18817	0	0	0
T33	0	27	0	0
T50	492	0	0	0
T52	8539	0	0	0
T60	0	18	0	0
T61	710	0	0	0
T66	0	8	0	0
T68	408	0	0	0
T69	981	0	0	0
T74	493	0	0	0
T77	526	0	0	0
T78	522	0	0	0
T80	0	11	0	0
T96	0	4	0	0
T111	0	3	0	0
T112	0	18	0	0
T113	0	11	0	0
T114	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	75967	0	0
T3	17023	1096	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	2024	0	0
T59	0	368	0	0
T67	0	121	0	0
T115	0	1708	0	0
T202	0	283	0	0
T242	0	2796	0	0
T243	0	643	0	0
T257	0	626	0	0
T258	0	2559	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	813	0	0
T3	17023	14	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	24	0	0
T59	0	15	0	0
T67	0	2	0	0
T115	0	22	0	0
T202	0	3	0	0
T242	0	11	0	0
T243	0	11	0	0
T257	0	18	0	0
T258	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7975443	0	0
T1	215137	214736	0	0
T2	27744	25685	0	0
T3	17023	11209	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	7977647	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	11209	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1501	0	0
T3	17023	14	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	11	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	27	0	0
T51	711	0	0	0
T52	0	24	0	0
T59	0	15	0	0
T60	0	27	0	0
T66	0	17	0	0
T67	0	2	0	0
T80	0	11	0	0
T81	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	1464	0	0
T3	17023	14	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T9	0	11	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T33	0	27	0	0
T51	711	0	0	0
T52	0	24	0	0
T59	0	15	0	0
T60	0	27	0	0
T66	0	17	0	0
T67	0	2	0	0
T80	0	11	0	0
T81	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	813	0	0
T3	17023	14	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	24	0	0
T59	0	15	0	0
T67	0	2	0	0
T115	0	22	0	0
T202	0	3	0	0
T242	0	11	0	0
T243	0	11	0	0
T257	0	18	0	0
T258	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	813	0	0
T3	17023	14	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	24	0	0
T59	0	15	0	0
T67	0	2	0	0
T115	0	22	0	0
T202	0	3	0	0
T242	0	11	0	0
T243	0	11	0	0
T257	0	18	0	0
T258	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	75033	0	0
T3	17023	1078	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	2000	0	0
T59	0	353	0	0
T67	0	119	0	0
T115	0	1682	0	0
T202	0	280	0	0
T242	0	2784	0	0
T243	0	632	0	0
T257	0	606	0	0
T258	0	2528	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	686	0	0
T3	17023	10	0	0
T7	27126	0	0	0
T8	33137	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T51	711	0	0	0
T52	0	24	0	0
T59	0	15	0	0
T67	0	2	0	0
T115	0	18	0	0
T202	0	3	0	0
T242	0	10	0	0
T243	0	11	0	0
T257	0	16	0	0
T258	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T2,T3
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T2,T16,T259
1	0	Covered	T91,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T52,T92

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T8,T13,T90
DetectSt->IdleSt	186	Covered	T2,T16,T259
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T91,T92
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T13,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T16,T259
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9116158	744	0	0
CntIncr_A	9116158	38359	0	0
CntNoWrap_A	9116158	8447814	0	0
DetectStDropOut_A	9116158	68	0	0
DetectedOut_A	9116158	12303	0	0
DetectedPulseOut_A	9116158	277	0	0
DisabledIdleSt_A	9116158	8106524	0	0
DisabledNoDetection_A	9116158	8108263	0	0
EnterDebounceSt_A	9116158	396	0	0
EnterDetectSt_A	9116158	349	0	0
EnterStableSt_A	9116158	277	0	0
PulseIsPulse_A	9116158	277	0	0
StayInStableSt	9116158	12000	0	0
gen_high_level_sva.HighLevelEvent_A	9116158	8450973	0	0
gen_not_sticky_sva.StableStDropOut_A	9116158	247	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	744	0	0
T2	27744	4	0	0
T3	17023	2	0	0
T7	27126	4	0	0
T8	0	5	0	0
T10	0	4	0	0
T13	0	4	0	0
T16	0	4	0	0
T18	0	16	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T52	0	10	0	0
T90	0	25	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	38359	0	0
T2	27744	217	0	0
T3	17023	63	0	0
T7	27126	224	0	0
T8	0	267	0	0
T10	0	128	0	0
T13	0	210	0	0
T16	0	211	0	0
T18	0	744	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T52	0	405	0	0
T90	0	1753	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8447814	0	0
T1	215137	214736	0	0
T2	27744	25681	0	0
T3	17023	16581	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	68	0	0
T2	27744	2	0	0
T3	17023	0	0	0
T7	27126	0	0	0
T16	0	2	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T117	0	1	0	0
T121	0	12	0	0
T123	0	11	0	0
T259	0	3	0	0
T260	0	10	0	0
T261	0	1	0	0
T262	0	9	0	0
T263	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	12303	0	0
T3	17023	63	0	0
T7	27126	122	0	0
T8	33137	69	0	0
T10	0	112	0	0
T13	0	39	0	0
T18	0	322	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T43	0	32	0	0
T51	711	0	0	0
T52	0	614	0	0
T90	0	58	0	0
T264	0	353	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	277	0	0
T3	17023	1	0	0
T7	27126	2	0	0
T8	33137	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T18	0	8	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T43	0	1	0	0
T51	711	0	0	0
T52	0	5	0	0
T90	0	12	0	0
T264	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8106524	0	0
T1	215137	214736	0	0
T2	27744	22737	0	0
T3	17023	15490	0	0
T4	2290	286	0	0
T5	419	18	0	0
T6	444	43	0	0
T25	492	91	0	0
T26	507	106	0	0
T27	405	4	0	0
T28	768	367	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8108263	0	0
T1	215137	214737	0	0
T2	27744	22740	0	0
T3	17023	15491	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	396	0	0
T2	27744	2	0	0
T3	17023	1	0	0
T7	27126	2	0	0
T8	0	4	0	0
T10	0	2	0	0
T13	0	3	0	0
T16	0	2	0	0
T18	0	8	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T52	0	5	0	0
T90	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	349	0	0
T2	27744	2	0	0
T3	17023	1	0	0
T7	27126	2	0	0
T8	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T16	0	2	0	0
T18	0	8	0	0
T26	507	0	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T52	0	5	0	0
T90	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	277	0	0
T3	17023	1	0	0
T7	27126	2	0	0
T8	33137	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T18	0	8	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T43	0	1	0	0
T51	711	0	0	0
T52	0	5	0	0
T90	0	12	0	0
T264	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	277	0	0
T3	17023	1	0	0
T7	27126	2	0	0
T8	33137	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T18	0	8	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T43	0	1	0	0
T51	711	0	0	0
T52	0	5	0	0
T90	0	12	0	0
T264	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	12000	0	0
T3	17023	62	0	0
T7	27126	120	0	0
T8	33137	68	0	0
T10	0	110	0	0
T13	0	38	0	0
T18	0	314	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T43	0	31	0	0
T51	711	0	0	0
T52	0	609	0	0
T90	0	46	0	0
T264	0	346	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	8450973	0	0
T1	215137	214737	0	0
T2	27744	25699	0	0
T3	17023	16588	0	0
T4	2290	290	0	0
T5	419	19	0	0
T6	444	44	0	0
T25	492	92	0	0
T26	507	107	0	0
T27	405	5	0	0
T28	768	368	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9116158	247	0	0
T3	17023	1	0	0
T7	27126	2	0	0
T8	33137	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T18	0	8	0	0
T27	405	0	0	0
T28	768	0	0	0
T29	547	0	0	0
T30	663	0	0	0
T31	451	0	0	0
T32	450	0	0	0
T43	0	1	0	0
T51	711	0	0	0
T52	0	4	0	0
T90	0	12	0	0
T264	0	7	0	0