Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1396952907	13199	0	0
auto_block_debounce_ctl_rd_A	1396952907	1701	0	0
auto_block_out_ctl_rd_A	1396952907	2397	0	0
com_det_ctl_0_rd_A	1396952907	3892	0	0
com_det_ctl_1_rd_A	1396952907	3779	0	0
com_det_ctl_2_rd_A	1396952907	3835	0	0
com_det_ctl_3_rd_A	1396952907	3889	0	0
com_out_ctl_0_rd_A	1396952907	4567	0	0
com_out_ctl_1_rd_A	1396952907	4353	0	0
com_out_ctl_2_rd_A	1396952907	4361	0	0
com_out_ctl_3_rd_A	1396952907	4355	0	0
com_pre_det_ctl_0_rd_A	1396952907	1427	0	0
com_pre_det_ctl_1_rd_A	1396952907	1625	0	0
com_pre_det_ctl_2_rd_A	1396952907	1410	0	0
com_pre_det_ctl_3_rd_A	1396952907	1401	0	0
com_pre_sel_ctl_0_rd_A	1396952907	4421	0	0
com_pre_sel_ctl_1_rd_A	1396952907	4542	0	0
com_pre_sel_ctl_2_rd_A	1396952907	4364	0	0
com_pre_sel_ctl_3_rd_A	1396952907	4372	0	0
com_sel_ctl_0_rd_A	1396952907	4593	0	0
com_sel_ctl_1_rd_A	1396952907	4321	0	0
com_sel_ctl_2_rd_A	1396952907	4528	0	0
com_sel_ctl_3_rd_A	1396952907	4582	0	0
ec_rst_ctl_rd_A	1396952907	2463	0	0
intr_enable_rd_A	1396952907	2036	0	0
key_intr_ctl_rd_A	1396952907	3761	0	0
key_intr_debounce_ctl_rd_A	1396952907	1443	0	0
key_invert_ctl_rd_A	1396952907	5371	0	0
pin_allowed_ctl_rd_A	1396952907	5372	0	0
pin_out_ctl_rd_A	1396952907	4488	0	0
pin_out_value_rd_A	1396952907	4510	0	0
regwen_rd_A	1396952907	1615	0	0
ulp_ac_debounce_ctl_rd_A	1396952907	1573	0	0
ulp_ctl_rd_A	1396952907	1639	0	0
ulp_lid_debounce_ctl_rd_A	1396952907	1586	0	0
ulp_pwrb_debounce_ctl_rd_A	1396952907	1569	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	13199	0	0
T14	327219	5	0	0
T15	258178	0	0	0
T20	0	8	0	0
T22	0	17	0	0
T24	0	8	0	0
T39	53693	0	0	0
T43	0	12	0	0
T62	156232	0	0	0
T63	56354	0	0	0
T65	0	2	0	0
T154	0	4	0	0
T165	0	8	0	0
T222	51174	0	0	0
T223	106430	0	0	0
T224	222558	0	0	0
T225	56685	0	0	0
T226	15476	0	0	0
T252	0	10	0	0
T291	0	13	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1701	0	0
T39	53693	0	0	0
T62	156232	10	0	0
T63	56354	0	0	0
T65	0	19	0	0
T79	238658	0	0	0
T93	0	31	0	0
T94	0	15	0	0
T154	0	27	0	0
T182	0	35	0	0
T222	51174	0	0	0
T223	106430	0	0	0
T224	222558	0	0	0
T225	56685	0	0	0
T226	15476	0	0	0
T292	0	6	0	0
T293	0	35	0	0
T294	0	11	0	0
T295	0	7	0	0
T296	128300	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	2397	0	0
T39	53693	0	0	0
T62	156232	13	0	0
T63	56354	0	0	0
T65	0	37	0	0
T79	238658	0	0	0
T93	0	22	0	0
T94	0	26	0	0
T154	0	30	0	0
T182	0	29	0	0
T222	51174	0	0	0
T223	106430	0	0	0
T224	222558	0	0	0
T225	56685	0	0	0
T226	15476	0	0	0
T292	0	9	0	0
T293	0	52	0	0
T294	0	15	0	0
T295	0	7	0	0
T296	128300	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	3892	0	0
T3	204269	26	0	0
T7	126134	38	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	43	0	0
T60	0	47	0	0
T65	0	15	0	0
T66	0	57	0	0
T90	0	66	0	0
T111	0	32	0	0
T259	0	71	0	0
T297	0	73	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	3779	0	0
T3	204269	37	0	0
T7	126134	30	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	44	0	0
T60	0	29	0	0
T65	0	12	0	0
T66	0	86	0	0
T90	0	77	0	0
T111	0	41	0	0
T259	0	61	0	0
T297	0	62	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	3835	0	0
T3	204269	23	0	0
T7	126134	58	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	38	0	0
T60	0	29	0	0
T65	0	11	0	0
T66	0	81	0	0
T90	0	77	0	0
T111	0	26	0	0
T259	0	93	0	0
T297	0	56	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	3889	0	0
T3	204269	22	0	0
T7	126134	39	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	29	0	0
T60	0	38	0	0
T65	0	9	0	0
T66	0	57	0	0
T90	0	74	0	0
T111	0	32	0	0
T259	0	52	0	0
T297	0	76	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4567	0	0
T3	204269	48	0	0
T7	126134	30	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	43	0	0
T60	0	51	0	0
T65	0	10	0	0
T66	0	37	0	0
T90	0	62	0	0
T111	0	41	0	0
T259	0	63	0	0
T297	0	63	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4353	0	0
T3	204269	12	0	0
T7	126134	46	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	37	0	0
T60	0	51	0	0
T65	0	14	0	0
T66	0	66	0	0
T90	0	47	0	0
T111	0	35	0	0
T259	0	72	0	0
T297	0	71	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4361	0	0
T3	204269	32	0	0
T7	126134	52	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	47	0	0
T60	0	39	0	0
T65	0	12	0	0
T66	0	60	0	0
T90	0	57	0	0
T111	0	51	0	0
T259	0	49	0	0
T297	0	60	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4355	0	0
T3	204269	34	0	0
T7	126134	39	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	26	0	0
T60	0	43	0	0
T65	0	12	0	0
T66	0	84	0	0
T90	0	54	0	0
T111	0	25	0	0
T259	0	67	0	0
T297	0	36	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1427	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	13	0	0
T66	297955	0	0	0
T87	0	25	0	0
T90	763968	0	0	0
T93	0	13	0	0
T94	0	16	0	0
T150	0	18	0	0
T154	0	20	0	0
T182	0	38	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	37	0	0
T298	0	17	0	0
T299	0	12	0	0
T300	243622	0	0	0
T301	244417	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1625	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	13	0	0
T66	297955	0	0	0
T87	0	23	0	0
T90	763968	0	0	0
T93	0	12	0	0
T94	0	29	0	0
T150	0	22	0	0
T154	0	23	0	0
T182	0	30	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	45	0	0
T298	0	16	0	0
T299	0	12	0	0
T300	243622	0	0	0
T301	244417	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1410	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	11	0	0
T66	297955	0	0	0
T87	0	17	0	0
T90	763968	0	0	0
T93	0	30	0	0
T94	0	19	0	0
T150	0	11	0	0
T154	0	15	0	0
T182	0	46	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	51	0	0
T298	0	11	0	0
T299	0	12	0	0
T300	243622	0	0	0
T301	244417	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1401	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	18	0	0
T66	297955	0	0	0
T87	0	28	0	0
T90	763968	0	0	0
T93	0	15	0	0
T94	0	10	0	0
T150	0	11	0	0
T154	0	23	0	0
T182	0	42	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	37	0	0
T298	0	13	0	0
T299	0	7	0	0
T300	243622	0	0	0
T301	244417	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4421	0	0
T3	204269	17	0	0
T7	126134	30	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	32	0	0
T60	0	42	0	0
T65	0	17	0	0
T66	0	40	0	0
T90	0	71	0	0
T111	0	30	0	0
T259	0	71	0	0
T297	0	57	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4542	0	0
T3	204269	30	0	0
T7	126134	43	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	40	0	0
T60	0	19	0	0
T65	0	5	0	0
T66	0	44	0	0
T90	0	75	0	0
T111	0	28	0	0
T259	0	72	0	0
T297	0	70	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4364	0	0
T3	204269	17	0	0
T7	126134	37	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	30	0	0
T60	0	31	0	0
T65	0	13	0	0
T66	0	80	0	0
T90	0	75	0	0
T111	0	19	0	0
T259	0	72	0	0
T297	0	89	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4372	0	0
T3	204269	31	0	0
T7	126134	35	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	35	0	0
T60	0	30	0	0
T65	0	17	0	0
T66	0	64	0	0
T90	0	89	0	0
T111	0	20	0	0
T259	0	61	0	0
T297	0	70	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4593	0	0
T3	204269	38	0	0
T7	126134	49	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	37	0	0
T60	0	32	0	0
T65	0	12	0	0
T66	0	65	0	0
T90	0	67	0	0
T111	0	44	0	0
T259	0	65	0	0
T297	0	82	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4321	0	0
T3	204269	16	0	0
T7	126134	27	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	43	0	0
T60	0	23	0	0
T65	0	9	0	0
T66	0	73	0	0
T90	0	72	0	0
T111	0	31	0	0
T259	0	80	0	0
T297	0	77	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4528	0	0
T3	204269	38	0	0
T7	126134	25	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	36	0	0
T60	0	19	0	0
T65	0	2	0	0
T66	0	57	0	0
T90	0	66	0	0
T111	0	23	0	0
T259	0	52	0	0
T297	0	78	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4582	0	0
T3	204269	31	0	0
T7	126134	19	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	32	0	0
T60	0	25	0	0
T65	0	11	0	0
T66	0	81	0	0
T90	0	92	0	0
T111	0	25	0	0
T259	0	80	0	0
T297	0	66	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	2463	0	0
T3	204269	12	0	0
T7	126134	10	0	0
T8	811888	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T32	220764	0	0	0
T51	106742	0	0	0
T52	0	8	0	0
T60	0	1	0	0
T65	0	15	0	0
T66	0	28	0	0
T90	0	52	0	0
T164	0	3	0	0
T302	0	2	0	0
T303	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	2036	0	0
T19	345767	0	0	0
T20	167028	0	0	0
T60	781678	0	0	0
T64	331606	0	0	0
T65	268513	8	0	0
T87	0	55	0	0
T93	0	37	0	0
T94	0	40	0	0
T133	0	5	0	0
T150	0	33	0	0
T154	0	59	0	0
T182	0	23	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	41	0	0
T300	243622	0	0	0
T301	244417	0	0	0
T304	810634	10	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	3761	0	0
T12	335568	1	0	0
T13	195733	0	0	0
T14	327219	0	0	0
T15	258178	0	0	0
T17	0	1	0	0
T23	0	5	0	0
T34	248400	0	0	0
T35	48767	0	0	0
T36	98705	0	0	0
T37	123504	0	0	0
T38	69295	0	0	0
T54	0	2	0	0
T56	0	2	0	0
T62	156232	0	0	0
T65	0	17	0	0
T93	0	16	0	0
T154	0	29	0	0
T182	0	46	0	0
T200	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1443	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	2	0	0
T66	297955	0	0	0
T87	0	17	0	0
T90	763968	0	0	0
T93	0	14	0	0
T94	0	24	0	0
T150	0	20	0	0
T154	0	19	0	0
T182	0	40	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	23	0	0
T298	0	11	0	0
T299	0	5	0	0
T300	243622	0	0	0
T301	244417	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	5371	0	0
T2	105427	0	0	0
T3	204269	0	0	0
T7	126134	0	0	0
T25	199495	65	0	0
T26	63405	0	0	0
T27	56848	0	0	0
T28	92232	0	0	0
T29	21870	0	0	0
T30	50159	0	0	0
T31	29347	0	0	0
T50	0	61	0	0
T62	0	55	0	0
T65	0	129	0	0
T93	0	330	0	0
T154	0	133	0	0
T168	0	66	0	0
T182	0	110	0	0
T305	0	70	0	0
T306	0	70	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	5372	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	97	0	0
T66	297955	0	0	0
T90	763968	0	0	0
T93	0	266	0	0
T94	0	9	0	0
T154	0	70	0	0
T182	0	96	0	0
T204	0	73	0	0
T205	0	49	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	27	0	0
T300	243622	0	0	0
T301	244417	0	0	0
T307	0	75	0	0
T308	0	77	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4488	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	81	0	0
T66	297955	0	0	0
T90	763968	0	0	0
T93	0	231	0	0
T94	0	17	0	0
T154	0	111	0	0
T182	0	109	0	0
T204	0	65	0	0
T205	0	69	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	42	0	0
T300	243622	0	0	0
T301	244417	0	0	0
T307	0	74	0	0
T308	0	77	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	4510	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	71	0	0
T66	297955	0	0	0
T90	763968	0	0	0
T93	0	323	0	0
T94	0	20	0	0
T154	0	76	0	0
T182	0	101	0	0
T204	0	70	0	0
T205	0	88	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	44	0	0
T300	243622	0	0	0
T301	244417	0	0	0
T307	0	53	0	0
T308	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1615	0	0
T20	167028	0	0	0
T21	47740	0	0	0
T60	781678	0	0	0
T65	268513	14	0	0
T66	297955	0	0	0
T87	0	23	0	0
T90	763968	0	0	0
T93	0	12	0	0
T94	0	17	0	0
T150	0	11	0	0
T154	0	10	0	0
T182	0	24	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T293	0	29	0	0
T298	0	15	0	0
T300	243622	0	0	0
T301	244417	0	0	0
T309	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1573	0	0
T19	345767	0	0	0
T20	167028	0	0	0
T44	0	15	0	0
T45	0	12	0	0
T60	781678	0	0	0
T64	331606	0	0	0
T65	268513	9	0	0
T93	0	28	0	0
T139	0	7	0	0
T140	0	10	0	0
T142	0	9	0	0
T154	0	26	0	0
T227	101198	0	0	0
T228	250753	0	0	0
T300	243622	0	0	0
T301	244417	0	0	0
T304	810634	2	0	0
T310	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1639	0	0
T16	522507	0	0	0
T17	72405	0	0	0
T18	160827	0	0	0
T40	227903	8	0	0
T41	228008	0	0	0
T42	218334	4	0	0
T44	0	6	0	0
T45	0	5	0	0
T59	365586	0	0	0
T65	0	14	0	0
T93	0	24	0	0
T106	125702	0	0	0
T107	59656	0	0	0
T127	70540	0	0	0
T140	0	10	0	0
T154	0	16	0	0
T304	0	3	0	0
T310	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1586	0	0
T16	522507	0	0	0
T17	72405	0	0	0
T18	160827	0	0	0
T42	218334	1	0	0
T44	0	14	0	0
T45	0	4	0	0
T65	0	17	0	0
T93	0	30	0	0
T106	125702	0	0	0
T107	59656	0	0	0
T108	83430	0	0	0
T109	147540	0	0	0
T110	427576	0	0	0
T127	70540	0	0	0
T140	0	3	0	0
T142	0	6	0	0
T154	0	27	0	0
T304	0	2	0	0
T310	0	13	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1396952907	1569	0	0
T16	522507	0	0	0
T17	72405	0	0	0
T18	160827	0	0	0
T42	218334	6	0	0
T44	0	9	0	0
T45	0	7	0	0
T65	0	8	0	0
T93	0	12	0	0
T106	125702	0	0	0
T107	59656	0	0	0
T108	83430	0	0	0
T109	147540	0	0	0
T110	427576	0	0	0
T127	70540	0	0	0
T140	0	8	0	0
T142	0	1	0	0
T154	0	18	0	0
T304	0	3	0	0
T310	0	4	0	0