Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_intr_status_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_intr_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	0	28	100.00

Variables for Group Instance sysrst_ctrl_key_intr_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_h2l	2	0	2	100.00	100	1	1	2
cp_ac_present_l2h	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_h2l	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_l2h	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_h2l	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_l2h	2	0	2	100.00	100	1	1	2
cp_key0_in_h2l	2	0	2	100.00	100	1	1	2
cp_key0_in_l2h	2	0	2	100.00	100	1	1	2
cp_key1_in_h2l	2	0	2	100.00	100	1	1	2
cp_key1_in_l2h	2	0	2	100.00	100	1	1	2
cp_key2_in_h2l	2	0	2	100.00	100	1	1	2
cp_key2_in_l2h	2	0	2	100.00	100	1	1	2
cp_pwrb_h2l	2	0	2	100.00	100	1	1	2
cp_pwrb_l2h	2	0	2	100.00	100	1	1	2

Summary for Variable cp_ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T3

1

T8

1

T9

1

auto[1]

92

1

T8

3

T15

4

T20

1

---

Summary for Variable cp_ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T3

1

T8

3

T9

1

auto[1]

139

1

T8

1

T15

6

T20

2

---

Summary for Variable cp_ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T3

1

T8

4

T9

1

auto[1]

119

1

T12

4

T20

1

T21

3

---

Summary for Variable cp_ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T3

1

T8

3

T9

1

auto[1]

96

1

T8

1

T20

2

T24

3

---

Summary for Variable cp_flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T3

1

T8

3

T9

1

auto[1]

111

1

T8

1

T10

3

T12

1

---

Summary for Variable cp_flash_wp_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T3

1

T8

1

T9

1

auto[1]

103

1

T8

3

T12

1

T15

1

---

Summary for Variable cp_key0_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T3

1

T8

4

T9

1

auto[1]

92

1

T10

3

T15

2

T22

3

---

Summary for Variable cp_key0_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T3

1

T8

3

T9

1

auto[1]

145

1

T8

1

T10

3

T15

1

---

Summary for Variable cp_key1_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T3

1

T8

4

T9

1

auto[1]

79

1

T15

3

T17

1

T22

1

---

Summary for Variable cp_key1_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T3

1

T8

3

T9

1

auto[1]

139

1

T8

1

T10

3

T12

2

---

Summary for Variable cp_key2_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T3

1

T8

3

T9

1

auto[1]

99

1

T8

1

T15

4

T20

3

---

Summary for Variable cp_key2_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T3

1

T8

4

T9

1

auto[1]

109

1

T10

3

T12

4

T15

4

---

Summary for Variable cp_pwrb_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T3

1

T8

4

T9

1

auto[1]

92

1

T10

3

T12

3

T15

3

---

Summary for Variable cp_pwrb_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T3

1

T8

1

T9

1

auto[1]

150

1

T8

3

T10

5

T12

2