Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2196

1

T42

20

T25

11

T2

16

auto[1]

752

1

T1

11

T28

2

T11

21

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2202

1

T42

14

T1

5

T25

9

auto[1]

746

1

T42

6

T1

6

T25

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2204

1

T42

15

T25

9

T2

16

auto[1]

744

1

T42

5

T1

11

T25

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2207

1

T42

17

T1

11

T2

12

auto[1]

741

1

T42

3

T25

11

T2

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2721

1

T42

13

T1

11

T25

11

auto[1]

227

1

T42

7

T2

4

T13

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2691

1

T42

18

T1

11

T25

11

auto[1]

257

1

T42

2

T11

11

T13

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2665

1

T42

19

T1

11

T25

11

auto[1]

283

1

T42

1

T2

4

T28

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619

1

T42

20

T1

11

T25

11

auto[1]

329

1

T18

11

T52

1

T125

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2581

1

T42

14

T1

11

T25

11

auto[1]

367

1

T42

6

T7

12

T28

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2217

1

T42

17

T1

9

T25

11

auto[1]

731

1

T42

3

T1

2

T13

5

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	796	1			T1	11		T25	11		T82	6
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	84	1			T217	1		T368	2		T352	24
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	159	1			T7	12		T13	24		T52	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	27	1			T42	6		T229	5		T369	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	150	1			T18	6		T217	1		T239	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	29	1			T214	1		T239	2		T285	7
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	32	1			T79	13		T285	7		T370	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T370	2		T371	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	82	1			T13	5		T18	5		T214	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	25	1			T42	1		T2	4		T352	8
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	55	1			T28	2		T11	10		T18	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T239	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	24	1			T18	5		T125	3		T372	6
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T52	1		T362	3		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	13	1			T229	7		T369	6		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	104	1			T52	8		T125	4		T372	9
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	15	1			T13	4		T201	2		T373	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	34	1			T11	11		T240	6		T374	13
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T373	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	25	1			T229	6		T375	1		T366	8
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T353	1		T183	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	8	1			T360	1		T201	1		T376	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	28	1			T352	9		T359	1		T374	12
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T359	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T86	5		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T359	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T86	2		T377	2		T378	1

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

122

1

T11

10

T149

24

T79

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

113

1

T42

1

T86

2

T243

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

56

1

T18

6

T256

8

T372

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

98

1

T25

9

T13

12

T86

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T20

2

T79

9

T284

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T13

5

T82

4

T256

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T20

1

T214

1

T78

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

90

1

T7

12

T351

8

T285

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

125

1

T1

5

T79

17

T372

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T52

8

T83

7

T88

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46

1

T229

6

T81

3

T379

17

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T13

16

T20

1

T250

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37

1

T11

11

T52

5

T125

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

34

1

T149

5

T250

1

T286

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T253

2

T174

1

T291

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

147

1

T42

3

T18

5

T52

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

52

1

T149

4

T217

1

T372

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

84

1

T20

1

T125

3

T214

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

45

1

T82

1

T256

5

T380

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

43

1

T2

4

T286

5

T381

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T28

2

T18

10

T240

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T368

2

T56

1

T380

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T377

2

T174

1

T246

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

77

1

T19

4

T229

16

T368

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T1

4

T19

2

T83

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T256

3

T250

2

T239

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T1

2

T228

6

T186

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T42

3

T25

2

T110

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T82

1

T360

14

T252

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T110

2

T83

2

T253

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T20

2

T255

1

T195

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded