Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T6

10

T40

10

T41

10

auto[1]

1123

1

T6

10

T40

10

T41

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T6

7

T40

5

T41

5

from_0to1

528

1

T6

6

T40

5

T41

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T6

11

T40

10

T41

10

auto[1]

1097

1

T6

9

T40

10

T41

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T6

12

T40

11

T41

9

auto[1]

1049

1

T6

8

T40

9

T41

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T41

1

T29

1

T30

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T40

1

T41

2

T29

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T6

2

T30

1

T15

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T6

1

T29

1

T15

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T6

1

T40

1

T15

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T40

1

T41

1

T29

3

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T6

3

T41

1

T30

2

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T41

1

T29

1

T15

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T6

2

T40

2

T15

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T40

1

T41

2

T15

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T6

1

T40

1

T30

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T6

1

T29

1

T30

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T40

1

T29

1

T30

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T6

1

T41

1

T30

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T40

1

T41

1

T108

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T6

1

T40

1

T29

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T6

11

T40

11

T41

10

auto[1]

1086

1

T6

9

T40

9

T41

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T6

3

T40

4

T41

4

from_0to1

517

1

T6

3

T40

4

T41

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T6

9

T40

14

T41

7

auto[1]

1087

1

T6

11

T40

6

T41

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T6

10

T40

12

T41

7

auto[1]

1107

1

T6

10

T40

8

T41

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T6

1

T41

1

T29

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T40

1

T41

2

T29

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T64

3

T20

1

T150

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T30

1

T15

2

T108

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T40

1

T29

1

T150

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T40

1

T15

1

T64

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T6

2

T40

2

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T15

1

T64

1

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T6

2

T40

1

T15

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T40

2

T29

2

T15

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T64

1

T150

1

T305

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T41

1

T29

1

T30

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T41

1

T29

1

T15

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T6

1

T20

1

T121

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T30

1

T15

1

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T41

2

T29

2

T15

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T6

10

T40

8

T41

12

auto[1]

1076

1

T6

10

T40

12

T41

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T6

5

T40

5

T41

6

from_0to1

520

1

T6

5

T40

4

T41

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T6

9

T40

7

T41

10

auto[1]

1142

1

T6

11

T40

13

T41

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T6

7

T40

13

T41

11

auto[1]

1067

1

T6

13

T40

7

T41

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T41

1

T29

1

T108

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T6

1

T41

1

T29

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T41

1

T29

1

T15

6

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T41

1

T29

3

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T41

1

T29

3

T108

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T6

1

T15

1

T64

3

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T6

1

T40

2

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T6

1

T41

1

T29

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T6

1

T41

2

T29

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T40

2

T108

2

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T6

1

T40

2

T30

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T6

1

T40

1

T15

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T40

1

T29

1

T15

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T6

1

T41

3

T30

2

auto[1]

from_0to1

auto[1]

auto[0]

82

1

T40

1

T29

1

T30

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T6

1

T30

1

T15

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T6

10

T40

12

T41

10

auto[1]

1043

1

T6

10

T40

8

T41

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T6

2

T40

5

T41

4

from_0to1

519

1

T6

3

T40

6

T41

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T6

9

T40

7

T41

7

auto[1]

1089

1

T6

11

T40

13

T41

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T6

12

T40

13

T41

12

auto[1]

1101

1

T6

8

T40

7

T41

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T6

1

T41

1

T15

3

auto[0]

from_1to0

auto[0]

auto[1]

45

1

T41

1

T305

2

T300

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T40

2

T29

1

T64

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T40

1

T29

1

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T6

1

T29

1

T15

2

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T40

1

T29

2

T15

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T40

2

T41

4

T29

1

auto[0]

from_0to1

auto[1]

auto[1]

81

1

T40

1

T30

1

T15

3

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T6

1

T40

2

T30

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T29

1

T15

3

T64

2

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T41

1

T29

1

T15

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T41

1

T30

1

T15

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T40

1

T15

1

T108

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T6

1

T15

3

T64

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T6

1

T40

1

T30

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T41

1

T121

1

T305

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T6

11

T40

7

T41

10

auto[1]

1082

1

T6

9

T40

13

T41

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T6

6

T40

4

T41

6

from_0to1

536

1

T6

6

T40

5

T41

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T6

11

T40

12

T41

14

auto[1]

1066

1

T6

9

T40

8

T41

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T6

11

T40

12

T41

8

auto[1]

1077

1

T6

9

T40

8

T41

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T15

1

T64

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T40

1

T41

2

T15

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T6

3

T29

1

T30

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T6

1

T41

1

T15

3

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T6

1

T41

3

T29

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T40

1

T29

1

T30

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T41

1

T30

1

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T41

1

T30

1

T15

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T29

1

T15

1

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T6

1

T40

1

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T41

1

T30

2

T15

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T6

1

T40

2

T29

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T6

1

T40

2

T15

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T6

2

T40

1

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T6

2

T40

1

T29

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T29

1

T30

1

T20

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T6

11

T40

13

T41

13

auto[1]

1137

1

T6

9

T40

7

T41

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T6

6

T40

4

T41

3

from_0to1

540

1

T6

6

T40

5

T41

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T6

8

T40

10

T41

8

auto[1]

1097

1

T6

12

T40

10

T41

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T6

12

T40

8

T41

11

auto[1]

1095

1

T6

8

T40

12

T41

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T6

1

T41

1

T15

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T6

1

T40

1

T64

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T6

2

T40

1

T29

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T6

1

T41

1

T15

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T40

1

T41

1

T29

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T6

1

T40

1

T30

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T6

1

T41

2

T29

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T6

1

T40

1

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T40

1

T29

2

T15

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T40

1

T15

1

T64

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T30

2

T15

1

T64

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T6

1

T41

1

T29

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T6

1

T29

1

T30

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T29

1

T15

2

T20

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T6

2

T40

1

T29

1

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T40

1

T41

1

T30

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T6

7

T40

8

T41

10

auto[1]

1098

1

T6

13

T40

12

T41

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T6

5

T40

5

T41

5

from_0to1

514

1

T6

4

T40

6

T41

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1099

1

T6

11

T40

13

T41

7

auto[1]

1098

1

T6

9

T40

7

T41

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T6

8

T40

12

T41

11

auto[1]

1106

1

T6

12

T40

8

T41

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T40

1

T15

2

T108

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T6

2

T40

1

T15

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T40

1

T41

1

T64

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T40

1

T41

1

T29

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T6

1

T40

1

T15

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T6

1

T41

1

T29

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T41

2

T30

1

T15

3

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T6

1

T20

1

T34

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T40

1

T41

1

T15

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T6

2

T29

1

T15

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T41

1

T29

1

T30

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T6

1

T41

1

T30

3

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T6

1

T29

1

T15

3

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T40

1

T41

1

T29

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T40

4

T41

1

T29

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T41

1

T30

2

T64

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T6

13

T40

10

T41

7

auto[1]

1093

1

T6

7

T40

10

T41

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T6

3

T40

4

T41

6

from_0to1

525

1

T6

3

T40

3

T41

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T6

13

T40

7

T41

8

auto[1]

1126

1

T6

7

T40

13

T41

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T6

9

T40

12

T41

6

auto[1]

1067

1

T6

11

T40

8

T41

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T6

1

T40

2

T30

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T6

1

T40

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T30

2

T15

1

T108

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T6

1

T29

1

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T64

1

T20

3

T150

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T6

1

T41

2

T64

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T30

1

T108

3

T121

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T41

1

T29

2

T30

2

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T30

1

T15

1

T108

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T41

1

T29

3

T108

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T40

1

T41

1

T15

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T41

3

T30

2

T15

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T6

1

T40

1

T30

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T6

1

T40

1

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T40

1

T41

1

T29

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T41

1

T29

1

T15

1