Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153866	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116014

1

T4

235

T5

6

T6

70

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138552	1			T4	193		T5	3		T6	70
values[0x0]	65595	1			T4	278		T5	5		T6	32
values[0x1]	65733	1			T4	284		T5	4		T6	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124700	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145180

1

T4

298

T5

6

T6

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	900	1			T4	3		T41	2		T1	1
valid_sources[0x01]	1988	1			T4	2		T41	1		T1	3
valid_sources[0x02]	1738	1			T4	3		T1	1		T28	3
valid_sources[0x03]	986	1			T4	3		T1	1		T2	3
valid_sources[0x04]	1124	1			T4	6		T1	1		T25	7
valid_sources[0x05]	754	1			T4	3		T42	21		T1	1
valid_sources[0x06]	865	1			T4	1		T39	2		T42	22
valid_sources[0x07]	2913	1			T4	4		T6	3		T41	1
valid_sources[0x08]	1604	1			T4	2		T41	1		T1	2
valid_sources[0x09]	1127	1			T4	2		T6	3		T1	3
valid_sources[0x0a]	749	1			T4	4		T41	1		T1	2
valid_sources[0x0b]	978	1			T4	3		T1	2		T26	1
valid_sources[0x0c]	962	1			T4	3		T1	3		T2	1
valid_sources[0x0d]	720	1			T39	1		T40	1		T41	1
valid_sources[0x0e]	1187	1			T4	1		T39	1		T40	1
valid_sources[0x0f]	725	1			T4	1		T39	1		T1	1
valid_sources[0x10]	849	1			T4	3		T2	11		T28	3
valid_sources[0x11]	917	1			T4	3		T6	1		T40	7
valid_sources[0x12]	1257	1			T4	2		T42	7		T1	2
valid_sources[0x13]	927	1			T4	1		T41	1		T42	9
valid_sources[0x14]	1868	1			T4	4		T41	1		T1	1
valid_sources[0x15]	1126	1			T4	2		T41	1		T1	1
valid_sources[0x16]	957	1			T4	2		T42	9		T1	4
valid_sources[0x17]	742	1			T4	2		T39	2		T41	1
valid_sources[0x18]	1002	1			T41	1		T1	3		T28	6
valid_sources[0x19]	974	1			T4	4		T6	3		T39	1
valid_sources[0x1a]	864	1			T4	2		T40	3		T1	2
valid_sources[0x1b]	1074	1			T4	4		T6	6		T2	1
valid_sources[0x1c]	930	1			T4	4		T41	2		T2	1
valid_sources[0x1d]	1043	1			T4	1		T39	1		T41	1
valid_sources[0x1e]	1077	1			T4	4		T39	2		T42	4
valid_sources[0x1f]	1658	1			T4	4		T6	1		T40	3
valid_sources[0x20]	890	1			T4	8		T41	1		T42	3
valid_sources[0x21]	1206	1			T4	2		T41	1		T1	4
valid_sources[0x22]	2037	1			T4	2		T25	8		T2	4
valid_sources[0x23]	705	1			T4	3		T1	2		T25	3
valid_sources[0x24]	1066	1			T4	3		T39	1		T41	1
valid_sources[0x25]	2238	1			T4	1		T42	5		T1	2
valid_sources[0x26]	1050	1			T4	2		T41	1		T42	8
valid_sources[0x27]	938	1			T1	6		T2	2		T28	2
valid_sources[0x28]	1006	1			T4	2		T41	1		T25	12
valid_sources[0x29]	1114	1			T4	6		T6	1		T41	2
valid_sources[0x2a]	925	1			T4	3		T39	1		T42	8
valid_sources[0x2b]	872	1			T4	3		T42	1		T1	6
valid_sources[0x2c]	907	1			T4	2		T6	5		T41	1
valid_sources[0x2d]	1028	1			T4	2		T42	6		T1	2
valid_sources[0x2e]	791	1			T42	9		T1	2		T26	3
valid_sources[0x2f]	717	1			T4	2		T39	2		T42	4
valid_sources[0x30]	1460	1			T4	2		T5	1		T41	1
valid_sources[0x31]	1204	1			T4	4		T40	4		T41	2
valid_sources[0x32]	1384	1			T4	1		T40	2		T42	2
valid_sources[0x33]	794	1			T4	2		T42	15		T1	2
valid_sources[0x34]	813	1			T4	5		T6	1		T25	4
valid_sources[0x35]	898	1			T4	5		T42	2		T1	4
valid_sources[0x36]	2790	1			T4	6		T1	5		T25	2
valid_sources[0x37]	926	1			T4	2		T42	4		T1	1
valid_sources[0x38]	962	1			T4	2		T39	1		T41	1
valid_sources[0x39]	856	1			T4	5		T42	12		T1	3
valid_sources[0x3a]	1116	1			T4	5		T6	2		T1	3
valid_sources[0x3b]	933	1			T4	3		T5	1		T42	1
valid_sources[0x3c]	928	1			T4	3		T40	1		T42	9
valid_sources[0x3d]	1064	1			T4	1		T2	8		T28	5
valid_sources[0x3e]	924	1			T4	5		T42	11		T1	4
valid_sources[0x3f]	794	1			T4	1		T39	1		T42	17
valid_sources[0x40]	2112	1			T4	3		T41	1		T1	4
valid_sources[0x41]	796	1			T4	1		T1	2		T2	4
valid_sources[0x42]	883	1			T4	2		T39	3		T42	3
valid_sources[0x43]	952	1			T4	6		T41	1		T42	7
valid_sources[0x44]	813	1			T40	7		T41	5		T1	6
valid_sources[0x45]	925	1			T39	1		T41	1		T1	3
valid_sources[0x46]	959	1			T4	2		T41	1		T1	2
valid_sources[0x47]	833	1			T4	3		T41	1		T42	13
valid_sources[0x48]	907	1			T4	6		T1	1		T25	7
valid_sources[0x49]	1398	1			T4	2		T1	3		T28	3
valid_sources[0x4a]	798	1			T4	2		T1	2		T28	4
valid_sources[0x4b]	1104	1			T4	5		T42	8		T1	3
valid_sources[0x4c]	2001	1			T4	2		T1	3		T25	8
valid_sources[0x4d]	926	1			T4	3		T40	8		T1	3
valid_sources[0x4e]	988	1			T4	1		T42	11		T1	6
valid_sources[0x4f]	1100	1			T4	2		T41	1		T25	6
valid_sources[0x50]	1049	1			T4	7		T2	1		T28	3
valid_sources[0x51]	860	1			T4	3		T39	1		T42	1
valid_sources[0x52]	1628	1			T4	2		T42	9		T1	1
valid_sources[0x53]	829	1			T4	2		T1	7		T28	8
valid_sources[0x54]	1260	1			T6	3		T1	1		T25	12
valid_sources[0x55]	757	1			T4	2		T41	1		T1	2
valid_sources[0x56]	931	1			T4	9		T1	3		T28	5
valid_sources[0x57]	1006	1			T4	3		T42	3		T1	3
valid_sources[0x58]	962	1			T4	2		T39	4		T42	4
valid_sources[0x59]	1452	1			T41	1		T42	2		T1	3
valid_sources[0x5a]	865	1			T4	4		T6	1		T1	3
valid_sources[0x5b]	1222	1			T4	1		T6	1		T40	2
valid_sources[0x5c]	881	1			T4	2		T6	2		T42	7
valid_sources[0x5d]	1110	1			T4	5		T40	6		T41	1
valid_sources[0x5e]	832	1			T4	6		T39	1		T40	2
valid_sources[0x5f]	812	1			T4	5		T41	1		T42	4
valid_sources[0x60]	1844	1			T4	5		T41	1		T42	2
valid_sources[0x61]	971	1			T4	4		T1	1		T2	4
valid_sources[0x62]	733	1			T4	5		T39	1		T1	2
valid_sources[0x63]	1687	1			T42	4		T1	3		T2	5
valid_sources[0x64]	721	1			T4	4		T41	1		T1	3
valid_sources[0x65]	717	1			T4	1		T5	1		T25	6
valid_sources[0x66]	842	1			T4	3		T1	2		T2	8
valid_sources[0x67]	1124	1			T4	2		T6	6		T43	17
valid_sources[0x68]	744	1			T4	3		T39	1		T1	2
valid_sources[0x69]	2078	1			T4	3		T40	6		T41	1
valid_sources[0x6a]	975	1			T4	4		T42	2		T25	4
valid_sources[0x6b]	844	1			T4	3		T41	1		T1	3
valid_sources[0x6c]	761	1			T4	2		T1	1		T25	4
valid_sources[0x6d]	1128	1			T4	9		T41	4		T1	1
valid_sources[0x6e]	2314	1			T4	7		T2	1		T7	1330
valid_sources[0x6f]	739	1			T4	3		T39	1		T1	1
valid_sources[0x70]	850	1			T4	5		T42	3		T1	7
valid_sources[0x71]	713	1			T4	1		T1	4		T25	3
valid_sources[0x72]	1402	1			T4	3		T42	17		T25	7
valid_sources[0x73]	1551	1			T4	1		T39	1		T1	1
valid_sources[0x74]	705	1			T4	4		T42	9		T1	4
valid_sources[0x75]	1000	1			T4	3		T5	1		T40	8
valid_sources[0x76]	2176	1			T4	4		T25	4		T26	1
valid_sources[0x77]	733	1			T4	5		T6	4		T42	8
valid_sources[0x78]	685	1			T4	2		T25	7		T2	2
valid_sources[0x79]	961	1			T4	2		T6	2		T41	1
valid_sources[0x7a]	1153	1			T4	2		T42	6		T1	1
valid_sources[0x7b]	1085	1			T6	1		T41	2		T42	3
valid_sources[0x7c]	1682	1			T4	1		T39	1		T1	4
valid_sources[0x7d]	1781	1			T4	3		T6	1		T1	2
valid_sources[0x7e]	1012	1			T4	1		T40	5		T1	3
valid_sources[0x7f]	1370	1			T4	5		T6	1		T41	1
valid_sources[0x80]	1072	1			T4	4		T42	1		T1	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61977

1

T4

104

T5

2

T6

43

values[0x0]

all_enables

biggest_size

31664

1

T4

82

T5

3

T6

17

values[0x1]

all_enables

biggest_size

22373

1

T4

49

T5

1

T6

10