Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T39
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T51,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T50,T51,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T51,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T51,T15
1	0	Covered	T4,T6,T39
1	1	Covered	T50,T51,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T51,T20
0	1	Covered	T15,T38,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T51,T20
0	1	Covered	T50,T51,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T51,T20
1	-	Covered	T50,T51,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T50,T51,T15
DetectSt	168	Covered	T50,T51,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T50,T51,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T50,T51,T15
DebounceSt->IdleSt	163	Covered	T15,T22,T61
DetectSt->IdleSt	186	Covered	T15,T38,T99
DetectSt->StableSt	191	Covered	T50,T51,T20
IdleSt->DebounceSt	148	Covered	T50,T51,T15
StableSt->IdleSt	206	Covered	T50,T51,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T50,T51,T15
0	1	Covered	T50,T51,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T50,T51,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T50,T51,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T51,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T22,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T51,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T38,T99
DetectSt	-	-	-	-	0	1	-	Covered	T50,T51,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T50,T51,T20
StableSt	-	-	-	-	-	-	0	Covered	T50,T51,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	329	0	0
CntIncr_A	5957637	265603	0	0
CntNoWrap_A	5957637	5338670	0	0
DetectStDropOut_A	5957637	4	0	0
DetectedOut_A	5957637	1047	0	0
DetectedPulseOut_A	5957637	148	0	0
DisabledIdleSt_A	5957637	5065686	0	0
DisabledNoDetection_A	5957637	5067916	0	0
EnterDebounceSt_A	5957637	182	0	0
EnterDetectSt_A	5957637	152	0	0
EnterStableSt_A	5957637	148	0	0
PulseIsPulse_A	5957637	148	0	0
StayInStableSt	5957637	898	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	6634	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	147	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	329	0	0
T14	3545	0	0	0
T15	14678	4	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	4	0	0
T22	0	1	0	0
T34	0	10	0	0
T48	490	0	0	0
T50	59196	6	0	0
T51	49736	4	0	0
T58	0	4	0	0
T60	0	4	0	0
T61	0	4	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	265603	0	0
T14	3545	0	0	0
T15	14678	134	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	42	0	0
T22	0	64	0	0
T34	0	160	0	0
T48	490	0	0	0
T50	59196	58654	0	0
T51	49736	49151	0	0
T58	0	4649	0	0
T60	0	112	0	0
T61	0	119	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338670	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T38	0	1	0	0
T49	494	0	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T99	0	1	0	0
T104	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1047	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	17	0	0
T34	0	31	0	0
T38	0	3	0	0
T48	490	0	0	0
T50	59196	25	0	0
T51	49736	16	0	0
T58	0	14	0	0
T60	0	9	0	0
T61	0	12	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	9	0	0
T111	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	148	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	2	0	0
T34	0	5	0	0
T38	0	1	0	0
T48	490	0	0	0
T50	59196	3	0	0
T51	49736	2	0	0
T58	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	1	0	0
T111	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5065686	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5067916	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	182	0	0
T14	3545	0	0	0
T15	14678	3	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T34	0	5	0	0
T48	490	0	0	0
T50	59196	3	0	0
T51	49736	2	0	0
T58	0	2	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	152	0	0
T14	3545	0	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	2	0	0
T34	0	5	0	0
T48	490	0	0	0
T50	59196	3	0	0
T51	49736	2	0	0
T58	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	1	0	0
T111	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	148	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	2	0	0
T34	0	5	0	0
T38	0	1	0	0
T48	490	0	0	0
T50	59196	3	0	0
T51	49736	2	0	0
T58	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	1	0	0
T111	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	148	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	2	0	0
T34	0	5	0	0
T38	0	1	0	0
T48	490	0	0	0
T50	59196	3	0	0
T51	49736	2	0	0
T58	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	1	0	0
T111	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	898	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	15	0	0
T34	0	26	0	0
T38	0	2	0	0
T48	490	0	0	0
T50	59196	22	0	0
T51	49736	14	0	0
T58	0	12	0	0
T60	0	7	0	0
T61	0	11	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	8	0	0
T111	0	20	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	6634	0	0
T1	17765	11	0	0
T2	0	32	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	4	0	0
T25	24867	16	0	0
T26	0	3	0	0
T39	524	5	0	0
T40	2405	6	0	0
T41	503	5	0	0
T42	11915	27	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	147	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	2	0	0
T34	0	5	0	0
T38	0	1	0	0
T48	490	0	0	0
T50	59196	3	0	0
T51	49736	2	0	0
T58	0	2	0	0
T60	0	2	0	0
T61	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T92	0	1	0	0
T111	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T39
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T16,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T16
1	0	Covered	T4,T6,T39
1	1	Covered	T3,T9,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T16,T19
0	1	Covered	T34,T37,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T16,T19
0	1	Unreachable
1	0	Covered	T9,T16,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T16
DetectSt	168	Covered	T9,T16,T19
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T16,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T16,T19
DebounceSt->IdleSt	163	Covered	T3,T34,T36
DetectSt->IdleSt	186	Covered	T34,T37,T91
DetectSt->StableSt	191	Covered	T9,T16,T19
IdleSt->DebounceSt	148	Covered	T3,T9,T16
StableSt->IdleSt	206	Covered	T9,T16,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T16
0	1	Covered	T3,T9,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T16,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T16,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T34,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T16
DetectSt	-	-	-	-	1	-	-	Covered	T34,T37,T91
DetectSt	-	-	-	-	0	1	-	Covered	T9,T16,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T16,T19
StableSt	-	-	-	-	-	-	0	Covered	T9,T16,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	189	0	0
CntIncr_A	5957637	61408	0	0
CntNoWrap_A	5957637	5338810	0	0
DetectStDropOut_A	5957637	18	0	0
DetectedOut_A	5957637	145106	0	0
DetectedPulseOut_A	5957637	60	0	0
DisabledIdleSt_A	5957637	4635272	0	0
DisabledNoDetection_A	5957637	4637568	0	0
EnterDebounceSt_A	5957637	112	0	0
EnterDetectSt_A	5957637	78	0	0
EnterStableSt_A	5957637	60	0	0
PulseIsPulse_A	5957637	60	0	0
StayInStableSt	5957637	145046	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	6634	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_sticky_sva.StableStDropOut_A	5957637	464866	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	189	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	2	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	2	0	0
T19	0	2	0	0
T20	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	7	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	6	0	0
T38	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	61408	0	0
T3	1152	29	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	22	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	58	0	0
T19	0	58	0	0
T20	0	52	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	60	0	0
T35	0	97	0	0
T36	0	34	0	0
T37	0	105	0	0
T38	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338810	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	18	0	0
T34	9620	2	0	0
T35	1461	0	0	0
T37	0	3	0	0
T70	492	0	0	0
T91	0	3	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	6	0	0
T119	0	1	0	0
T120	443	0	0	0
T121	504	0	0	0
T122	422	0	0	0
T123	525	0	0	0
T124	463	0	0	0
T125	12493	0	0	0
T126	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	145106	0	0
T9	685	11	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	235	0	0
T19	0	158	0	0
T20	0	140	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	18	0	0
T35	0	78	0	0
T38	0	400	0	0
T75	6216	0	0	0
T113	0	35	0	0
T114	0	305	0	0
T115	0	961	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T75	6216	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4635272	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4637568	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	112	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	78	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	3	0	0
T35	0	1	0	0
T37	0	3	0	0
T38	0	1	0	0
T75	6216	0	0	0
T91	0	3	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T75	6216	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T75	6216	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	145046	0	0
T9	685	10	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	234	0	0
T19	0	157	0	0
T20	0	139	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	17	0	0
T35	0	77	0	0
T38	0	399	0	0
T75	6216	0	0	0
T113	0	34	0	0
T114	0	304	0	0
T115	0	958	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	6634	0	0
T1	17765	11	0	0
T2	0	32	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	4	0	0
T25	24867	16	0	0
T26	0	3	0	0
T39	524	5	0	0
T40	2405	6	0	0
T41	503	5	0	0
T42	11915	27	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	464866	0	0
T9	685	84	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T16	0	66545	0	0
T19	0	130	0	0
T20	0	136	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	86	0	0
T35	0	30	0	0
T38	0	126	0	0
T75	6216	0	0	0
T113	0	42	0	0
T114	0	311	0	0
T115	0	1223	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T39,T40
1	1	Covered	T6,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T19,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T16
1	0	Covered	T6,T39,T40
1	1	Covered	T3,T9,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T34
0	1	Covered	T19,T81,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T19,T34
0	1	Unreachable
1	0	Covered	T9,T19,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T16
DetectSt	168	Covered	T9,T19,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T19,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T19,T34
DebounceSt->IdleSt	163	Covered	T3,T16,T20
DetectSt->IdleSt	186	Covered	T19,T81,T90
DetectSt->StableSt	191	Covered	T9,T19,T34
IdleSt->DebounceSt	148	Covered	T3,T9,T16
StableSt->IdleSt	206	Covered	T9,T19,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T16
0	1	Covered	T3,T9,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T19,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T16
IdleSt	0	-	-	-	-	-	-	Covered	T6,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T19,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T16,T20
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T16
DetectSt	-	-	-	-	1	-	-	Covered	T19,T81,T90
DetectSt	-	-	-	-	0	1	-	Covered	T9,T19,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T19,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T19,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	197	0	0
CntIncr_A	5957637	164036	0	0
CntNoWrap_A	5957637	5338802	0	0
DetectStDropOut_A	5957637	18	0	0
DetectedOut_A	5957637	254768	0	0
DetectedPulseOut_A	5957637	50	0	0
DisabledIdleSt_A	5957637	4635272	0	0
DisabledNoDetection_A	5957637	4637568	0	0
EnterDebounceSt_A	5957637	130	0	0
EnterDetectSt_A	5957637	68	0	0
EnterStableSt_A	5957637	50	0	0
PulseIsPulse_A	5957637	50	0	0
StayInStableSt	5957637	254718	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_sticky_sva.StableStDropOut_A	5957637	66640	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	197	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	2	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	4	0	0
T19	0	4	0	0
T20	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	164036	0	0
T3	1152	73	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	85	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	376	0	0
T19	0	186	0	0
T20	0	56	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	37	0	0
T35	0	79	0	0
T36	0	97	0	0
T37	0	41	0	0
T38	0	336	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338802	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	18	0	0
T19	16760	1	0	0
T20	21299	0	0	0
T67	496	0	0	0
T68	499	0	0	0
T69	2415	0	0	0
T81	0	4	0	0
T90	0	2	0	0
T107	694	0	0	0
T108	504	0	0	0
T109	422	0	0	0
T110	17716	0	0	0
T118	0	4	0	0
T127	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	254768	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T19	0	96	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	154	0	0
T35	0	5	0	0
T36	0	6	0	0
T37	0	159	0	0
T75	6216	0	0	0
T81	0	298	0	0
T91	0	23474	0	0
T112	0	32	0	0
T114	0	467	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	50	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T19	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T75	6216	0	0	0
T81	0	2	0	0
T91	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4635272	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4637568	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	130	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	4	0	0
T19	0	2	0	0
T20	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	68	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T19	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T75	6216	0	0	0
T81	0	6	0	0
T91	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	50	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T19	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T75	6216	0	0	0
T81	0	2	0	0
T91	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	50	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T19	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T75	6216	0	0	0
T81	0	2	0	0
T91	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	254718	0	0
T19	16760	95	0	0
T20	21299	0	0	0
T34	0	153	0	0
T35	0	4	0	0
T36	0	5	0	0
T37	0	158	0	0
T67	496	0	0	0
T68	499	0	0	0
T69	2415	0	0	0
T81	0	296	0	0
T91	0	23473	0	0
T107	694	0	0	0
T108	504	0	0	0
T109	422	0	0	0
T110	17716	0	0	0
T112	0	31	0	0
T114	0	466	0	0
T131	404	0	0	0
T132	0	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	66640	0	0
T9	685	28	0	0
T10	638	0	0	0
T11	46616	0	0	0
T12	650	0	0	0
T19	0	43	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T34	0	93	0	0
T35	0	133	0	0
T36	0	78	0	0
T37	0	109	0	0
T75	6216	0	0	0
T81	0	362	0	0
T91	0	103	0	0
T112	0	35	0	0
T114	0	117	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T39

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T9,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T9,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T16
1	0	Covered	T4,T6,T39
1	1	Covered	T3,T9,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T16
0	1	Covered	T19,T37,T38
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T16
0	1	Unreachable
1	0	Covered	T3,T9,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T16
DetectSt	168	Covered	T3,T9,T16
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T9,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T16
DebounceSt->IdleSt	163	Covered	T19,T20,T81
DetectSt->IdleSt	186	Covered	T19,T37,T38
DetectSt->StableSt	191	Covered	T3,T9,T16
IdleSt->DebounceSt	148	Covered	T3,T9,T16
StableSt->IdleSt	206	Covered	T3,T9,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T16
0	1	Covered	T3,T9,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T16
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T39
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T20,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T16
DetectSt	-	-	-	-	1	-	-	Covered	T19,T37,T38
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T16
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T16
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	207	0	0
CntIncr_A	5957637	26626	0	0
CntNoWrap_A	5957637	5338792	0	0
DetectStDropOut_A	5957637	26	0	0
DetectedOut_A	5957637	70725	0	0
DetectedPulseOut_A	5957637	59	0	0
DisabledIdleSt_A	5957637	4635272	0	0
DisabledNoDetection_A	5957637	4637568	0	0
EnterDebounceSt_A	5957637	123	0	0
EnterDetectSt_A	5957637	85	0	0
EnterStableSt_A	5957637	59	0	0
PulseIsPulse_A	5957637	59	0	0
StayInStableSt	5957637	70666	0	0
gen_high_event_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_sticky_sva.StableStDropOut_A	5957637	427409	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	207	0	0
T3	1152	2	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	2	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	2	0	0
T19	0	5	0	0
T20	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	6	0	0
T38	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	26626	0	0
T3	1152	69	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	11	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	9744	0	0
T19	0	120	0	0
T20	0	104	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	34	0	0
T35	0	92	0	0
T36	0	83	0	0
T37	0	270	0	0
T38	0	220	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338792	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	26	0	0
T19	16760	2	0	0
T20	21299	0	0	0
T37	0	3	0	0
T38	0	4	0	0
T67	496	0	0	0
T68	499	0	0	0
T69	2415	0	0	0
T107	694	0	0	0
T108	504	0	0	0
T109	422	0	0	0
T110	17716	0	0	0
T131	404	0	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0
T139	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	70725	0	0
T3	1152	22	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	4	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	56934	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	195	0	0
T35	0	1	0	0
T36	0	66	0	0
T91	0	136	0	0
T112	0	51	0	0
T113	0	44	0	0
T114	0	490	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	59	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T91	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4635272	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4637568	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	123	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	85	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	1	0	0
T19	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	3	0	0
T38	0	4	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	59	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T91	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	59	0	0
T3	1152	1	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	1	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T91	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	70666	0	0
T3	1152	21	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	3	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	56933	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	194	0	0
T36	0	65	0	0
T91	0	135	0	0
T112	0	50	0	0
T113	0	43	0	0
T114	0	489	0	0
T115	0	1207	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	427409	0	0
T3	1152	65	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	119	0	0
T10	638	0	0	0
T11	46616	0	0	0
T16	0	169	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T34	0	57	0	0
T35	0	132	0	0
T36	0	52	0	0
T91	0	27985	0	0
T112	0	31	0	0
T113	0	40	0	0
T114	0	121	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T17,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T17,T20
0	1	Not Covered
1	0	Covered	T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T17,T20
0	1	Covered	T20,T22,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T17,T20
1	-	Covered	T20,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T17,T20
DetectSt	168	Covered	T8,T17,T20
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T17,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T17,T20
DebounceSt->IdleSt	163	Covered	T55,T85,T140
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T8,T17,T20
IdleSt->DebounceSt	148	Covered	T8,T17,T20
StableSt->IdleSt	206	Covered	T20,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T17,T20
0	1	Covered	T8,T17,T20
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T17,T20
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T17,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T17,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T140,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T17,T20
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T8,T17,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T8,T17,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	68	0	0
CntIncr_A	5957637	25079	0	0
CntNoWrap_A	5957637	5338931	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	36494	0	0
DetectedPulseOut_A	5957637	31	0	0
DisabledIdleSt_A	5957637	5182414	0	0
DisabledNoDetection_A	5957637	5184657	0	0
EnterDebounceSt_A	5957637	36	0	0
EnterDetectSt_A	5957637	32	0	0
EnterStableSt_A	5957637	31	0	0
PulseIsPulse_A	5957637	31	0	0
StayInStableSt	5957637	36448	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	68	0	0
T8	580	2	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	2	0	0
T20	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	3	0	0
T81	0	2	0	0
T84	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	25079	0	0
T8	580	66	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	86	0	0
T20	0	67	0	0
T22	0	776	0	0
T23	0	65	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	52	0	0
T81	0	62	0	0
T84	0	41	0	0
T142	0	46	0	0
T143	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338931	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36494	0	0
T8	580	44	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	41	0	0
T20	0	44	0	0
T22	0	42	0	0
T23	0	30	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	40	0	0
T81	0	111	0	0
T127	0	41	0	0
T142	0	87	0	0
T143	0	266	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	1	0	0
T81	0	1	0	0
T127	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5182414	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5184657	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T81	0	1	0	0
T84	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	32	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	1	0	0
T81	0	1	0	0
T127	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	1	0	0
T81	0	1	0	0
T127	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36448	0	0
T8	580	42	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T17	0	39	0	0
T20	0	43	0	0
T22	0	41	0	0
T23	0	29	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	39	0	0
T81	0	110	0	0
T127	0	39	0	0
T142	0	85	0	0
T143	0	264	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	16	0	0
T20	21299	1	0	0
T21	651	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	1	0	0
T70	492	0	0	0
T81	0	1	0	0
T83	27038	0	0	0
T120	443	0	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	36136	0	0	0
T150	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T10,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T12
1	0	Covered	T6,T39,T40
1	1	Covered	T8,T10,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T23,T24
0	1	Covered	T10,T23,T53
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T23,T24
1	-	Covered	T10,T23,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T17
DetectSt	168	Covered	T10,T23,T24
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T23,T24
DebounceSt->IdleSt	163	Covered	T8,T10,T17
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T23,T24
IdleSt->DebounceSt	148	Covered	T8,T10,T17
StableSt->IdleSt	206	Covered	T10,T23,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T17
0	1	Covered	T8,T10,T17
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T23,T24
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T17
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T17
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T23,T53
StableSt	-	-	-	-	-	-	0	Covered	T10,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	86	0	0
CntIncr_A	5957637	19348	0	0
CntNoWrap_A	5957637	5338913	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	28852	0	0
DetectedPulseOut_A	5957637	40	0	0
DisabledIdleSt_A	5957637	5284965	0	0
DisabledNoDetection_A	5957637	5287214	0	0
EnterDebounceSt_A	5957637	46	0	0
EnterDetectSt_A	5957637	40	0	0
EnterStableSt_A	5957637	40	0	0
PulseIsPulse_A	5957637	40	0	0
StayInStableSt	5957637	28787	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	2482	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	86	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	3	0	0
T11	46616	0	0	0
T17	0	1	0	0
T23	0	4	0	0
T24	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	4	0	0
T54	0	2	0	0
T88	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	19348	0	0
T8	580	66	0	0
T9	685	0	0	0
T10	638	38	0	0
T11	46616	0	0	0
T17	0	86	0	0
T23	0	130	0	0
T24	0	11	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	150	0	0
T54	0	47	0	0
T88	0	23	0	0
T151	0	25	0	0
T152	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338913	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	28852	0	0
T10	638	51	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	112	0	0
T24	0	112	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	123	0	0
T54	0	39	0	0
T75	6216	0	0	0
T81	0	368	0	0
T88	0	69	0	0
T151	0	77	0	0
T152	0	399	0	0
T153	0	222	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	40	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T75	6216	0	0	0
T81	0	4	0	0
T88	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5284965	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5287214	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	46	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T17	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T88	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	40	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T75	6216	0	0	0
T81	0	4	0	0
T88	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	40	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T75	6216	0	0	0
T81	0	4	0	0
T88	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	40	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T54	0	1	0	0
T75	6216	0	0	0
T81	0	4	0	0
T88	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	28787	0	0
T10	638	50	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	109	0	0
T24	0	110	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	121	0	0
T54	0	37	0	0
T75	6216	0	0	0
T81	0	361	0	0
T88	0	68	0	0
T151	0	75	0	0
T152	0	397	0	0
T153	0	220	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2482	0	0
T1	17765	0	0	0
T6	1976	4	0	0
T8	0	1	0	0
T10	0	2	0	0
T14	0	4	0	0
T25	24867	0	0	0
T26	440	4	0	0
T27	411	0	0	0
T29	0	7	0	0
T30	0	4	0	0
T39	524	6	0	0
T40	2405	4	0	0
T41	503	8	0	0
T42	11915	0	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	14	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T75	6216	0	0	0
T81	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T127	0	1	0	0
T143	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0