Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T24,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T20,T24,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T24,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T24
1	0	Covered	T4,T5,T6
1	1	Covered	T20,T24,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T57
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T57
0	1	Covered	T55,T137,T89
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T24,T57
1	-	Covered	T55,T137,T89

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T24,T57
DetectSt	168	Covered	T20,T24,T57
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T20,T24,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T24,T57
DebounceSt->IdleSt	163	Covered	T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T20,T24,T57
IdleSt->DebounceSt	148	Covered	T20,T24,T57
StableSt->IdleSt	206	Covered	T20,T55,T88

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T24,T57
0	1	Covered	T20,T24,T57
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T24,T57
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T24,T57
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T24,T57
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T24,T57
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T20,T24,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T55,T84,T137
StableSt	-	-	-	-	-	-	0	Covered	T20,T24,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	73	0	0
CntIncr_A	5957637	1870	0	0
CntNoWrap_A	5957637	5338926	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	2963	0	0
DetectedPulseOut_A	5957637	36	0	0
DisabledIdleSt_A	5957637	5324679	0	0
DisabledNoDetection_A	5957637	5326932	0	0
EnterDebounceSt_A	5957637	37	0	0
EnterDetectSt_A	5957637	36	0	0
EnterStableSt_A	5957637	36	0	0
PulseIsPulse_A	5957637	36	0	0
StayInStableSt	5957637	2901	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	73	0	0
T20	21299	2	0	0
T21	651	0	0	0
T24	0	2	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	2	0	0
T57	0	2	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	2	0	0
T88	0	2	0	0
T120	443	0	0	0
T143	0	2	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1870	0	0
T20	21299	67	0	0
T21	651	0	0	0
T24	0	11	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	26	0	0
T57	0	60	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	41	0	0
T88	0	23	0	0
T120	443	0	0	0
T143	0	69	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	91	0	0
T155	0	33	0	0
T156	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338926	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2963	0	0
T20	21299	43	0	0
T21	651	0	0	0
T24	0	112	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	3	0	0
T57	0	38	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	1	0	0
T88	0	42	0	0
T120	443	0	0	0
T143	0	38	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	131	0	0
T155	0	43	0	0
T156	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36	0	0
T20	21299	1	0	0
T21	651	0	0	0
T24	0	1	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	1	0	0
T88	0	1	0	0
T120	443	0	0	0
T143	0	1	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5324679	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5326932	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	37	0	0
T20	21299	1	0	0
T21	651	0	0	0
T24	0	1	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	1	0	0
T88	0	1	0	0
T120	443	0	0	0
T143	0	1	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36	0	0
T20	21299	1	0	0
T21	651	0	0	0
T24	0	1	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	1	0	0
T88	0	1	0	0
T120	443	0	0	0
T143	0	1	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36	0	0
T20	21299	1	0	0
T21	651	0	0	0
T24	0	1	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	1	0	0
T88	0	1	0	0
T120	443	0	0	0
T143	0	1	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	36	0	0
T20	21299	1	0	0
T21	651	0	0	0
T24	0	1	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T70	492	0	0	0
T83	27038	0	0	0
T84	0	1	0	0
T88	0	1	0	0
T120	443	0	0	0
T143	0	1	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2901	0	0
T20	21299	41	0	0
T21	651	0	0	0
T24	0	110	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T52	28974	0	0	0
T55	0	2	0	0
T57	0	36	0	0
T70	492	0	0	0
T83	27038	0	0	0
T88	0	40	0	0
T120	443	0	0	0
T143	0	36	0	0
T149	36136	0	0	0
T150	502	0	0	0
T152	0	129	0	0
T155	0	41	0	0
T156	0	36	0	0
T157	0	310	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	9	0	0
T55	706	1	0	0
T89	0	1	0	0
T113	694	0	0	0
T114	2536	0	0	0
T137	0	1	0	0
T151	607	0	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	489	0	0	0
T164	747	0	0	0
T165	417	0	0	0
T166	495	0	0	0
T167	1170	0	0	0
T168	410	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T21,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T21
1	0	Covered	T6,T39,T40
1	1	Covered	T12,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T56
0	1	Covered	T154,T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T21,T56
0	1	Covered	T12,T56,T55
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T21,T56
1	-	Covered	T12,T56,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T20,T21
DetectSt	168	Covered	T12,T21,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T21,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T21,T56
DebounceSt->IdleSt	163	Covered	T20,T23,T56
DetectSt->IdleSt	186	Covered	T154,T160
DetectSt->StableSt	191	Covered	T12,T21,T56
IdleSt->DebounceSt	148	Covered	T12,T20,T21
StableSt->IdleSt	206	Covered	T12,T56,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T20,T21
0	1	Covered	T12,T20,T21
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T21,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T21,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T23,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T154,T160
DetectSt	-	-	-	-	0	1	-	Covered	T12,T21,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T56,T55
StableSt	-	-	-	-	-	-	0	Covered	T12,T21,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	111	0	0
CntIncr_A	5957637	19821	0	0
CntNoWrap_A	5957637	5338888	0	0
DetectStDropOut_A	5957637	2	0	0
DetectedOut_A	5957637	10723	0	0
DetectedPulseOut_A	5957637	49	0	0
DisabledIdleSt_A	5957637	5284271	0	0
DisabledNoDetection_A	5957637	5286521	0	0
EnterDebounceSt_A	5957637	60	0	0
EnterDetectSt_A	5957637	51	0	0
EnterStableSt_A	5957637	49	0	0
PulseIsPulse_A	5957637	49	0	0
StayInStableSt	5957637	10650	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	2733	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	111	0	0
T12	650	4	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T23	0	1	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	4	0	0
T56	0	9	0	0
T62	402	0	0	0
T81	0	7	0	0
T153	0	4	0	0
T155	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	19821	0	0
T12	650	76	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	67	0	0
T21	0	68	0	0
T23	0	65	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	52	0	0
T56	0	329	0	0
T62	402	0	0	0
T81	0	176	0	0
T153	0	82	0	0
T155	0	33	0	0
T169	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338888	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2	0	0
T145	699	0	0	0
T154	604	1	0	0
T160	0	1	0	0
T170	422	0	0	0
T171	12872	0	0	0
T172	424	0	0	0
T173	428	0	0	0
T174	7599	0	0	0
T175	10790	0	0	0
T176	417	0	0	0
T177	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	10723	0	0
T12	650	86	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T21	0	41	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	165	0	0
T56	0	175	0	0
T62	402	0	0	0
T81	0	279	0	0
T90	0	82	0	0
T153	0	128	0	0
T155	0	1	0	0
T169	0	33	0	0
T178	0	131	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	49	0	0
T12	650	2	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T21	0	1	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T62	402	0	0	0
T81	0	3	0	0
T90	0	2	0	0
T153	0	2	0	0
T155	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5284271	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5286521	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T12	650	2	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	2	0	0
T56	0	5	0	0
T62	402	0	0	0
T81	0	4	0	0
T153	0	2	0	0
T155	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	51	0	0
T12	650	2	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T21	0	1	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T62	402	0	0	0
T81	0	3	0	0
T90	0	2	0	0
T153	0	2	0	0
T155	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	49	0	0
T12	650	2	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T21	0	1	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T62	402	0	0	0
T81	0	3	0	0
T90	0	2	0	0
T153	0	2	0	0
T155	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	49	0	0
T12	650	2	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T21	0	1	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T62	402	0	0	0
T81	0	3	0	0
T90	0	2	0	0
T153	0	2	0	0
T155	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	10650	0	0
T12	650	83	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T21	0	39	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	162	0	0
T56	0	168	0	0
T62	402	0	0	0
T81	0	273	0	0
T90	0	79	0	0
T153	0	125	0	0
T156	0	37	0	0
T169	0	32	0	0
T178	0	129	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2733	0	0
T1	17765	0	0	0
T6	1976	8	0	0
T10	0	2	0	0
T12	0	2	0	0
T25	24867	0	0	0
T26	440	5	0	0
T27	411	0	0	0
T29	0	6	0	0
T30	0	6	0	0
T33	0	4	0	0
T39	524	6	0	0
T40	2405	12	0	0
T41	503	4	0	0
T42	11915	0	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	25	0	0
T12	650	1	0	0
T13	23539	0	0	0
T14	3545	0	0	0
T15	14678	0	0	0
T16	67283	0	0	0
T17	840	0	0	0
T48	490	0	0	0
T50	59196	0	0	0
T51	49736	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	402	0	0	0
T90	0	1	0	0
T153	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T39

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T39
1	1	Covered	T4,T6,T39

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T15,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T15,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T15,T20
1	0	Covered	T4,T6,T39
1	1	Covered	T8,T15,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T21
0	1	Covered	T89,T181,T182
1	0	Covered	T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T21
0	1	Covered	T15,T22,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T20,T21
1	-	Covered	T15,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T15,T20
DetectSt	168	Covered	T15,T20,T21
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T20,T21
DebounceSt->IdleSt	163	Covered	T8,T22,T157
DetectSt->IdleSt	186	Covered	T84,T89,T181
DetectSt->StableSt	191	Covered	T15,T20,T21
IdleSt->DebounceSt	148	Covered	T8,T15,T20
StableSt->IdleSt	206	Covered	T15,T20,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T15,T20
0	1	Covered	T8,T15,T20
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T20,T21
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T15,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T39
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T157,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T15,T20
DetectSt	-	-	-	-	1	-	-	Covered	T84,T89,T181
DetectSt	-	-	-	-	0	1	-	Covered	T15,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T15,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	129	0	0
CntIncr_A	5957637	55643	0	0
CntNoWrap_A	5957637	5338870	0	0
DetectStDropOut_A	5957637	3	0	0
DetectedOut_A	5957637	38771	0	0
DetectedPulseOut_A	5957637	58	0	0
DisabledIdleSt_A	5957637	5176409	0	0
DisabledNoDetection_A	5957637	5178652	0	0
EnterDebounceSt_A	5957637	68	0	0
EnterDetectSt_A	5957637	62	0	0
EnterStableSt_A	5957637	58	0	0
PulseIsPulse_A	5957637	58	0	0
StayInStableSt	5957637	38687	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	129	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	4	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T55	0	4	0	0
T56	0	6	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	55643	0	0
T8	580	66	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	48	0	0
T20	0	67	0	0
T21	0	68	0	0
T22	0	1286	0	0
T23	0	65	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	75	0	0
T55	0	52	0	0
T56	0	170	0	0
T151	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338870	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	3	0	0
T89	1268	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	41078	0	0	0
T184	524	0	0	0
T185	937	0	0	0
T186	25496	0	0	0
T187	81778	0	0	0
T188	702	0	0	0
T189	638	0	0	0
T190	504	0	0	0
T191	786	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	38771	0	0
T15	14678	57	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	105	0	0
T21	0	173	0	0
T22	0	43	0	0
T23	0	169	0	0
T49	494	0	0	0
T53	0	191	0	0
T55	0	140	0	0
T56	0	416	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T88	0	81	0	0
T151	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	58	0	0
T15	14678	2	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	494	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T88	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5176409	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5178652	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	68	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	62	0	0
T15	14678	2	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	494	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T88	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	58	0	0
T15	14678	2	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	494	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T88	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	58	0	0
T15	14678	2	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	494	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	3	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T88	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	38687	0	0
T15	14678	54	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	103	0	0
T21	0	171	0	0
T22	0	42	0	0
T23	0	168	0	0
T49	494	0	0	0
T53	0	190	0	0
T55	0	138	0	0
T56	0	411	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T88	0	80	0	0
T151	0	75	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	32	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T49	494	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	1	0	0
T88	0	1	0	0
T142	0	1	0	0
T153	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T39
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T15,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T15,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T15,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T15,T20
1	0	Covered	T4,T6,T39
1	1	Covered	T8,T15,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T15,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T15,T24
0	1	Covered	T15,T24,T146
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T15,T24
1	-	Covered	T15,T24,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T15,T24
DetectSt	168	Covered	T8,T15,T24
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T15,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T15,T24
DebounceSt->IdleSt	163	Covered	T81,T85,T192
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T15,T24
IdleSt->DebounceSt	148	Covered	T8,T15,T24
StableSt->IdleSt	206	Covered	T15,T24,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T15,T24
0	1	Covered	T8,T15,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T24
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T15,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T15,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T192
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T15,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T15,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T24,T84
StableSt	-	-	-	-	-	-	0	Covered	T8,T15,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	66	0	0
CntIncr_A	5957637	38334	0	0
CntNoWrap_A	5957637	5338933	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	17939	0	0
DetectedPulseOut_A	5957637	32	0	0
DisabledIdleSt_A	5957637	5183055	0	0
DisabledNoDetection_A	5957637	5185305	0	0
EnterDebounceSt_A	5957637	34	0	0
EnterDetectSt_A	5957637	32	0	0
EnterStableSt_A	5957637	32	0	0
PulseIsPulse_A	5957637	32	0	0
StayInStableSt	5957637	17887	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	6415	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	66	0	0
T8	580	2	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	2	0	0
T24	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T56	0	2	0	0
T81	0	2	0	0
T84	0	2	0	0
T90	0	2	0	0
T142	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	38334	0	0
T8	580	66	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	24	0	0
T24	0	11	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	75	0	0
T56	0	76	0	0
T81	0	13	0	0
T84	0	41	0	0
T90	0	53	0	0
T142	0	46	0	0
T156	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338933	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	17939	0	0
T8	580	43	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	84	0	0
T24	0	42	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	378	0	0
T56	0	59	0	0
T81	0	56	0	0
T84	0	1	0	0
T90	0	227	0	0
T142	0	40	0	0
T156	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	32	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T142	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5183055	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5185305	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	34	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T142	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	32	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T142	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	32	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T142	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	32	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T81	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T142	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	17887	0	0
T8	580	41	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T15	0	83	0	0
T24	0	41	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	376	0	0
T56	0	57	0	0
T81	0	54	0	0
T90	0	225	0	0
T142	0	38	0	0
T156	0	36	0	0
T193	0	15679	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	6415	0	0
T1	17765	11	0	0
T2	0	26	0	0
T4	5919	24	0	0
T5	460	0	0	0
T6	1976	4	0	0
T25	24867	13	0	0
T26	0	4	0	0
T39	524	6	0	0
T40	2405	5	0	0
T41	503	7	0	0
T42	11915	28	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	11	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T24	0	1	0	0
T49	494	0	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T89	0	2	0	0
T130	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T12,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T12,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T15
0	1	Covered	T88
1	0	Covered	T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T15
0	1	Covered	T10,T12,T15
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T15
1	-	Covered	T10,T12,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T15
DetectSt	168	Covered	T10,T12,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T15
DebounceSt->IdleSt	163	Covered	T10,T85,T147
DetectSt->IdleSt	186	Covered	T88,T84
DetectSt->StableSt	191	Covered	T10,T12,T15
IdleSt->DebounceSt	148	Covered	T10,T12,T15
StableSt->IdleSt	206	Covered	T10,T12,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T15
0	1	Covered	T10,T12,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T147,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T15
DetectSt	-	-	-	-	1	-	-	Covered	T88,T84
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T15
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	104	0	0
CntIncr_A	5957637	38069	0	0
CntNoWrap_A	5957637	5338895	0	0
DetectStDropOut_A	5957637	1	0	0
DetectedOut_A	5957637	67060	0	0
DetectedPulseOut_A	5957637	48	0	0
DisabledIdleSt_A	5957637	5223515	0	0
DisabledNoDetection_A	5957637	5225771	0	0
EnterDebounceSt_A	5957637	54	0	0
EnterDetectSt_A	5957637	50	0	0
EnterStableSt_A	5957637	48	0	0
PulseIsPulse_A	5957637	48	0	0
StayInStableSt	5957637	66987	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	104	0	0
T10	638	3	0	0
T11	46616	0	0	0
T12	650	4	0	0
T13	23539	0	0	0
T15	0	4	0	0
T17	0	2	0	0
T20	0	2	0	0
T22	0	4	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T56	0	4	0	0
T57	0	4	0	0
T75	6216	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	38069	0	0
T10	638	38	0	0
T11	46616	0	0	0
T12	650	76	0	0
T13	23539	0	0	0
T15	0	5479	0	0
T17	0	86	0	0
T20	0	67	0	0
T22	0	1552	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	75	0	0
T54	0	47	0	0
T56	0	132	0	0
T57	0	120	0	0
T75	6216	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338895	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1	0	0
T80	1168	0	0	0
T88	54735	1	0	0
T95	13861	0	0	0
T115	2875	0	0	0
T196	502	0	0	0
T197	798	0	0	0
T198	7877	0	0	0
T199	540	0	0	0
T200	500	0	0	0
T201	12218	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	67060	0	0
T10	638	73	0	0
T11	46616	0	0	0
T12	650	85	0	0
T13	23539	0	0	0
T15	0	387	0	0
T17	0	42	0	0
T20	0	49	0	0
T22	0	840	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	377	0	0
T54	0	111	0	0
T56	0	136	0	0
T57	0	139	0	0
T75	6216	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	48	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	2	0	0
T13	23539	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T75	6216	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5223515	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5225771	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	54	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	650	2	0	0
T13	23539	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T75	6216	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	50	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	2	0	0
T13	23539	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T75	6216	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	48	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	2	0	0
T13	23539	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T75	6216	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	48	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	2	0	0
T13	23539	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T75	6216	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	66987	0	0
T10	638	72	0	0
T11	46616	0	0	0
T12	650	82	0	0
T13	23539	0	0	0
T15	0	384	0	0
T17	0	40	0	0
T20	0	48	0	0
T22	0	838	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	375	0	0
T54	0	109	0	0
T56	0	133	0	0
T57	0	136	0	0
T75	6216	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	23	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T20	0	1	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T75	6216	0	0	0
T127	0	1	0	0
T151	0	1	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T15,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T15,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T15,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T22
0	1	Covered	T81,T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T22
0	1	Covered	T22,T56,T88
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T20,T22
1	-	Covered	T22,T56,T88

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T20,T22
DetectSt	168	Covered	T15,T20,T22
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T20,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T20,T22
DebounceSt->IdleSt	163	Covered	T22,T84,T85
DetectSt->IdleSt	186	Covered	T81,T161
DetectSt->StableSt	191	Covered	T15,T20,T22
IdleSt->DebounceSt	148	Covered	T15,T20,T22
StableSt->IdleSt	206	Covered	T15,T20,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T20,T22
0	1	Covered	T15,T20,T22
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T20,T22
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T146,T140,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T20,T22
DetectSt	-	-	-	-	1	-	-	Covered	T81,T161
DetectSt	-	-	-	-	0	1	-	Covered	T15,T20,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T56,T88
StableSt	-	-	-	-	-	-	0	Covered	T15,T20,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	71	0	0
CntIncr_A	5957637	17434	0	0
CntNoWrap_A	5957637	5338928	0	0
DetectStDropOut_A	5957637	2	0	0
DetectedOut_A	5957637	2467	0	0
DetectedPulseOut_A	5957637	31	0	0
DisabledIdleSt_A	5957637	5225124	0	0
DisabledNoDetection_A	5957637	5227369	0	0
EnterDebounceSt_A	5957637	39	0	0
EnterDetectSt_A	5957637	33	0	0
EnterStableSt_A	5957637	31	0	0
PulseIsPulse_A	5957637	31	0	0
StayInStableSt	5957637	2420	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	5998	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	71	0	0
T15	14678	2	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	2	0	0
T22	0	2	0	0
T49	494	0	0	0
T56	0	2	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	4	0	0
T84	0	1	0	0
T88	0	4	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	17434	0	0
T15	14678	24	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	67	0	0
T22	0	1287	0	0
T49	494	0	0	0
T56	0	66	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	123	0	0
T84	0	41	0	0
T88	0	46	0	0
T151	0	25	0	0
T152	0	91	0	0
T153	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338928	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2	0	0
T81	86963	1	0	0
T161	0	1	0	0
T202	489	0	0	0
T203	483	0	0	0
T204	494	0	0	0
T205	424	0	0	0
T206	691	0	0	0
T207	21076	0	0	0
T208	5927	0	0	0
T209	529	0	0	0
T210	10790	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2467	0	0
T15	14678	82	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	216	0	0
T22	0	42	0	0
T49	494	0	0	0
T56	0	40	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	216	0	0
T88	0	85	0	0
T127	0	43	0	0
T151	0	46	0	0
T152	0	266	0	0
T153	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T49	494	0	0	0
T56	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	1	0	0
T88	0	2	0	0
T127	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5225124	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5227369	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	39	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T49	494	0	0	0
T56	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T84	0	1	0	0
T88	0	2	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T49	494	0	0	0
T56	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T88	0	2	0	0
T127	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T49	494	0	0	0
T56	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	1	0	0
T88	0	2	0	0
T127	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T49	494	0	0	0
T56	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	1	0	0
T88	0	2	0	0
T127	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2420	0	0
T15	14678	80	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T20	0	214	0	0
T22	0	41	0	0
T49	494	0	0	0
T56	0	39	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	214	0	0
T88	0	82	0	0
T127	0	41	0	0
T151	0	44	0	0
T152	0	264	0	0
T153	0	46	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5998	0	0
T1	17765	10	0	0
T4	5919	29	0	0
T5	460	1	0	0
T6	1976	6	0	0
T25	24867	10	0	0
T26	0	6	0	0
T39	524	4	0	0
T40	2405	5	0	0
T41	503	6	0	0
T42	11915	34	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	15	0	0
T22	8908	1	0	0
T36	632	0	0	0
T56	0	1	0	0
T65	1389	0	0	0
T88	0	1	0	0
T89	0	1	0	0
T137	0	1	0	0
T147	0	1	0	0
T153	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T211	0	1	0	0
T212	429	0	0	0
T213	8434	0	0	0
T214	14211	0	0	0
T215	502	0	0	0
T216	423	0	0	0
T217	11073	0	0	0
T218	7611	0	0	0