Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T15
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T15
0	1	Covered	T10,T12,T15
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T15
1	-	Covered	T10,T12,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T12
DetectSt	168	Covered	T10,T12,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T15
DebounceSt->IdleSt	163	Covered	T8,T156,T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T12,T15
IdleSt->DebounceSt	148	Covered	T8,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T140,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T15
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	130	0	0
CntIncr_A	5957637	35031	0	0
CntNoWrap_A	5957637	5338869	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	30308	0	0
DetectedPulseOut_A	5957637	62	0	0
DisabledIdleSt_A	5957637	5229315	0	0
DisabledNoDetection_A	5957637	5231561	0	0
EnterDebounceSt_A	5957637	69	0	0
EnterDetectSt_A	5957637	62	0	0
EnterStableSt_A	5957637	62	0	0
PulseIsPulse_A	5957637	62	0	0
StayInStableSt	5957637	30217	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	130	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	0	2	0	0
T15	0	8	0	0
T17	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	4	0	0
T56	0	8	0	0
T80	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	35031	0	0
T8	580	66	0	0
T9	685	0	0	0
T10	638	19	0	0
T11	46616	0	0	0
T12	0	38	0	0
T15	0	5566	0	0
T17	0	86	0	0
T22	0	776	0	0
T23	0	65	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	52	0	0
T56	0	246	0	0
T80	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338869	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	30308	0	0
T10	638	137	0	0
T11	46616	0	0	0
T12	650	84	0	0
T13	23539	0	0	0
T15	0	415	0	0
T17	0	127	0	0
T22	0	1196	0	0
T23	0	247	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	91	0	0
T56	0	243	0	0
T75	6216	0	0	0
T80	0	273	0	0
T81	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	62	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	4	0	0
T17	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5229315	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5231561	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	69	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	0	1	0	0
T15	0	4	0	0
T17	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T80	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	62	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	4	0	0
T17	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	62	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	4	0	0
T17	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	62	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	4	0	0
T17	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	30217	0	0
T10	638	136	0	0
T11	46616	0	0	0
T12	650	83	0	0
T13	23539	0	0	0
T15	0	408	0	0
T17	0	125	0	0
T22	0	1194	0	0
T23	0	245	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	89	0	0
T56	0	237	0	0
T75	6216	0	0	0
T80	0	272	0	0
T81	0	96	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T127	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T54,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T15,T54,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T15,T54,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T15,T54,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T54,T55
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T54,T55
0	1	Covered	T15,T55,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T54,T55
1	-	Covered	T15,T55,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T54,T55
DetectSt	168	Covered	T15,T54,T55
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T15,T54,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T54,T55
DebounceSt->IdleSt	163	Covered	T152,T84,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T15,T54,T55
IdleSt->DebounceSt	148	Covered	T15,T54,T55
StableSt->IdleSt	206	Covered	T15,T55,T151

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T54,T55
0	1	Covered	T15,T54,T55
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T54,T55
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T54,T55
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T54,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T54,T55
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T54,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T55,T151
StableSt	-	-	-	-	-	-	0	Covered	T15,T54,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	54	0	0
CntIncr_A	5957637	1342	0	0
CntNoWrap_A	5957637	5338945	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	1777	0	0
DetectedPulseOut_A	5957637	25	0	0
DisabledIdleSt_A	5957637	5277977	0	0
DisabledNoDetection_A	5957637	5280231	0	0
EnterDebounceSt_A	5957637	29	0	0
EnterDetectSt_A	5957637	25	0	0
EnterStableSt_A	5957637	25	0	0
PulseIsPulse_A	5957637	25	0	0
StayInStableSt	5957637	1738	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	6048	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	54	0	0
T15	14678	2	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	2	0	0
T55	0	4	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	4	0	0
T84	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0
T219	0	2	0	0
T220	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1342	0	0
T15	14678	24	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	47	0	0
T55	0	52	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	101	0	0
T84	0	41	0	0
T151	0	25	0	0
T152	0	91	0	0
T153	0	41	0	0
T219	0	86	0	0
T220	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338945	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1777	0	0
T15	14678	82	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	39	0	0
T55	0	98	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	65	0	0
T151	0	43	0	0
T153	0	93	0	0
T154	0	86	0	0
T157	0	193	0	0
T219	0	42	0	0
T220	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	25	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5277977	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5280231	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	29	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T84	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	25	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	25	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	25	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	1	0	0
T55	0	2	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1738	0	0
T15	14678	81	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T54	0	37	0	0
T55	0	95	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	62	0	0
T151	0	42	0	0
T153	0	92	0	0
T154	0	84	0	0
T157	0	192	0	0
T219	0	40	0	0
T220	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	6048	0	0
T1	17765	11	0	0
T4	5919	29	0	0
T5	460	1	0	0
T6	1976	4	0	0
T25	24867	12	0	0
T26	0	5	0	0
T39	524	6	0	0
T40	2405	4	0	0
T41	503	5	0	0
T42	11915	29	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	11	0	0
T15	14678	1	0	0
T16	67283	0	0	0
T17	840	0	0	0
T18	11295	0	0	0
T49	494	0	0	0
T55	0	1	0	0
T62	402	0	0	0
T63	408	0	0	0
T64	503	0	0	0
T73	425	0	0	0
T74	523	0	0	0
T81	0	1	0	0
T148	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T195	0	2	0	0
T220	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T15
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T15,T17
0	1	Covered	T10,T17,T22
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T15,T17
1	-	Covered	T10,T17,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T15,T17
DetectSt	168	Covered	T10,T15,T17
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T15,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T15,T17
DebounceSt->IdleSt	163	Covered	T23,T81,T142
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T10,T15,T17
IdleSt->DebounceSt	148	Covered	T10,T15,T17
StableSt->IdleSt	206	Covered	T10,T15,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T15,T17
0	1	Covered	T10,T15,T17
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T17
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T81,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T10,T15,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T17,T22
StableSt	-	-	-	-	-	-	0	Covered	T10,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	130	0	0
CntIncr_A	5957637	63661	0	0
CntNoWrap_A	5957637	5338869	0	0
DetectStDropOut_A	5957637	1	0	0
DetectedOut_A	5957637	65403	0	0
DetectedPulseOut_A	5957637	59	0	0
DisabledIdleSt_A	5957637	5133416	0	0
DisabledNoDetection_A	5957637	5135653	0	0
EnterDebounceSt_A	5957637	71	0	0
EnterDetectSt_A	5957637	60	0	0
EnterStableSt_A	5957637	59	0	0
PulseIsPulse_A	5957637	59	0	0
StayInStableSt	5957637	65310	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	130	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	2	0	0
T17	0	4	0	0
T20	0	2	0	0
T22	0	2	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	8	0	0
T75	6216	0	0	0
T80	0	2	0	0
T88	0	2	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	63661	0	0
T10	638	19	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	5455	0	0
T17	0	172	0	0
T20	0	67	0	0
T22	0	776	0	0
T23	0	65	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	246	0	0
T75	6216	0	0	0
T80	0	97	0	0
T88	0	41	0	0
T151	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338869	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1	0	0
T81	86963	1	0	0
T202	489	0	0	0
T203	483	0	0	0
T204	494	0	0	0
T205	424	0	0	0
T206	691	0	0	0
T207	21076	0	0	0
T208	5927	0	0	0
T209	529	0	0	0
T210	10790	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	65403	0	0
T10	638	68	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	303	0	0
T17	0	172	0	0
T20	0	43	0	0
T22	0	154	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	212	0	0
T75	6216	0	0	0
T80	0	447	0	0
T88	0	1	0	0
T151	0	90	0	0
T152	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	59	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T20	0	1	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5133416	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5135653	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	71	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T20	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T20	0	1	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	59	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T20	0	1	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	59	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	1	0	0
T17	0	2	0	0
T20	0	1	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	4	0	0
T75	6216	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	65310	0	0
T10	638	67	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T15	0	301	0	0
T17	0	169	0	0
T20	0	41	0	0
T22	0	153	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	206	0	0
T75	6216	0	0	0
T80	0	446	0	0
T81	0	358	0	0
T151	0	87	0	0
T152	0	130	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	24	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T17	0	1	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0
T75	6216	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T22,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T22,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T22,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T22
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T22,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T22,T53
0	1	Not Covered
1	0	Covered	T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T22,T53
0	1	Covered	T53,T151,T81
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T22,T53
1	-	Covered	T53,T151,T81

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T22,T53
DetectSt	168	Covered	T10,T22,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T22,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T22,T53
DebounceSt->IdleSt	163	Covered	T85,T147
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T10,T22,T53
IdleSt->DebounceSt	148	Covered	T10,T22,T53
StableSt->IdleSt	206	Covered	T22,T53,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T22,T53
0	1	Covered	T10,T22,T53
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T22,T53
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T22,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T22,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T147
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T22,T53
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T10,T22,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T53,T151,T81
StableSt	-	-	-	-	-	-	0	Covered	T10,T22,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	60	0	0
CntIncr_A	5957637	16406	0	0
CntNoWrap_A	5957637	5338939	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	4267	0	0
DetectedPulseOut_A	5957637	28	0	0
DisabledIdleSt_A	5957637	5186263	0	0
DisabledNoDetection_A	5957637	5188511	0	0
EnterDebounceSt_A	5957637	31	0	0
EnterDetectSt_A	5957637	29	0	0
EnterStableSt_A	5957637	28	0	0
PulseIsPulse_A	5957637	28	0	0
StayInStableSt	5957637	4222	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	5984	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	2	0	0
T56	0	2	0	0
T75	6216	0	0	0
T81	0	6	0	0
T84	0	2	0	0
T88	0	4	0	0
T151	0	2	0	0
T153	0	2	0	0
T220	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	16406	0	0
T10	638	19	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	776	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	75	0	0
T56	0	38	0	0
T75	6216	0	0	0
T81	0	207	0	0
T84	0	41	0	0
T88	0	64	0	0
T151	0	25	0	0
T153	0	41	0	0
T220	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338939	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4267	0	0
T10	638	117	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	2016	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	254	0	0
T56	0	47	0	0
T75	6216	0	0	0
T81	0	164	0	0
T88	0	83	0	0
T151	0	5	0	0
T153	0	41	0	0
T157	0	40	0	0
T220	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	28	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T75	6216	0	0	0
T81	0	3	0	0
T88	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T220	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5186263	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5188511	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	31	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T75	6216	0	0	0
T81	0	3	0	0
T84	0	1	0	0
T88	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T220	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	29	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T75	6216	0	0	0
T81	0	3	0	0
T84	0	1	0	0
T88	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T220	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	28	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T75	6216	0	0	0
T81	0	3	0	0
T88	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T220	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	28	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T75	6216	0	0	0
T81	0	3	0	0
T88	0	2	0	0
T151	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T220	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4222	0	0
T10	638	115	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	2014	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T53	0	253	0	0
T56	0	45	0	0
T75	6216	0	0	0
T81	0	160	0	0
T88	0	79	0	0
T151	0	4	0	0
T153	0	40	0	0
T157	0	39	0	0
T220	0	129	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5984	0	0
T1	17765	16	0	0
T4	5919	28	0	0
T5	460	1	0	0
T6	1976	5	0	0
T25	24867	12	0	0
T26	0	4	0	0
T39	524	5	0	0
T40	2405	5	0	0
T41	503	3	0	0
T42	11915	16	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	11	0	0
T53	1130	1	0	0
T78	19926	0	0	0
T81	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T157	0	1	0	0
T194	0	1	0	0
T220	0	1	0	0
T223	0	1	0	0
T224	404	0	0	0
T225	9192	0	0	0
T226	403	0	0	0
T227	504	0	0	0
T228	15406	0	0	0
T229	32159	0	0	0
T230	525	0	0	0
T231	895	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T39

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T39
1	1	Covered	T4,T6,T39

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T12
1	0	Covered	T4,T6,T39
1	1	Covered	T8,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Not Covered
1	0	Covered	T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T12
0	1	Covered	T10,T12,T21
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T12
1	-	Covered	T10,T12,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T12
DetectSt	168	Covered	T8,T10,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T12
DebounceSt->IdleSt	163	Covered	T22,T81,T85
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T8,T10,T12
IdleSt->DebounceSt	148	Covered	T8,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T12
0	1	Covered	T8,T10,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T39
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T146,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T21
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	131	0	0
CntIncr_A	5957637	33340	0	0
CntNoWrap_A	5957637	5338868	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	13933	0	0
DetectedPulseOut_A	5957637	61	0	0
DisabledIdleSt_A	5957637	5217843	0	0
DisabledNoDetection_A	5957637	5220079	0	0
EnterDebounceSt_A	5957637	70	0	0
EnterDetectSt_A	5957637	62	0	0
EnterStableSt_A	5957637	61	0	0
PulseIsPulse_A	5957637	61	0	0
StayInStableSt	5957637	13845	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	131	0	0
T8	580	2	0	0
T9	685	0	0	0
T10	638	4	0	0
T11	46616	0	0	0
T12	0	2	0	0
T15	0	2	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	0	2	0	0
T23	0	4	0	0
T24	0	2	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33340	0	0
T8	580	66	0	0
T9	685	0	0	0
T10	638	38	0	0
T11	46616	0	0	0
T12	0	38	0	0
T15	0	63	0	0
T20	0	67	0	0
T21	0	68	0	0
T22	0	1286	0	0
T23	0	130	0	0
T24	0	11	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338868	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	13933	0	0
T8	580	44	0	0
T9	685	0	0	0
T10	638	51	0	0
T11	46616	0	0	0
T12	0	74	0	0
T15	0	41	0	0
T20	0	104	0	0
T21	0	64	0	0
T22	0	43	0	0
T23	0	84	0	0
T24	0	76	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	61	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	0	1	0	0
T15	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5217843	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5220079	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	70	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	0	1	0	0
T15	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	62	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	0	1	0	0
T15	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	61	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	0	1	0	0
T15	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	61	0	0
T8	580	1	0	0
T9	685	0	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	0	1	0	0
T15	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	13845	0	0
T8	580	42	0	0
T9	685	0	0	0
T10	638	48	0	0
T11	46616	0	0	0
T12	0	73	0	0
T15	0	39	0	0
T20	0	102	0	0
T21	0	63	0	0
T22	0	42	0	0
T23	0	81	0	0
T24	0	75	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	34	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T90	0	2	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T39
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T12,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T15
1	0	Covered	T4,T6,T39
1	1	Covered	T10,T12,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T15
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T15
0	1	Covered	T10,T22,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T15
1	-	Covered	T10,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T15
DetectSt	168	Covered	T10,T12,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T15
DebounceSt->IdleSt	163	Covered	T84,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T12,T15
IdleSt->DebounceSt	148	Covered	T10,T12,T15
StableSt->IdleSt	206	Covered	T10,T15,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T15
0	1	Covered	T10,T12,T15
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T15
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T15
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	68	0	0
CntIncr_A	5957637	2665	0	0
CntNoWrap_A	5957637	5338931	0	0
DetectStDropOut_A	5957637	0	0	0
DetectedOut_A	5957637	2811	0	0
DetectedPulseOut_A	5957637	33	0	0
DisabledIdleSt_A	5957637	5321894	0	0
DisabledNoDetection_A	5957637	5324148	0	0
EnterDebounceSt_A	5957637	35	0	0
EnterDetectSt_A	5957637	33	0	0
EnterStableSt_A	5957637	33	0	0
PulseIsPulse_A	5957637	33	0	0
StayInStableSt	5957637	2759	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5957637	6634	0	0
gen_low_level_sva.LowLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	68	0	0
T10	638	2	0	0
T11	46616	0	0	0
T12	650	2	0	0
T13	23539	0	0	0
T15	0	2	0	0
T21	0	2	0	0
T22	0	2	0	0
T23	0	2	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	4	0	0
T57	0	2	0	0
T75	6216	0	0	0
T80	0	2	0	0
T81	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2665	0	0
T10	638	19	0	0
T11	46616	0	0	0
T12	650	38	0	0
T13	23539	0	0	0
T15	0	24	0	0
T21	0	68	0	0
T22	0	776	0	0
T23	0	65	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	132	0	0
T57	0	60	0	0
T75	6216	0	0	0
T80	0	97	0	0
T81	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338931	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2811	0	0
T10	638	52	0	0
T11	46616	0	0	0
T12	650	45	0	0
T13	23539	0	0	0
T15	0	150	0	0
T21	0	41	0	0
T22	0	684	0	0
T23	0	30	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	292	0	0
T57	0	38	0	0
T75	6216	0	0	0
T80	0	257	0	0
T81	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5321894	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5324148	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	35	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	1	0	0
T13	23539	0	0	0
T15	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T75	6216	0	0	0
T80	0	1	0	0
T81	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2759	0	0
T10	638	51	0	0
T11	46616	0	0	0
T12	650	43	0	0
T13	23539	0	0	0
T15	0	148	0	0
T21	0	39	0	0
T22	0	683	0	0
T23	0	29	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	289	0	0
T57	0	36	0	0
T75	6216	0	0	0
T80	0	255	0	0
T81	0	58	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	6634	0	0
T1	17765	11	0	0
T2	0	32	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	4	0	0
T25	24867	16	0	0
T26	0	3	0	0
T39	524	5	0	0
T40	2405	6	0	0
T41	503	5	0	0
T42	11915	27	0	0
T43	402	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	14	0	0
T10	638	1	0	0
T11	46616	0	0	0
T12	650	0	0	0
T13	23539	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	0	0	0
T33	877	0	0	0
T56	0	1	0	0
T75	6216	0	0	0
T89	0	1	0	0
T90	0	1	0	0
T147	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T233	0	1	0	0