Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1144277122	10274	0	0
auto_block_debounce_ctl_rd_A	1144277122	1178	0	0
auto_block_out_ctl_rd_A	1144277122	1525	0	0
com_det_ctl_0_rd_A	1144277122	2592	0	0
com_det_ctl_1_rd_A	1144277122	2659	0	0
com_det_ctl_2_rd_A	1144277122	2508	0	0
com_det_ctl_3_rd_A	1144277122	2514	0	0
com_out_ctl_0_rd_A	1144277122	2805	0	0
com_out_ctl_1_rd_A	1144277122	2835	0	0
com_out_ctl_2_rd_A	1144277122	2659	0	0
com_out_ctl_3_rd_A	1144277122	2866	0	0
com_pre_det_ctl_0_rd_A	1144277122	918	0	0
com_pre_det_ctl_1_rd_A	1144277122	905	0	0
com_pre_det_ctl_2_rd_A	1144277122	801	0	0
com_pre_det_ctl_3_rd_A	1144277122	982	0	0
com_pre_sel_ctl_0_rd_A	1144277122	2840	0	0
com_pre_sel_ctl_1_rd_A	1144277122	2934	0	0
com_pre_sel_ctl_2_rd_A	1144277122	2923	0	0
com_pre_sel_ctl_3_rd_A	1144277122	2928	0	0
com_sel_ctl_0_rd_A	1144277122	2900	0	0
com_sel_ctl_1_rd_A	1144277122	2901	0	0
com_sel_ctl_2_rd_A	1144277122	2925	0	0
com_sel_ctl_3_rd_A	1144277122	2949	0	0
ec_rst_ctl_rd_A	1144277122	1490	0	0
intr_enable_rd_A	1144277122	1313	0	0
key_intr_ctl_rd_A	1144277122	2202	0	0
key_intr_debounce_ctl_rd_A	1144277122	881	0	0
key_invert_ctl_rd_A	1144277122	3859	0	0
pin_allowed_ctl_rd_A	1144277122	4439	0	0
pin_out_ctl_rd_A	1144277122	3405	0	0
pin_out_value_rd_A	1144277122	3606	0	0
regwen_rd_A	1144277122	1008	0	0
ulp_ac_debounce_ctl_rd_A	1144277122	1036	0	0
ulp_ctl_rd_A	1144277122	1109	0	0
ulp_lid_debounce_ctl_rd_A	1144277122	1026	0	0
ulp_pwrb_debounce_ctl_rd_A	1144277122	1067	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	10274	0	0
T14	175516	10	0	0
T15	174347	6	0	0
T16	56792	0	0	0
T17	201506	0	0	0
T18	101658	0	0	0
T20	0	4	0	0
T22	0	12	0	0
T34	0	11	0	0
T38	0	18	0	0
T48	235008	0	0	0
T51	547096	0	0	0
T56	0	6	0	0
T62	193011	0	0	0
T63	48982	0	0	0
T64	110655	0	0	0
T69	0	14	0	0
T112	0	26	0	0
T277	0	15	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1178	0	0
T22	345097	0	0	0
T58	657331	14	0	0
T59	0	11	0	0
T60	0	3	0	0
T65	39085	0	0	0
T81	0	67	0	0
T90	0	25	0	0
T153	0	6	0	0
T212	19319	0	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T215	128181	0	0	0
T256	137814	0	0	0
T278	0	15	0	0
T279	0	9	0	0
T280	0	2	0	0
T281	0	15	0	0
T282	253363	0	0	0
T283	676789	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1525	0	0
T22	345097	0	0	0
T58	657331	9	0	0
T59	0	17	0	0
T65	39085	0	0	0
T81	0	77	0	0
T90	0	8	0	0
T127	0	51	0	0
T153	0	7	0	0
T212	19319	0	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T215	128181	0	0	0
T256	137814	0	0	0
T278	0	3	0	0
T279	0	8	0	0
T280	0	7	0	0
T281	0	15	0	0
T282	253363	0	0	0
T283	676789	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2592	0	0
T11	279704	43	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	71	0	0
T81	0	197	0	0
T198	0	46	0	0
T214	0	17	0	0
T239	0	69	0	0
T250	0	58	0	0
T284	0	57	0	0
T285	0	50	0	0
T286	0	60	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2659	0	0
T11	279704	58	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	91	0	0
T81	0	231	0	0
T198	0	27	0	0
T214	0	24	0	0
T239	0	35	0	0
T250	0	54	0	0
T284	0	69	0	0
T285	0	49	0	0
T286	0	58	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2508	0	0
T11	279704	61	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	67	0	0
T81	0	228	0	0
T198	0	36	0	0
T214	0	28	0	0
T239	0	53	0	0
T250	0	75	0	0
T284	0	66	0	0
T285	0	37	0	0
T286	0	38	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2514	0	0
T11	279704	75	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	68	0	0
T81	0	219	0	0
T198	0	38	0	0
T214	0	17	0	0
T239	0	40	0	0
T250	0	91	0	0
T284	0	67	0	0
T285	0	28	0	0
T286	0	29	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2805	0	0
T11	279704	70	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	56	0	0
T81	0	222	0	0
T198	0	51	0	0
T214	0	22	0	0
T239	0	29	0	0
T250	0	68	0	0
T284	0	66	0	0
T285	0	49	0	0
T286	0	44	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2835	0	0
T11	279704	49	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	70	0	0
T81	0	182	0	0
T198	0	37	0	0
T214	0	34	0	0
T239	0	34	0	0
T250	0	66	0	0
T284	0	47	0	0
T285	0	19	0	0
T286	0	49	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2659	0	0
T11	279704	44	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	80	0	0
T81	0	211	0	0
T198	0	32	0	0
T214	0	21	0	0
T239	0	36	0	0
T250	0	66	0	0
T284	0	52	0	0
T285	0	32	0	0
T286	0	41	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2866	0	0
T11	279704	43	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	75	0	0
T81	0	207	0	0
T198	0	38	0	0
T214	0	32	0	0
T239	0	42	0	0
T250	0	70	0	0
T284	0	66	0	0
T285	0	40	0	0
T286	0	36	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	918	0	0
T44	0	19	0	0
T81	295197	13	0	0
T90	0	10	0	0
T127	0	18	0	0
T137	0	39	0	0
T141	0	20	0	0
T202	56186	0	0	0
T203	241912	0	0	0
T204	59342	0	0	0
T205	48828	0	0	0
T206	96894	0	0	0
T207	179150	0	0	0
T208	290438	0	0	0
T209	37020	0	0	0
T210	147708	0	0	0
T261	0	27	0	0
T287	0	12	0	0
T288	0	16	0	0
T289	0	25	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	905	0	0
T44	0	10	0	0
T81	295197	15	0	0
T90	0	25	0	0
T127	0	21	0	0
T137	0	61	0	0
T141	0	10	0	0
T202	56186	0	0	0
T203	241912	0	0	0
T204	59342	0	0	0
T205	48828	0	0	0
T206	96894	0	0	0
T207	179150	0	0	0
T208	290438	0	0	0
T209	37020	0	0	0
T210	147708	0	0	0
T261	0	17	0	0
T287	0	14	0	0
T288	0	22	0	0
T289	0	2	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	801	0	0
T44	0	16	0	0
T81	295197	15	0	0
T90	0	13	0	0
T127	0	4	0	0
T137	0	28	0	0
T141	0	5	0	0
T202	56186	0	0	0
T203	241912	0	0	0
T204	59342	0	0	0
T205	48828	0	0	0
T206	96894	0	0	0
T207	179150	0	0	0
T208	290438	0	0	0
T209	37020	0	0	0
T210	147708	0	0	0
T261	0	26	0	0
T287	0	16	0	0
T288	0	12	0	0
T289	0	2	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	982	0	0
T44	0	8	0	0
T81	295197	17	0	0
T90	0	24	0	0
T127	0	9	0	0
T137	0	39	0	0
T141	0	16	0	0
T202	56186	0	0	0
T203	241912	0	0	0
T204	59342	0	0	0
T205	48828	0	0	0
T206	96894	0	0	0
T207	179150	0	0	0
T208	290438	0	0	0
T209	37020	0	0	0
T210	147708	0	0	0
T261	0	32	0	0
T287	0	14	0	0
T288	0	23	0	0
T289	0	20	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2840	0	0
T11	279704	49	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	61	0	0
T81	0	187	0	0
T198	0	54	0	0
T214	0	24	0	0
T239	0	27	0	0
T250	0	57	0	0
T284	0	68	0	0
T285	0	31	0	0
T286	0	43	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2934	0	0
T11	279704	27	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	81	0	0
T81	0	213	0	0
T198	0	40	0	0
T214	0	25	0	0
T239	0	43	0	0
T250	0	81	0	0
T284	0	46	0	0
T285	0	46	0	0
T286	0	49	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2923	0	0
T11	279704	81	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	81	0	0
T81	0	204	0	0
T198	0	42	0	0
T214	0	37	0	0
T239	0	23	0	0
T250	0	76	0	0
T284	0	52	0	0
T285	0	32	0	0
T286	0	41	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2928	0	0
T11	279704	33	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	63	0	0
T81	0	216	0	0
T198	0	42	0	0
T214	0	27	0	0
T239	0	67	0	0
T250	0	57	0	0
T284	0	45	0	0
T285	0	37	0	0
T286	0	53	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2900	0	0
T11	279704	47	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	70	0	0
T81	0	230	0	0
T198	0	43	0	0
T214	0	44	0	0
T239	0	58	0	0
T250	0	79	0	0
T284	0	57	0	0
T285	0	25	0	0
T286	0	70	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2901	0	0
T11	279704	57	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	45	0	0
T81	0	226	0	0
T198	0	29	0	0
T214	0	24	0	0
T239	0	58	0	0
T250	0	87	0	0
T284	0	45	0	0
T285	0	59	0	0
T286	0	39	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2925	0	0
T11	279704	45	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	80	0	0
T81	0	220	0	0
T198	0	28	0	0
T214	0	11	0	0
T239	0	24	0	0
T250	0	77	0	0
T284	0	63	0	0
T285	0	31	0	0
T286	0	29	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2949	0	0
T11	279704	71	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	0	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	65	0	0
T81	0	230	0	0
T198	0	39	0	0
T214	0	33	0	0
T239	0	22	0	0
T250	0	81	0	0
T284	0	65	0	0
T285	0	36	0	0
T286	0	33	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1490	0	0
T11	279704	11	0	0
T12	76682	0	0	0
T13	576717	0	0	0
T14	175516	0	0	0
T30	68417	0	0	0
T31	54990	0	0	0
T32	614727	1	0	0
T33	57054	0	0	0
T50	710342	0	0	0
T75	307729	0	0	0
T78	0	16	0	0
T214	0	18	0	0
T231	0	5	0	0
T237	0	2	0	0
T239	0	10	0	0
T250	0	12	0	0
T284	0	31	0	0
T290	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1313	0	0
T22	345097	0	0	0
T44	0	11	0	0
T58	657331	0	0	0
T65	39085	0	0	0
T72	191081	21	0	0
T81	0	62	0	0
T90	0	46	0	0
T127	0	32	0	0
T137	0	41	0	0
T141	0	38	0	0
T212	19319	0	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T256	137814	0	0	0
T282	253363	0	0	0
T283	676789	0	0	0
T287	0	11	0	0
T288	0	24	0	0
T291	0	9	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	2202	0	0
T21	211551	8	0	0
T24	0	3	0	0
T34	448835	0	0	0
T35	58860	0	0	0
T54	0	9	0	0
T70	51703	0	0	0
T81	0	46	0	0
T83	256869	0	0	0
T84	0	115	0	0
T90	0	20	0	0
T120	48781	0	0	0
T121	73151	0	0	0
T122	202417	0	0	0
T123	55152	0	0	0
T124	11599	0	0	0
T127	0	28	0	0
T154	0	1	0	0
T193	0	3	0	0
T292	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	881	0	0
T44	0	31	0	0
T81	295197	10	0	0
T90	0	17	0	0
T137	0	36	0	0
T141	0	3	0	0
T202	56186	0	0	0
T203	241912	0	0	0
T204	59342	0	0	0
T205	48828	0	0	0
T206	96894	0	0	0
T207	179150	0	0	0
T208	290438	0	0	0
T209	37020	0	0	0
T210	147708	0	0	0
T261	0	14	0	0
T287	0	7	0	0
T288	0	21	0	0
T289	0	5	0	0
T293	0	6	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	3859	0	0
T19	195598	0	0	0
T66	118795	71	0	0
T67	59568	0	0	0
T68	62376	63	0	0
T69	115960	0	0	0
T72	0	66	0	0
T81	0	20	0	0
T107	173581	0	0	0
T108	80660	0	0	0
T109	101575	0	0	0
T110	434076	0	0	0
T131	97045	0	0	0
T294	0	82	0	0
T295	0	35	0	0
T296	0	48	0	0
T297	0	44	0	0
T298	0	69	0	0
T299	0	63	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	4439	0	0
T58	657331	0	0	0
T71	242643	0	0	0
T72	191081	0	0	0
T81	0	88	0	0
T121	73151	27	0	0
T122	202417	0	0	0
T123	55152	0	0	0
T124	11599	0	0	0
T125	593475	0	0	0
T126	204960	0	0	0
T199	0	77	0	0
T275	0	22	0	0
T283	0	32	0	0
T300	0	70	0	0
T301	0	67	0	0
T302	0	29	0	0
T303	0	48	0	0
T304	0	65	0	0
T305	113740	0	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	3405	0	0
T58	657331	0	0	0
T71	242643	0	0	0
T72	191081	0	0	0
T81	0	79	0	0
T121	73151	28	0	0
T122	202417	0	0	0
T123	55152	0	0	0
T124	11599	0	0	0
T125	593475	0	0	0
T126	204960	0	0	0
T199	0	75	0	0
T275	0	35	0	0
T283	0	58	0	0
T300	0	60	0	0
T301	0	65	0	0
T302	0	25	0	0
T303	0	53	0	0
T304	0	80	0	0
T305	113740	0	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	3606	0	0
T58	657331	0	0	0
T71	242643	0	0	0
T72	191081	0	0	0
T81	0	92	0	0
T121	73151	39	0	0
T122	202417	0	0	0
T123	55152	0	0	0
T124	11599	0	0	0
T125	593475	0	0	0
T126	204960	0	0	0
T199	0	54	0	0
T275	0	33	0	0
T283	0	64	0	0
T300	0	49	0	0
T301	0	65	0	0
T302	0	31	0	0
T303	0	56	0	0
T304	0	60	0	0
T305	113740	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1008	0	0
T44	0	20	0	0
T81	295197	11	0	0
T90	0	19	0	0
T127	0	13	0	0
T137	0	34	0	0
T141	0	11	0	0
T202	56186	0	0	0
T203	241912	0	0	0
T204	59342	0	0	0
T205	48828	0	0	0
T206	96894	0	0	0
T207	179150	0	0	0
T208	290438	0	0	0
T209	37020	0	0	0
T210	147708	0	0	0
T261	0	21	0	0
T287	0	14	0	0
T288	0	25	0	0
T289	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1036	0	0
T36	112580	9	0	0
T65	39085	6	0	0
T81	0	23	0	0
T90	0	30	0	0
T133	0	3	0	0
T153	0	3	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T215	128181	0	0	0
T216	52997	0	0	0
T217	132884	0	0	0
T218	875300	0	0	0
T238	247735	0	0	0
T275	63410	0	0	0
T304	0	3	0	0
T306	0	4	0	0
T307	0	6	0	0
T308	0	10	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1109	0	0
T36	112580	7	0	0
T65	39085	7	0	0
T81	0	13	0	0
T90	0	43	0	0
T91	0	1	0	0
T133	0	5	0	0
T153	0	2	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T215	128181	0	0	0
T216	52997	0	0	0
T217	132884	0	0	0
T218	875300	0	0	0
T238	247735	0	0	0
T275	63410	0	0	0
T304	0	5	0	0
T307	0	9	0	0
T308	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1026	0	0
T36	112580	0	0	0
T65	39085	2	0	0
T81	0	20	0	0
T90	0	25	0	0
T91	0	9	0	0
T127	0	21	0	0
T153	0	5	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T215	128181	0	0	0
T216	52997	0	0	0
T217	132884	0	0	0
T218	875300	0	0	0
T238	247735	0	0	0
T275	63410	0	0	0
T304	0	1	0	0
T306	0	10	0	0
T307	0	7	0	0
T309	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1144277122	1067	0	0
T36	112580	1	0	0
T65	39085	11	0	0
T81	0	26	0	0
T90	0	11	0	0
T91	0	10	0	0
T133	0	7	0	0
T153	0	4	0	0
T213	674768	0	0	0
T214	255802	0	0	0
T215	128181	0	0	0
T216	52997	0	0	0
T217	132884	0	0	0
T218	875300	0	0	0
T238	247735	0	0	0
T275	63410	0	0	0
T304	0	6	0	0
T306	0	3	0	0
T307	0	3	0	0