Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 72.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

5 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg_(3) 0.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(4) 62.50 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg 100.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(1) 100.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(2) 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(3)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 12 0 0.00
Crosses 12 12 0 0.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 2 0 0.00 100 1 1 2
cp_key0_out_value 2 2 0 0.00 100 1 1 2
cp_key1_out_sel 2 2 0 0.00 100 1 1 2
cp_key1_out_value 2 2 0 0.00 100 1 1 2
cp_key2_out_sel 2 2 0 0.00 100 1 1 2
cp_key2_out_value 2 2 0 0.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 4 0 0.00 100 1 1 0
cross_key1_out_sel_value 4 4 0 0.00 100 1 1 0
cross_key2_out_sel_value 4 4 0 0.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(4)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 2 10 83.33
Crosses 12 7 5 41.67


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 1 1 50.00 100 1 1 2
cp_key2_out_value 2 1 1 50.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(4)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 2 2 50.00 100 1 1 0
cross_key1_out_sel_value 4 2 2 50.00 100 1 1 0
cross_key2_out_sel_value 4 3 1 25.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(2)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key0_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key0_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key1_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key1_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key2_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_key2_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 4 0 0.00 4


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
* * -- -- 4


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T167 1
auto[1] 2 1 T167 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T167 2
auto[1] 1 1 T167 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T167 1
auto[1] 2 1 T167 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T167 2
auto[1] 1 1 T167 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_key2_out_sel

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 3 1 T167 3



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_key2_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[1] 3 1 T167 3



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] 0 1 1
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[1] 2 1 T167 2
auto[1] auto[0] 1 1 T167 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[0]] 0 1 1
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[1] 2 1 T167 2
auto[1] auto[0] 1 1 T167 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 3 1 25.00 3


Automatically Generated Cross Bins for cross_key2_out_sel_value

Element holes
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] * -- -- 2


Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[1] auto[0] 3 1 T167 3


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 122 1 T4 2 T41 2 T46 1
auto[1] 113 1 T4 1 T41 1 T45 3



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 108 1 T4 2 T41 1 T45 3
auto[1] 127 1 T4 1 T41 2 T47 3



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 125 1 T4 2 T41 3 T45 2
auto[1] 110 1 T4 1 T45 1 T46 3



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118 1 T4 1 T41 1 T45 1
auto[1] 117 1 T4 2 T41 2 T45 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 120 1 T4 2 T41 2 T46 2
auto[1] 115 1 T4 1 T41 1 T45 3



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 124 1 T4 3 T41 2 T45 3
auto[1] 111 1 T41 1 T46 2 T47 1



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 54 1 T4 2 T41 1 T46 1
auto[0] auto[1] 54 1 T45 3 T46 2 T49 1
auto[1] auto[0] 68 1 T41 1 T47 2 T48 1
auto[1] auto[1] 59 1 T4 1 T41 1 T47 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 65 1 T4 1 T41 1 T48 3
auto[0] auto[1] 53 1 T45 1 T46 1 T51 1
auto[1] auto[0] 60 1 T4 1 T41 2 T45 2
auto[1] auto[1] 57 1 T4 1 T46 2 T47 2



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 64 1 T4 2 T41 1 T46 1
auto[0] auto[1] 60 1 T4 1 T41 1 T45 3
auto[1] auto[0] 56 1 T41 1 T46 1 T47 1
auto[1] auto[1] 55 1 T46 1 T48 1 T50 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19 1 T4 2 T50 1 T31 2
auto[1] 12 1 T50 2 T29 1 T31 1



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15 1 T50 3 T364 2 T232 3
auto[1] 16 1 T4 2 T29 1 T31 3



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17 1 T4 1 T29 1 T31 1
auto[1] 14 1 T4 1 T50 3 T31 2



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19 1 T4 1 T50 2 T29 1
auto[1] 12 1 T4 1 T50 1 T31 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17 1 T50 3 T29 1 T31 1
auto[1] 14 1 T4 2 T31 2 T364 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 15 1 T50 1 T31 2 T364 3
auto[1] 16 1 T4 2 T50 2 T29 1



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 8 1 T50 1 T364 1 T232 2
auto[0] auto[1] 7 1 T50 2 T364 1 T232 1
auto[1] auto[0] 11 1 T4 2 T31 2 T364 1
auto[1] auto[1] 5 1 T29 1 T31 1 T93 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 9 1 T29 1 T31 1 T232 1
auto[0] auto[1] 10 1 T4 1 T50 2 T31 1
auto[1] auto[0] 8 1 T4 1 T364 3 T232 1
auto[1] auto[1] 4 1 T50 1 T31 1 T93 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 7 1 T50 1 T31 1 T364 1
auto[0] auto[1] 8 1 T31 1 T364 2 T170 1
auto[1] auto[0] 10 1 T50 2 T29 1 T232 1
auto[1] auto[1] 6 1 T4 2 T31 1 T232 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8 1 T4 3 T167 1 T81 2
auto[1] 4 1 T167 2 T81 1 T114 1



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4 1 T4 2 T81 2 - -
auto[1] 8 1 T4 1 T167 3 T81 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5 1 T167 2 T81 2 T114 1
auto[1] 7 1 T4 3 T167 1 T81 1



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8 1 T4 2 T167 2 T81 1
auto[1] 4 1 T4 1 T167 1 T81 2



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3 1 T4 1 T81 1 T114 1
auto[1] 9 1 T4 2 T167 3 T81 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2 1 T114 2 - - - -
auto[1] 10 1 T4 3 T167 3 T81 3



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 3 1 T4 2 T81 1 - -
auto[0] auto[1] 1 1 T81 1 - - - -
auto[1] auto[0] 5 1 T4 1 T167 1 T81 1
auto[1] auto[1] 3 1 T167 2 T114 1 - -



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 3 1 T167 1 T81 1 T114 1
auto[0] auto[1] 5 1 T4 2 T167 1 T114 2
auto[1] auto[0] 2 1 T167 1 T81 1 - -
auto[1] auto[1] 2 1 T4 1 T81 1 - -



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1 1 T114 1 - - - -
auto[0] auto[1] 1 1 T114 1 - - - -
auto[1] auto[0] 2 1 T4 1 T81 1 - -
auto[1] auto[1] 8 1 T4 2 T167 3 T81 2

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