Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1813

1

T1

27

T3

4

T4

6

auto[1]

659

1

T1

17

T3

2

T4

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1847

1

T1

44

T3

4

T5

16

auto[1]

625

1

T3

2

T4

9

T5

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1834

1

T1

44

T3

4

T4

3

auto[1]

638

1

T3

2

T4

6

T5

14

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1920

1

T1

44

T3

2

T4

9

auto[1]

552

1

T3

4

T24

5

T6

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2250

1

T1

44

T3

6

T4

9

auto[1]

222

1

T7

20

T8

14

T13

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2290

1

T1

44

T3

6

T4

9

auto[1]

182

1

T8

5

T13

5

T73

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2257

1

T1

38

T3

6

T4

9

auto[1]

215

1

T1

6

T8

6

T13

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296

1

T1

27

T3

6

T4

9

auto[1]

176

1

T1

17

T7

11

T13

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2201

1

T1

38

T3

6

T4

9

auto[1]

271

1

T1

6

T24

5

T7

31

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1957

1

T1

33

T4

6

T5

14

auto[1]

515

1

T1

11

T3

6

T4

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

764

1

T3

6

T4

9

T5

20

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

86

1

T8

8

T13

4

T87

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

70

1

T24

5

T8

5

T73

17

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

42

1

T7

20

T73

12

T74

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T1

11

T252

21

T254

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T334

2

T349

3

T342

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T7

11

T254

2

T264

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T102

3

T268

2

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T74

1

T102

8

T87

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T8

6

T253

5

T350

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T101

2

T256

6

T116

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T252

3

T342

2

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

19

1

T13

1

T73

5

T351

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T1

6

T102

5

T257

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T352

1

T267

3

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T13

5

T101

1

T258

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T353

1

T354

1

T342

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

21

1

T8

5

T74

2

T334

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T141

1

T349

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

16

1

T256

3

T339

2

T355

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T339

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T253

1

T258

1

T356

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

22

1

T73

2

T354

3

T351

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T335

1

T337

3

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T254

1

T357

3

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T88

4

T358

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

82

1

T1

6

T74

2

T253

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T73

5

T253

5

T359

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

71

1

T1

11

T5

6

T58

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

74

1

T87

7

T349

1

T342

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

47

1

T8

5

T74

2

T256

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T13

5

T180

3

T353

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T3

2

T6

2

T73

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

110

1

T5

10

T7

20

T97

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

92

1

T97

6

T82

10

T332

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T332

3

T83

4

T87

16

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T83

1

T256

3

T31

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T24

5

T6

3

T141

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T334

3

T360

5

T104

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T3

2

T8

8

T97

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T332

2

T236

3

T270

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

131

1

T8

5

T13

1

T73

17

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

69

1

T10

4

T256

9

T139

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T3

2

T8

6

T10

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T4

3

T254

2

T160

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T12

7

T58

1

T73

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T139

3

T359

2

T116

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T6

3

T12

4

T97

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T124

1

T58

1

T77

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T4

6

T124

6

T50

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

41

1

T5

4

T7

11

T58

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T13

4

T124

3

T77

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T6

1

T12

1

T252

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T12

3

T82

3

T236

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T180

1

T333

3

T247

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T121

1

T339

2

T270

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T121

1

T108

1

T336

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded