Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T39

10

T65

9

T42

26

auto[1]

1095

1

T39

10

T65

11

T42

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T39

4

T65

2

T42

9

from_0to1

517

1

T39

4

T65

1

T42

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1045

1

T39

12

T65

8

T42

23

auto[1]

1115

1

T39

8

T65

12

T42

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T39

8

T65

12

T42

19

auto[1]

1078

1

T39

12

T65

8

T42

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T69

1

T301

1

T263

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T39

3

T65

1

T42

3

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T42

2

T68

1

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T42

1

T70

1

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T39

1

T42

1

T263

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T39

1

T68

2

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T39

1

T42

1

T68

2

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T65

1

T42

2

T70

2

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T39

1

T42

1

T68

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T68

1

T69

1

T369

2

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T65

1

T42

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T42

1

T68

1

T70

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T42

1

T68

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T42

3

T69

1

T301

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T39

1

T68

2

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T42

1

T69

1

T301

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T39

7

T65

8

T42

28

auto[1]

1106

1

T39

13

T65

12

T42

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

528

1

T39

5

T65

5

T42

12

from_0to1

533

1

T39

5

T65

4

T42

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T39

9

T65

10

T42

22

auto[1]

1083

1

T39

11

T65

10

T42

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T39

7

T65

10

T42

14

auto[1]

1094

1

T39

13

T65

10

T42

26

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T65

1

T42

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T42

4

T369

1

T301

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T42

2

T369

2

T263

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T65

1

T42

3

T68

3

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T42

1

T68

1

T369

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T42

5

T69

1

T50

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T39

1

T65

1

T68

2

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T39

2

T65

1

T42

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T39

2

T65

1

T42

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T39

2

T65

1

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T39

1

T68

2

T50

2

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T65

1

T68

1

T301

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T65

1

T69

2

T369

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T65

1

T301

1

T263

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T42

3

T68

4

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T39

2

T42

2

T70

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T39

8

T65

5

T42

17

auto[1]

1102

1

T39

12

T65

15

T42

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T39

5

T65

4

T42

9

from_0to1

518

1

T39

4

T65

5

T42

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T39

11

T65

12

T42

24

auto[1]

1113

1

T39

9

T65

8

T42

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1074

1

T39

7

T65

10

T42

20

auto[1]

1086

1

T39

13

T65

10

T42

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T39

1

T65

1

T42

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T42

1

T68

1

T69

2

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T39

1

T70

1

T369

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T68

1

T69

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T65

1

T68

1

T69

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T42

2

T68

3

T369

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T42

1

T301

2

T50

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T42

3

T369

3

T301

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T42

2

T50

1

T370

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T39

1

T65

1

T42

2

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T65

1

T42

2

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T39

2

T65

1

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T39

1

T65

1

T42

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T65

1

T42

2

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T65

2

T68

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T39

3

T70

1

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T39

12

T65

12

T42

15

auto[1]

1110

1

T39

8

T65

8

T42

25

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

523

1

T39

5

T65

4

T42

11

from_0to1

522

1

T39

5

T65

3

T42

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T39

8

T65

10

T42

22

auto[1]

1064

1

T39

12

T65

10

T42

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T39

11

T65

9

T42

20

auto[1]

1087

1

T39

9

T65

11

T42

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T39

1

T42

1

T69

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T39

2

T65

1

T42

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T68

1

T69

1

T263

2

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T39

1

T70

1

T369

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T65

1

T42

2

T68

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T69

1

T369

1

T263

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T39

1

T65

1

T42

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T39

1

T65

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

82

1

T65

2

T42

2

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T42

3

T68

1

T69

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T39

1

T42

2

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T65

1

T42

2

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T42

2

T68

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T42

1

T68

2

T369

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T39

3

T42

1

T301

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T42

2

T69

1

T70

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T39

10

T65

12

T42

20

auto[1]

1062

1

T39

10

T65

8

T42

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T39

5

T65

4

T42

11

from_0to1

524

1

T39

4

T65

4

T42

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T39

7

T65

7

T42

19

auto[1]

1072

1

T39

13

T65

13

T42

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T39

5

T65

10

T42

23

auto[1]

1079

1

T39

15

T65

10

T42

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T42

3

T68

2

T69

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T42

1

T68

1

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T39

1

T65

3

T42

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T39

2

T65

1

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

80

1

T42

1

T69

1

T50

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T39

1

T65

1

T42

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T42

2

T68

1

T301

1

auto[0]

from_0to1

auto[1]

auto[1]

80

1

T39

1

T42

2

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T369

1

T50

1

T371

2

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T39

1

T42

1

T70

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T42

3

T369

1

T301

2

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T39

1

T42

1

T69

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T39

1

T65

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T42

1

T68

1

T369

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T65

1

T42

3

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T39

1

T65

1

T369

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T39

11

T65

9

T42

25

auto[1]

1074

1

T39

9

T65

11

T42

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T39

3

T65

5

T42

9

from_0to1

520

1

T39

3

T65

6

T42

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T39

13

T65

12

T42

20

auto[1]

1062

1

T39

7

T65

8

T42

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T39

6

T65

12

T42

16

auto[1]

1074

1

T39

14

T65

8

T42

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T42

2

T70

1

T369

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T39

2

T42

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T65

1

T69

2

T301

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T65

1

T42

2

T69

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T39

1

T65

2

T42

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T42

1

T369

1

T301

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T42

2

T263

1

T370

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T65

1

T42

2

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T39

1

T65

1

T42

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T42

1

T70

1

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T65

2

T68

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T42

2

T68

1

T369

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T65

3

T42

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T39

1

T68

1

T69

3

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T42

2

T68

1

T70

3

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T39

1

T42

1

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T39

9

T65

12

T42

24

auto[1]

1080

1

T39

11

T65

8

T42

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

542

1

T39

4

T65

2

T42

9

from_0to1

542

1

T39

5

T65

3

T42

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T39

9

T65

9

T42

13

auto[1]

1067

1

T39

11

T65

11

T42

27

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T39

14

T65

7

T42

13

auto[1]

1071

1

T39

6

T65

13

T42

27

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T39

1

T68

1

T369

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T69

1

T50

2

T219

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T39

3

T42

3

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T65

1

T42

3

T70

3

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T65

1

T42

1

T70

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T69

3

T70

1

T369

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T42

1

T68

1

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T39

2

T42

3

T369

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T68

1

T369

1

T302

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T65

1

T42

1

T369

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T42

1

T69

1

T369

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T42

1

T68

1

T69

2

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T39

2

T42

1

T68

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T42

2

T68

2

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T65

1

T369

2

T301

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T39

1

T65

1

T42

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T39

10

T65

13

T42

23

auto[1]

1071

1

T39

10

T65

7

T42

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T39

4

T65

4

T42

9

from_0to1

503

1

T39

5

T65

4

T42

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T39

7

T65

9

T42

19

auto[1]

1093

1

T39

13

T65

11

T42

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T39

6

T65

14

T42

20

auto[1]

1073

1

T39

14

T65

6

T42

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T42

2

T70

1

T369

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T39

1

T65

1

T42

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T65

2

T42

2

T70

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T39

1

T42

1

T68

2

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T65

1

T69

1

T369

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T39

1

T68

1

T219

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T65

1

T42

2

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T39

2

T42

1

T68

2

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T69

2

T301

2

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T70

1

T369

1

T263

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T39

1

T65

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T39

1

T42

2

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T39

1

T65

1

T42

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T42

2

T69

2

T263

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T65

1

T42

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T39

1

T42

2

T70

1