Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118894

1

T1

487

T2

4

T3

216

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142038	1			T1	449		T2	7		T3	391
values[0x0]	65532	1			T1	393		T2	1		T3	32
values[0x1]	66334	1			T1	385		T2	3		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148257

1

T1

597

T2

6

T3

261

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	814	1			T1	2		T4	4		T5	1
valid_sources[0x01]	864	1			T1	13		T4	7		T5	3
valid_sources[0x02]	1476	1			T1	13		T4	8		T5	2
valid_sources[0x03]	1243	1			T1	1		T4	6		T5	2
valid_sources[0x04]	1006	1			T1	1		T4	5		T5	3
valid_sources[0x05]	1447	1			T4	5		T5	2		T24	6
valid_sources[0x06]	1359	1			T4	7		T5	3		T24	2
valid_sources[0x07]	1933	1			T1	5		T4	1		T5	3
valid_sources[0x08]	911	1			T1	5		T4	3		T5	1
valid_sources[0x09]	1004	1			T1	5		T4	2		T5	3
valid_sources[0x0a]	1002	1			T1	4		T4	8		T5	2
valid_sources[0x0b]	852	1			T1	9		T4	3		T5	4
valid_sources[0x0c]	973	1			T1	1		T4	6		T24	5
valid_sources[0x0d]	1059	1			T1	6		T4	4		T5	1
valid_sources[0x0e]	996	1			T1	10		T4	5		T5	1
valid_sources[0x0f]	810	1			T4	2		T5	2		T24	6
valid_sources[0x10]	1003	1			T1	1		T4	5		T5	2
valid_sources[0x11]	978	1			T1	1		T4	2		T5	2
valid_sources[0x12]	892	1			T1	5		T4	6		T5	5
valid_sources[0x13]	999	1			T1	5		T4	9		T5	3
valid_sources[0x14]	1242	1			T1	4		T4	5		T5	8
valid_sources[0x15]	1214	1			T1	1		T4	7		T5	1
valid_sources[0x16]	1032	1			T1	7		T4	2		T5	3
valid_sources[0x17]	931	1			T1	7		T4	8		T5	2
valid_sources[0x18]	1229	1			T4	7		T5	3		T24	5
valid_sources[0x19]	1473	1			T1	2		T4	4		T5	3
valid_sources[0x1a]	812	1			T1	1		T4	5		T5	9
valid_sources[0x1b]	1013	1			T1	1		T4	5		T5	2
valid_sources[0x1c]	1030	1			T1	1		T4	1		T5	2
valid_sources[0x1d]	1001	1			T1	13		T4	4		T5	4
valid_sources[0x1e]	924	1			T1	12		T4	6		T5	1
valid_sources[0x1f]	842	1			T1	1		T4	7		T24	5
valid_sources[0x20]	979	1			T1	6		T4	7		T5	1
valid_sources[0x21]	930	1			T1	13		T4	11		T5	6
valid_sources[0x22]	827	1			T1	14		T4	4		T5	5
valid_sources[0x23]	783	1			T1	9		T4	6		T5	2
valid_sources[0x24]	908	1			T4	5		T24	4		T26	37
valid_sources[0x25]	953	1			T1	4		T5	1		T24	3
valid_sources[0x26]	794	1			T4	4		T5	1		T24	5
valid_sources[0x27]	963	1			T1	2		T4	1		T5	1
valid_sources[0x28]	899	1			T1	5		T4	8		T5	2
valid_sources[0x29]	898	1			T1	16		T4	2		T5	3
valid_sources[0x2a]	885	1			T1	1		T4	5		T24	6
valid_sources[0x2b]	2499	1			T4	6		T5	4		T24	5
valid_sources[0x2c]	947	1			T1	4		T4	2		T5	1
valid_sources[0x2d]	1368	1			T1	4		T4	7		T5	3
valid_sources[0x2e]	967	1			T1	4		T4	10		T5	1
valid_sources[0x2f]	826	1			T1	5		T4	5		T24	8
valid_sources[0x30]	1043	1			T1	4		T2	11		T4	6
valid_sources[0x31]	939	1			T4	7		T5	2		T24	4
valid_sources[0x32]	865	1			T1	2		T4	3		T24	8
valid_sources[0x33]	919	1			T1	4		T4	7		T5	2
valid_sources[0x34]	1090	1			T1	6		T4	7		T5	1
valid_sources[0x35]	1008	1			T1	9		T4	5		T24	6
valid_sources[0x36]	842	1			T1	1		T4	6		T5	2
valid_sources[0x37]	931	1			T1	8		T4	7		T5	2
valid_sources[0x38]	881	1			T1	5		T4	5		T5	4
valid_sources[0x39]	1119	1			T1	7		T4	3		T5	5
valid_sources[0x3a]	991	1			T1	2		T4	5		T5	3
valid_sources[0x3b]	906	1			T1	3		T4	6		T5	1
valid_sources[0x3c]	912	1			T1	2		T4	4		T24	4
valid_sources[0x3d]	1915	1			T1	6		T4	7		T5	2
valid_sources[0x3e]	847	1			T1	4		T4	5		T5	1
valid_sources[0x3f]	906	1			T1	1		T4	9		T5	1
valid_sources[0x40]	978	1			T1	14		T4	5		T24	1
valid_sources[0x41]	1067	1			T1	6		T4	6		T24	3
valid_sources[0x42]	1076	1			T1	2		T4	8		T5	3
valid_sources[0x43]	911	1			T1	5		T4	5		T5	2
valid_sources[0x44]	1402	1			T1	1		T4	6		T5	4
valid_sources[0x45]	1770	1			T1	1		T4	6		T5	4
valid_sources[0x46]	1112	1			T1	4		T4	4		T5	4
valid_sources[0x47]	966	1			T1	5		T4	3		T5	3
valid_sources[0x48]	932	1			T1	5		T4	4		T24	6
valid_sources[0x49]	979	1			T1	3		T4	3		T5	1
valid_sources[0x4a]	908	1			T1	3		T4	6		T5	1
valid_sources[0x4b]	1165	1			T1	4		T4	4		T24	7
valid_sources[0x4c]	1009	1			T1	5		T4	7		T5	4
valid_sources[0x4d]	1391	1			T1	2		T4	6		T5	2
valid_sources[0x4e]	747	1			T4	6		T5	4		T24	6
valid_sources[0x4f]	1536	1			T1	1		T4	3		T24	7
valid_sources[0x50]	1052	1			T1	6		T4	3		T5	3
valid_sources[0x51]	1117	1			T1	4		T4	5		T5	1
valid_sources[0x52]	849	1			T1	8		T4	5		T24	3
valid_sources[0x53]	1414	1			T1	2		T4	7		T5	6
valid_sources[0x54]	899	1			T1	4		T4	5		T6	2
valid_sources[0x55]	791	1			T4	2		T5	5		T24	5
valid_sources[0x56]	947	1			T1	14		T4	5		T5	1
valid_sources[0x57]	1400	1			T1	6		T4	5		T5	2
valid_sources[0x58]	1144	1			T1	3		T4	1		T5	5
valid_sources[0x59]	929	1			T1	5		T4	4		T5	4
valid_sources[0x5a]	1008	1			T1	5		T4	4		T5	2
valid_sources[0x5b]	1076	1			T1	10		T4	6		T5	2
valid_sources[0x5c]	994	1			T1	2		T4	4		T5	1
valid_sources[0x5d]	828	1			T1	4		T4	3		T5	3
valid_sources[0x5e]	913	1			T1	5		T4	4		T24	3
valid_sources[0x5f]	1068	1			T1	4		T4	2		T5	3
valid_sources[0x60]	907	1			T1	3		T4	5		T5	3
valid_sources[0x61]	831	1			T1	9		T4	2		T5	3
valid_sources[0x62]	2192	1			T1	14		T4	7		T5	5
valid_sources[0x63]	1009	1			T4	6		T5	4		T24	5
valid_sources[0x64]	847	1			T4	3		T5	1		T24	4
valid_sources[0x65]	982	1			T1	11		T4	3		T24	4
valid_sources[0x66]	1203	1			T4	3		T24	8		T6	1
valid_sources[0x67]	957	1			T1	3		T4	6		T5	2
valid_sources[0x68]	1222	1			T1	9		T4	8		T24	4
valid_sources[0x69]	916	1			T4	4		T5	1		T24	2
valid_sources[0x6a]	1056	1			T4	7		T5	5		T24	5
valid_sources[0x6b]	1728	1			T1	10		T4	2		T5	3
valid_sources[0x6c]	1423	1			T1	8		T4	6		T24	7
valid_sources[0x6d]	932	1			T1	4		T4	10		T5	3
valid_sources[0x6e]	877	1			T1	1		T4	6		T22	2
valid_sources[0x6f]	1064	1			T1	2		T4	5		T5	3
valid_sources[0x70]	938	1			T4	6		T5	1		T24	2
valid_sources[0x71]	1390	1			T1	6		T4	9		T5	2
valid_sources[0x72]	937	1			T1	1		T4	5		T24	6
valid_sources[0x73]	1100	1			T1	3		T4	7		T24	5
valid_sources[0x74]	1573	1			T1	16		T4	1		T5	4
valid_sources[0x75]	822	1			T1	1		T4	3		T5	3
valid_sources[0x76]	899	1			T1	13		T4	2		T5	1
valid_sources[0x77]	985	1			T1	2		T4	5		T5	4
valid_sources[0x78]	1046	1			T1	12		T4	1		T5	1
valid_sources[0x79]	1017	1			T1	1		T4	6		T5	1
valid_sources[0x7a]	1103	1			T1	3		T4	4		T5	2
valid_sources[0x7b]	839	1			T4	2		T5	1		T24	4
valid_sources[0x7c]	923	1			T1	3		T4	5		T5	2
valid_sources[0x7d]	818	1			T1	1		T4	12		T5	1
valid_sources[0x7e]	934	1			T1	1		T4	4		T24	4
valid_sources[0x7f]	970	1			T1	4		T4	3		T5	1
valid_sources[0x80]	895	1			T1	15		T4	6		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64666

1

T1

230

T2

2

T3

199

values[0x0]

all_enables

biggest_size

31757

1

T1

156

T2

1

T3

10

values[0x1]

all_enables

biggest_size

22471

1

T1

101

T2

1

T3

7