Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T41,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T41,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T41,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T41,T45
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T41,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T41,T45
0	1	Covered	T86,T105,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T41,T45
0	1	Covered	T4,T41,T45
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T41,T45
1	-	Covered	T4,T41,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T41,T45
DetectSt	168	Covered	T4,T41,T45
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T41,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T41,T45
DebounceSt->IdleSt	163	Covered	T49,T29,T56
DetectSt->IdleSt	186	Covered	T86,T105,T106
DetectSt->StableSt	191	Covered	T4,T41,T45
IdleSt->DebounceSt	148	Covered	T4,T41,T45
StableSt->IdleSt	206	Covered	T4,T41,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T41,T45
0	1	Covered	T4,T41,T45
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T41,T45
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T41,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T41,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T31,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T41,T45
DetectSt	-	-	-	-	1	-	-	Covered	T86,T105,T106
DetectSt	-	-	-	-	0	1	-	Covered	T4,T41,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T41,T45
StableSt	-	-	-	-	-	-	0	Covered	T4,T41,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	292	0	0
CntIncr_A	7822273	344022	0	0
CntNoWrap_A	7822273	7181251	0	0
DetectStDropOut_A	7822273	5	0	0
DetectedOut_A	7822273	917	0	0
DetectedPulseOut_A	7822273	132	0	0
DisabledIdleSt_A	7822273	6830892	0	0
DisabledNoDetection_A	7822273	6833084	0	0
EnterDebounceSt_A	7822273	158	0	0
EnterDetectSt_A	7822273	137	0	0
EnterStableSt_A	7822273	132	0	0
PulseIsPulse_A	7822273	132	0	0
StayInStableSt	7822273	785	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6901	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	131	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	292	0	0
T4	270392	10	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	6	0	0
T51	0	4	0	0
T98	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	344022	0	0
T4	270392	333	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	71	0	0
T45	0	35	0	0
T46	0	100	0	0
T47	0	137	0	0
T48	0	25	0	0
T49	0	100	0	0
T50	0	197	0	0
T51	0	122	0	0
T98	0	175	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181251	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261817	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5	0	0
T86	2275	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T111	0	1	0	0
T114	0	1	0	0
T115	524	0	0	0
T116	19880	0	0	0
T117	5166	0	0	0
T118	502	0	0	0
T119	793	0	0	0
T120	436	0	0	0
T121	20390	0	0	0
T122	523	0	0	0
T123	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	917	0	0
T4	270392	39	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	13	0	0
T45	0	10	0	0
T46	0	8	0	0
T47	0	9	0	0
T48	0	9	0	0
T49	0	7	0	0
T50	0	11	0	0
T51	0	16	0	0
T98	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	132	0	0
T4	270392	5	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T98	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6830892	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261263	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6833084	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261291	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	158	0	0
T4	270392	5	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T51	0	2	0	0
T98	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	137	0	0
T4	270392	5	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T98	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	132	0	0
T4	270392	5	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T98	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	132	0	0
T4	270392	5	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T98	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	785	0	0
T4	270392	34	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	12	0	0
T45	0	9	0	0
T46	0	7	0	0
T47	0	7	0	0
T48	0	8	0	0
T49	0	6	0	0
T50	0	8	0	0
T51	0	14	0	0
T98	0	18	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6901	0	0
T1	25224	29	0	0
T2	579	0	0	0
T3	9127	10	0	0
T4	270392	72	0	0
T5	20621	10	0	0
T6	0	13	0	0
T7	0	17	0	0
T22	4419	0	0	0
T23	425	1	0	0
T24	18732	30	0	0
T25	845	5	0	0
T26	5266	23	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	131	0	0
T4	270392	5	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T98	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T9,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T14
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T9,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T14,T21
0	1	Covered	T55,T95,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T14,T21
0	1	Unreachable
1	0	Covered	T4,T14,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T14
DetectSt	168	Covered	T4,T14,T21
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T14,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T14,T21
DebounceSt->IdleSt	163	Covered	T4,T9,T56
DetectSt->IdleSt	186	Covered	T55,T95,T96
DetectSt->StableSt	191	Covered	T4,T14,T21
IdleSt->DebounceSt	148	Covered	T4,T9,T14
StableSt->IdleSt	206	Covered	T4,T14,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T14
0	1	Covered	T4,T9,T14
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T14,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T9,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T14
DetectSt	-	-	-	-	1	-	-	Covered	T55,T95,T96
DetectSt	-	-	-	-	0	1	-	Covered	T4,T14,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T14,T21
StableSt	-	-	-	-	-	-	0	Covered	T4,T14,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	169	0	0
CntIncr_A	7822273	294729	0	0
CntNoWrap_A	7822273	7181374	0	0
DetectStDropOut_A	7822273	13	0	0
DetectedOut_A	7822273	39978	0	0
DetectedPulseOut_A	7822273	46	0	0
DisabledIdleSt_A	7822273	5529428	0	0
DisabledNoDetection_A	7822273	5531676	0	0
EnterDebounceSt_A	7822273	111	0	0
EnterDetectSt_A	7822273	59	0	0
EnterStableSt_A	7822273	46	0	0
PulseIsPulse_A	7822273	46	0	0
StayInStableSt	7822273	39932	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6901	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_sticky_sva.StableStDropOut_A	7822273	1041850	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	169	0	0
T4	270392	7	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	7	0	0
T14	0	4	0	0
T21	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T55	0	2	0	0
T56	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	294729	0	0
T4	270392	217000	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	553	0	0
T14	0	198	0	0
T21	0	14	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	72	0	0
T30	0	62	0	0
T31	0	73	0	0
T32	0	22	0	0
T55	0	94	0	0
T56	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181374	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261820	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	13	0	0
T30	586	0	0	0
T55	1149	1	0	0
T56	6404	0	0	0
T93	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T135	0	2	0	0
T136	0	4	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	19865	0	0	0
T140	718	0	0	0
T141	7456	0	0	0
T142	522	0	0	0
T143	702	0	0	0
T144	1353	0	0	0
T145	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	39978	0	0
T4	270392	44	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	120	0	0
T21	0	11	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	314	0	0
T30	0	38	0	0
T31	0	54	0	0
T33	0	307	0	0
T34	0	64	0	0
T131	0	668	0	0
T133	0	112	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	46	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T131	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5529428	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	44480	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5531676	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	44510	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	111	0	0
T4	270392	6	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	7	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	59	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T55	0	1	0	0
T131	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	46	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T131	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	46	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T131	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	39932	0	0
T4	270392	43	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	118	0	0
T21	0	10	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	313	0	0
T30	0	37	0	0
T31	0	53	0	0
T33	0	305	0	0
T34	0	63	0	0
T131	0	667	0	0
T133	0	111	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6901	0	0
T1	25224	29	0	0
T2	579	0	0	0
T3	9127	10	0	0
T4	270392	72	0	0
T5	20621	10	0	0
T6	0	13	0	0
T7	0	17	0	0
T22	4419	0	0	0
T23	425	1	0	0
T24	18732	30	0	0
T25	845	5	0	0
T26	5266	23	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1041850	0	0
T4	270392	187	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T14	0	54	0	0
T21	0	89	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	62	0	0
T30	0	31	0	0
T31	0	58	0	0
T33	0	791452	0	0
T34	0	191	0	0
T131	0	320	0	0
T133	0	317	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T23
1	1	Covered	T2,T4,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T9,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T14
1	0	Covered	T2,T4,T23
1	1	Covered	T4,T9,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T14
0	1	Covered	T92,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T14
0	1	Unreachable
1	0	Covered	T4,T9,T14

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T14
DetectSt	168	Covered	T4,T9,T14
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T9,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T14
DebounceSt->IdleSt	163	Covered	T21,T29,T55
DetectSt->IdleSt	186	Covered	T92,T93,T94
DetectSt->StableSt	191	Covered	T4,T9,T14
IdleSt->DebounceSt	148	Covered	T4,T9,T14
StableSt->IdleSt	206	Covered	T4,T9,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T14
0	1	Covered	T4,T9,T14
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T14
IdleSt	0	-	-	-	-	-	-	Covered	T2,T4,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T29,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T14
DetectSt	-	-	-	-	1	-	-	Covered	T92,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T14
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	142	0	0
CntIncr_A	7822273	175110	0	0
CntNoWrap_A	7822273	7181401	0	0
DetectStDropOut_A	7822273	6	0	0
DetectedOut_A	7822273	40935	0	0
DetectedPulseOut_A	7822273	48	0	0
DisabledIdleSt_A	7822273	5529428	0	0
DisabledNoDetection_A	7822273	5531676	0	0
EnterDebounceSt_A	7822273	89	0	0
EnterDetectSt_A	7822273	54	0	0
EnterStableSt_A	7822273	48	0	0
PulseIsPulse_A	7822273	48	0	0
StayInStableSt	7822273	40887	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_sticky_sva.StableStDropOut_A	7822273	1241215	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	142	0	0
T4	270392	4	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	4	0	0
T14	0	4	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	3	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	175110	0	0
T4	270392	50	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	156	0	0
T14	0	58	0	0
T21	0	81	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	51	0	0
T30	0	11	0	0
T31	0	23	0	0
T32	0	19	0	0
T55	0	37	0	0
T56	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181401	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261823	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6	0	0
T92	608	2	0	0
T93	0	2	0	0
T94	0	1	0	0
T137	0	1	0	0
T146	6423	0	0	0
T147	422	0	0	0
T148	26413	0	0	0
T149	537	0	0	0
T150	502	0	0	0
T151	18347	0	0	0
T152	494	0	0	0
T153	784	0	0	0
T154	19373	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40935	0	0
T4	270392	169	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	626	0	0
T14	0	7	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	4	0	0
T32	0	16	0	0
T33	0	790	0	0
T105	0	415	0	0
T131	0	391	0	0
T132	0	204	0	0
T133	0	294	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	48	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5529428	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	44480	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5531676	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	44510	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	89	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	3	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	54	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	48	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	48	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40887	0	0
T4	270392	167	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	624	0	0
T14	0	5	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	3	0	0
T32	0	15	0	0
T33	0	788	0	0
T105	0	414	0	0
T131	0	390	0	0
T132	0	203	0	0
T133	0	293	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1241215	0	0
T4	270392	217101	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	581	0	0
T14	0	308	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T30	0	116	0	0
T32	0	48	0	0
T33	0	790871	0	0
T105	0	211	0	0
T131	0	605	0	0
T132	0	265	0	0
T133	0	89	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T9,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T9,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T14
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T9,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T14
0	1	Covered	T55,T81,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T14
0	1	Unreachable
1	0	Covered	T4,T9,T14

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T9,T14
DetectSt	168	Covered	T4,T9,T14
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T9,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T14
DebounceSt->IdleSt	163	Covered	T56,T30,T31
DetectSt->IdleSt	186	Covered	T55,T81,T89
DetectSt->StableSt	191	Covered	T4,T9,T14
IdleSt->DebounceSt	148	Covered	T4,T9,T14
StableSt->IdleSt	206	Covered	T4,T9,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T9,T14
0	1	Covered	T4,T9,T14
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T9,T14
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T31,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T9,T14
DetectSt	-	-	-	-	1	-	-	Covered	T55,T81,T89
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T14
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	144	0	0
CntIncr_A	7822273	175166	0	0
CntNoWrap_A	7822273	7181399	0	0
DetectStDropOut_A	7822273	5	0	0
DetectedOut_A	7822273	946511	0	0
DetectedPulseOut_A	7822273	45	0	0
DisabledIdleSt_A	7822273	5529428	0	0
DisabledNoDetection_A	7822273	5531676	0	0
EnterDebounceSt_A	7822273	95	0	0
EnterDetectSt_A	7822273	50	0	0
EnterStableSt_A	7822273	45	0	0
PulseIsPulse_A	7822273	45	0	0
StayInStableSt	7822273	946466	0	0
gen_high_event_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_sticky_sva.StableStDropOut_A	7822273	524873	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	144	0	0
T4	270392	4	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	4	0	0
T14	0	4	0	0
T21	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T55	0	2	0	0
T56	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	175166	0	0
T4	270392	59	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	168	0	0
T14	0	28	0	0
T21	0	18	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	40	0	0
T30	0	54	0	0
T31	0	60	0	0
T32	0	45	0	0
T55	0	99	0	0
T56	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181399	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261823	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5	0	0
T30	586	0	0	0
T55	1149	1	0	0
T56	6404	0	0	0
T81	0	1	0	0
T89	0	3	0	0
T139	19865	0	0	0
T140	718	0	0	0
T141	7456	0	0	0
T142	522	0	0	0
T143	702	0	0	0
T144	1353	0	0	0
T145	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	946511	0	0
T4	270392	241	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	593	0	0
T14	0	20	0	0
T21	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	99	0	0
T32	0	5	0	0
T33	0	676985	0	0
T105	0	351	0	0
T132	0	333	0	0
T133	0	226	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	45	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5529428	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	44480	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5531676	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	44510	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	95	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	50	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T55	0	1	0	0
T105	0	1	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	45	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	45	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	2	0	0
T14	0	2	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T105	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	946466	0	0
T4	270392	239	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	591	0	0
T14	0	18	0	0
T21	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	98	0	0
T32	0	4	0	0
T33	0	676983	0	0
T105	0	350	0	0
T132	0	332	0	0
T133	0	225	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	524873	0	0
T4	270392	217033	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T9	0	614	0	0
T14	0	346	0	0
T21	0	106	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	319	0	0
T32	0	45	0	0
T33	0	87	0	0
T105	0	288	0	0
T132	0	130	0	0
T133	0	204	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T16,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T16,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T19
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T19
0	1	Covered	T132,T121,T105
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T19
1	-	Covered	T132,T121,T105

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T17,T19
DetectSt	168	Covered	T16,T17,T19
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T16,T17,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T17,T19
DebounceSt->IdleSt	163	Covered	T56
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T16,T17,T19
IdleSt->DebounceSt	148	Covered	T16,T17,T19
StableSt->IdleSt	206	Covered	T132,T80,T121

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T19
0	1	Covered	T16,T17,T19
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T19
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T19
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T132,T80,T121
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	65	0	0
CntIncr_A	7822273	64326	0	0
CntNoWrap_A	7822273	7181478	0	0
DetectStDropOut_A	7822273	1	0	0
DetectedOut_A	7822273	6469	0	0
DetectedPulseOut_A	7822273	31	0	0
DisabledIdleSt_A	7822273	6901683	0	0
DisabledNoDetection_A	7822273	6903879	0	0
EnterDebounceSt_A	7822273	33	0	0
EnterDetectSt_A	7822273	32	0	0
EnterStableSt_A	7822273	31	0	0
PulseIsPulse_A	7822273	31	0	0
StayInStableSt	7822273	6420	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	65	0	0
T16	701	2	0	0
T17	473	2	0	0
T18	620	0	0	0
T19	473	2	0	0
T46	690	0	0	0
T56	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	2	0	0
T85	0	2	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	64326	0	0
T16	701	40	0	0
T17	473	11	0	0
T18	620	0	0	0
T19	473	11	0	0
T46	690	0	0	0
T56	0	20	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	28	0	0
T85	0	53	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	11	0	0
T155	0	96	0	0
T156	0	67	0	0
T157	0	59541	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181478	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1	0	0
T85	906	1	0	0
T158	718	0	0	0
T159	406	0	0	0
T160	11228	0	0	0
T161	63252	0	0	0
T162	418	0	0	0
T163	932	0	0	0
T164	402	0	0	0
T165	776	0	0	0
T166	11013	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6469	0	0
T16	701	175	0	0
T17	473	40	0	0
T18	620	0	0	0
T19	473	38	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	20	0	0
T99	422	0	0	0
T100	4424	0	0	0
T105	0	57	0	0
T121	0	190	0	0
T132	0	66	0	0
T155	0	303	0	0
T156	0	142	0	0
T157	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	31	0	0
T16	701	1	0	0
T17	473	1	0	0
T18	620	0	0	0
T19	473	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T105	0	1	0	0
T121	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6901683	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6903879	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	33	0	0
T16	701	1	0	0
T17	473	1	0	0
T18	620	0	0	0
T19	473	1	0	0
T46	690	0	0	0
T56	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	32	0	0
T16	701	1	0	0
T17	473	1	0	0
T18	620	0	0	0
T19	473	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T121	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	31	0	0
T16	701	1	0	0
T17	473	1	0	0
T18	620	0	0	0
T19	473	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T105	0	1	0	0
T121	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	31	0	0
T16	701	1	0	0
T17	473	1	0	0
T18	620	0	0	0
T19	473	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T105	0	1	0	0
T121	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6420	0	0
T16	701	173	0	0
T17	473	38	0	0
T18	620	0	0	0
T19	473	36	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T80	0	19	0	0
T99	422	0	0	0
T100	4424	0	0	0
T105	0	56	0	0
T121	0	189	0	0
T132	0	65	0	0
T155	0	301	0	0
T156	0	140	0	0
T157	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	12	0	0
T81	0	1	0	0
T85	906	0	0	0
T105	0	1	0	0
T121	0	1	0	0
T132	14481	1	0	0
T158	718	0	0	0
T159	406	0	0	0
T160	11228	0	0	0
T161	63252	0	0	0
T162	418	0	0	0
T163	932	0	0	0
T164	402	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	562	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T11,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T11,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T15
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T15
0	1	Covered	T11,T15,T17
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T15
1	-	Covered	T11,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T15
DetectSt	168	Covered	T4,T11,T15
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T11,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T15
DebounceSt->IdleSt	163	Covered	T56,T157,T174
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T4,T11,T15
IdleSt->DebounceSt	148	Covered	T4,T11,T15
StableSt->IdleSt	206	Covered	T4,T11,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T15
0	1	Covered	T4,T11,T15
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T157,T174,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T15
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	158	0	0
CntIncr_A	7822273	273061	0	0
CntNoWrap_A	7822273	7181385	0	0
DetectStDropOut_A	7822273	1	0	0
DetectedOut_A	7822273	56792	0	0
DetectedPulseOut_A	7822273	74	0	0
DisabledIdleSt_A	7822273	6649666	0	0
DisabledNoDetection_A	7822273	6651853	0	0
EnterDebounceSt_A	7822273	83	0	0
EnterDetectSt_A	7822273	75	0	0
EnterStableSt_A	7822273	74	0	0
PulseIsPulse_A	7822273	74	0	0
StayInStableSt	7822273	56685	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	2645	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	158	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	4	0	0
T15	0	4	0	0
T17	0	2	0	0
T18	0	4	0	0
T20	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T44	0	2	0	0
T50	0	2	0	0
T56	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	273061	0	0
T4	270392	100	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	136	0	0
T15	0	109440	0	0
T17	0	11	0	0
T18	0	26	0	0
T20	0	49	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	50	0	0
T44	0	18	0	0
T50	0	75	0	0
T56	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181385	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261825	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1	0	0
T32	221565	0	0	0
T43	6003	0	0	0
T84	618	1	0	0
T155	1176	0	0	0
T175	617	0	0	0
T176	1118	0	0	0
T177	522	0	0	0
T178	405	0	0	0
T179	406	0	0	0
T180	16298	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	56792	0	0
T4	270392	348	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	68	0	0
T15	0	7947	0	0
T17	0	1	0	0
T18	0	106	0	0
T20	0	84	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	73	0	0
T44	0	74	0	0
T50	0	66	0	0
T84	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	74	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T84	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6649666	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261267	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6651853	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261296	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	83	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	75	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T84	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	74	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T84	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	74	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T84	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	56685	0	0
T4	270392	346	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	66	0	0
T15	0	7945	0	0
T18	0	103	0	0
T20	0	82	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	71	0	0
T43	0	47	0	0
T44	0	72	0	0
T50	0	64	0	0
T84	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2645	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	34	0	0
T5	20621	0	0	0
T10	0	5	0	0
T11	0	2	0	0
T22	4419	0	0	0
T23	425	3	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T35	0	4	0	0
T39	0	14	0	0
T40	0	6	0	0
T126	0	1	0	0
T128	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T32	0	2	0	0
T43	0	1	0	0
T52	2227	0	0	0
T84	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	1	0	0