Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T10,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T18,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T18,T44
0	1	Covered	T132
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T18,T44
0	1	Covered	T10,T18,T29
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T18,T44
1	-	Covered	T10,T18,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T18,T44
DetectSt	168	Covered	T10,T18,T44
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T10,T18,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T18,T44
DebounceSt->IdleSt	163	Covered	T56,T32,T91
DetectSt->IdleSt	186	Covered	T132
DetectSt->StableSt	191	Covered	T10,T18,T44
IdleSt->DebounceSt	148	Covered	T10,T18,T44
StableSt->IdleSt	206	Covered	T10,T18,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T18,T44
0	1	Covered	T10,T18,T44
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T18,T44
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T18,T44
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T18,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T91,T181,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T18,T44
DetectSt	-	-	-	-	1	-	-	Covered	T132
DetectSt	-	-	-	-	0	1	-	Covered	T10,T18,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T18,T29
StableSt	-	-	-	-	-	-	0	Covered	T10,T18,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	88	0	0
CntIncr_A	7822273	4715	0	0
CntNoWrap_A	7822273	7181455	0	0
DetectStDropOut_A	7822273	1	0	0
DetectedOut_A	7822273	2443	0	0
DetectedPulseOut_A	7822273	41	0	0
DisabledIdleSt_A	7822273	6653691	0	0
DisabledNoDetection_A	7822273	6655886	0	0
EnterDebounceSt_A	7822273	47	0	0
EnterDetectSt_A	7822273	42	0	0
EnterStableSt_A	7822273	41	0	0
PulseIsPulse_A	7822273	41	0	0
StayInStableSt	7822273	2380	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	88	0	0
T10	20651	2	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	4	0	0
T29	0	4	0	0
T32	0	4	0	0
T44	0	2	0	0
T56	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	4715	0	0
T10	20651	26	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	26	0	0
T29	0	130	0	0
T32	0	2325	0	0
T44	0	18	0	0
T56	0	20	0	0
T90	0	76	0	0
T91	0	175	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	11	0	0
T156	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181455	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1	0	0
T85	906	0	0	0
T132	14481	1	0	0
T158	718	0	0	0
T159	406	0	0	0
T160	11228	0	0	0
T161	63252	0	0	0
T162	418	0	0	0
T163	932	0	0	0
T164	402	0	0	0
T173	562	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2443	0	0
T10	20651	9	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	53	0	0
T29	0	82	0	0
T32	0	164	0	0
T44	0	73	0	0
T80	0	19	0	0
T90	0	39	0	0
T91	0	92	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	41	0	0
T158	0	24	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T10	20651	1	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T80	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6653691	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6655886	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	47	0	0
T10	20651	1	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T32	0	3	0	0
T44	0	1	0	0
T56	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	42	0	0
T10	20651	1	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T10	20651	1	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T80	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T10	20651	1	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T44	0	1	0	0
T80	0	1	0	0
T90	0	1	0	0
T91	0	2	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2380	0	0
T10	20651	8	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	50	0	0
T29	0	79	0	0
T32	0	160	0	0
T44	0	71	0	0
T80	0	18	0	0
T90	0	37	0	0
T91	0	88	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	40	0	0
T158	0	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	18	0	0
T10	20651	1	0	0
T11	832	0	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T18	0	1	0	0
T29	0	1	0	0
T121	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T156	0	1	0	0
T158	0	1	0	0
T174	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T149,T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T10,T11,T16
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T15
1	-	Covered	T10,T11,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T11
DetectSt	168	Covered	T10,T11,T15
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T10,T11,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T15
DebounceSt->IdleSt	163	Covered	T2,T56,T173
DetectSt->IdleSt	186	Covered	T149,T169
DetectSt->StableSt	191	Covered	T10,T11,T15
IdleSt->DebounceSt	148	Covered	T2,T10,T11
StableSt->IdleSt	206	Covered	T10,T11,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T11
0	1	Covered	T2,T10,T11
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T173,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T149,T169
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T16
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	149	0	0
CntIncr_A	7822273	245053	0	0
CntNoWrap_A	7822273	7181394	0	0
DetectStDropOut_A	7822273	2	0	0
DetectedOut_A	7822273	413937	0	0
DetectedPulseOut_A	7822273	68	0	0
DisabledIdleSt_A	7822273	6483220	0	0
DisabledNoDetection_A	7822273	6485409	0	0
EnterDebounceSt_A	7822273	79	0	0
EnterDetectSt_A	7822273	70	0	0
EnterStableSt_A	7822273	68	0	0
PulseIsPulse_A	7822273	68	0	0
StayInStableSt	7822273	413841	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	3066	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	149	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	4	0	0
T11	0	2	0	0
T15	0	2	0	0
T16	0	2	0	0
T19	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T43	0	2	0	0
T56	0	1	0	0
T59	0	2	0	0
T84	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	245053	0	0
T2	579	85	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	52	0	0
T11	0	68	0	0
T15	0	54720	0	0
T16	0	40	0	0
T19	0	11	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T43	0	36	0	0
T56	0	20	0	0
T59	0	12	0	0
T84	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181394	0	0
T1	25224	24762	0	0
T2	579	177	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2	0	0
T149	537	1	0	0
T150	502	0	0	0
T151	18347	0	0	0
T152	494	0	0	0
T153	784	0	0	0
T154	19373	0	0	0
T169	0	1	0	0
T186	10674	0	0	0
T187	503	0	0	0
T188	422	0	0	0
T189	413	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	413937	0	0
T10	20651	94	0	0
T11	832	43	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	172191	0	0
T16	0	157	0	0
T19	0	2	0	0
T32	0	151505	0	0
T43	0	99	0	0
T59	0	38	0	0
T84	0	57	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	194	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T32	0	3	0	0
T43	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6483220	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6485409	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	79	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T43	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	70	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T32	0	3	0	0
T43	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T32	0	3	0	0
T43	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T32	0	3	0	0
T43	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	413841	0	0
T10	20651	91	0	0
T11	832	42	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	172189	0	0
T16	0	156	0	0
T19	0	1	0	0
T32	0	151502	0	0
T43	0	98	0	0
T59	0	36	0	0
T84	0	56	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	192	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	3066	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	41	0	0
T5	20621	0	0	0
T10	0	11	0	0
T11	0	1	0	0
T22	4419	0	0	0
T23	425	1	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T35	0	5	0	0
T39	0	16	0	0
T125	0	4	0	0
T126	0	2	0	0
T127	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	39	0	0
T10	20651	1	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T32	0	3	0	0
T43	0	1	0	0
T84	0	1	0	0
T91	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	2	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T11,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T15
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T11,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T16
0	1	Covered	T17,T190
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T16
0	1	Covered	T4,T11,T16
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T16
1	-	Covered	T4,T11,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T16
DetectSt	168	Covered	T4,T11,T16
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T11,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T16
DebounceSt->IdleSt	163	Covered	T20,T56,T191
DetectSt->IdleSt	186	Covered	T17,T190
DetectSt->StableSt	191	Covered	T4,T11,T16
IdleSt->DebounceSt	148	Covered	T4,T11,T16
StableSt->IdleSt	206	Covered	T4,T11,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T16
0	1	Covered	T4,T11,T16
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T16
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T191,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T16
DetectSt	-	-	-	-	1	-	-	Covered	T17,T190
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T16
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T16
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	124	0	0
CntIncr_A	7822273	59846	0	0
CntNoWrap_A	7822273	7181419	0	0
DetectStDropOut_A	7822273	2	0	0
DetectedOut_A	7822273	160843	0	0
DetectedPulseOut_A	7822273	56	0	0
DisabledIdleSt_A	7822273	6714403	0	0
DisabledNoDetection_A	7822273	6716602	0	0
EnterDebounceSt_A	7822273	66	0	0
EnterDetectSt_A	7822273	58	0	0
EnterStableSt_A	7822273	56	0	0
PulseIsPulse_A	7822273	56	0	0
StayInStableSt	7822273	160765	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	124	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	4	0	0
T16	0	2	0	0
T17	0	2	0	0
T18	0	6	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T50	0	2	0	0
T56	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	59846	0	0
T4	270392	100	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	136	0	0
T16	0	40	0	0
T17	0	11	0	0
T18	0	39	0	0
T20	0	49	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	65	0	0
T32	0	49993	0	0
T50	0	75	0	0
T56	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181419	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261825	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2	0	0
T17	473	1	0	0
T18	620	0	0	0
T19	473	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T100	4424	0	0	0
T190	0	1	0	0
T193	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	160843	0	0
T4	270392	152	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	66	0	0
T16	0	40	0	0
T18	0	117	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	40	0	0
T32	0	151341	0	0
T50	0	40	0	0
T91	0	366	0	0
T132	0	124	0	0
T156	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	56	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T16	0	1	0	0
T18	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T50	0	1	0	0
T91	0	4	0	0
T132	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6714403	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261267	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6716602	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261296	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	66	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	58	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T50	0	1	0	0
T91	0	4	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	56	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T16	0	1	0	0
T18	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T50	0	1	0	0
T91	0	4	0	0
T132	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	56	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T16	0	1	0	0
T18	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T50	0	1	0	0
T91	0	4	0	0
T132	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	160765	0	0
T4	270392	151	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	64	0	0
T16	0	39	0	0
T18	0	113	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	38	0	0
T32	0	151340	0	0
T50	0	38	0	0
T91	0	361	0	0
T132	0	123	0	0
T156	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	33	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T16	0	1	0	0
T18	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T32	0	1	0	0
T91	0	3	0	0
T132	0	1	0	0
T156	0	1	0	0
T167	0	1	0	0
T183	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T11,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T15
1	0	Covered	T1,T3,T4
1	1	Covered	T11,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T16,T17
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T16,T17
0	1	Covered	T11,T84,T32
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T16,T17
1	-	Covered	T11,T84,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T16,T17
DetectSt	168	Covered	T11,T16,T17
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T11,T16,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T16,T17
DebounceSt->IdleSt	163	Covered	T56,T137,T138
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T16,T17
IdleSt->DebounceSt	148	Covered	T11,T16,T17
StableSt->IdleSt	206	Covered	T11,T84,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T16,T17
0	1	Covered	T11,T16,T17
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T137,T138
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T16,T17
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T16,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T84,T32
StableSt	-	-	-	-	-	-	0	Covered	T11,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	97	0	0
CntIncr_A	7822273	68157	0	0
CntNoWrap_A	7822273	7181446	0	0
DetectStDropOut_A	7822273	0	0	0
DetectedOut_A	7822273	6375	0	0
DetectedPulseOut_A	7822273	47	0	0
DisabledIdleSt_A	7822273	6672004	0	0
DisabledNoDetection_A	7822273	6674190	0	0
EnterDebounceSt_A	7822273	50	0	0
EnterDetectSt_A	7822273	47	0	0
EnterStableSt_A	7822273	47	0	0
PulseIsPulse_A	7822273	47	0	0
StayInStableSt	7822273	6302	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6606	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	97	0	0
T11	832	4	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	2	0	0
T17	0	2	0	0
T20	0	2	0	0
T32	0	4	0	0
T52	2227	0	0	0
T56	0	1	0	0
T84	0	2	0	0
T90	0	2	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	2	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68157	0	0
T11	832	136	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	40	0	0
T17	0	11	0	0
T20	0	49	0	0
T32	0	152	0	0
T52	2227	0	0	0
T56	0	19	0	0
T84	0	13	0	0
T90	0	76	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	11	0	0
T156	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181446	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6375	0	0
T11	832	81	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	95	0	0
T17	0	41	0	0
T20	0	42	0	0
T32	0	85	0	0
T52	2227	0	0	0
T84	0	125	0	0
T85	0	234	0	0
T90	0	233	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	45	0	0
T156	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	47	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	0	1	0	0
T32	0	2	0	0
T52	2227	0	0	0
T84	0	1	0	0
T85	0	2	0	0
T90	0	1	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6672004	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6674190	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	50	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	0	1	0	0
T32	0	2	0	0
T52	2227	0	0	0
T56	0	1	0	0
T84	0	1	0	0
T90	0	1	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	47	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	0	1	0	0
T32	0	2	0	0
T52	2227	0	0	0
T84	0	1	0	0
T85	0	2	0	0
T90	0	1	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	47	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	0	1	0	0
T32	0	2	0	0
T52	2227	0	0	0
T84	0	1	0	0
T85	0	2	0	0
T90	0	1	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	47	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T20	0	1	0	0
T32	0	2	0	0
T52	2227	0	0	0
T84	0	1	0	0
T85	0	2	0	0
T90	0	1	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6302	0	0
T11	832	78	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	93	0	0
T17	0	39	0	0
T20	0	40	0	0
T32	0	82	0	0
T52	2227	0	0	0
T84	0	124	0	0
T85	0	231	0	0
T90	0	231	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T132	0	43	0	0
T156	0	139	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6606	0	0
T1	25224	31	0	0
T2	579	0	0	0
T3	9127	13	0	0
T4	270392	70	0	0
T5	20621	12	0	0
T6	0	10	0	0
T7	0	29	0	0
T22	4419	0	0	0
T23	425	3	0	0
T24	18732	43	0	0
T25	845	5	0	0
T26	5266	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	20	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T32	0	1	0	0
T52	2227	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T167	0	1	0	0
T183	0	1	0	0
T185	0	2	0	0
T192	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T10,T11,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T15
1	0	Covered	T1,T3,T4
1	1	Covered	T10,T11,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T90,T167,T195
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T15
0	1	Covered	T10,T11,T44
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T15
1	-	Covered	T10,T11,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T15
DetectSt	168	Covered	T10,T11,T15
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T10,T11,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T15
DebounceSt->IdleSt	163	Covered	T20,T44,T56
DetectSt->IdleSt	186	Covered	T90,T167,T195
DetectSt->StableSt	191	Covered	T10,T11,T15
IdleSt->DebounceSt	148	Covered	T10,T11,T15
StableSt->IdleSt	206	Covered	T10,T11,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T15
0	1	Covered	T10,T11,T15
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T44,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T15
DetectSt	-	-	-	-	1	-	-	Covered	T90,T167,T195
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T44
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	150	0	0
CntIncr_A	7822273	254089	0	0
CntNoWrap_A	7822273	7181393	0	0
DetectStDropOut_A	7822273	3	0	0
DetectedOut_A	7822273	125629	0	0
DetectedPulseOut_A	7822273	68	0	0
DisabledIdleSt_A	7822273	6462515	0	0
DisabledNoDetection_A	7822273	6464705	0	0
EnterDebounceSt_A	7822273	79	0	0
EnterDetectSt_A	7822273	71	0	0
EnterStableSt_A	7822273	68	0	0
PulseIsPulse_A	7822273	68	0	0
StayInStableSt	7822273	125532	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	150	0	0
T10	20651	4	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	2	0	0
T16	0	2	0	0
T18	0	2	0	0
T20	0	1	0	0
T29	0	4	0	0
T44	0	3	0	0
T56	0	1	0	0
T84	0	6	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	254089	0	0
T10	20651	52	0	0
T11	832	68	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	54720	0	0
T16	0	40	0	0
T18	0	13	0	0
T20	0	49	0	0
T29	0	130	0	0
T44	0	36	0	0
T56	0	20	0	0
T84	0	39	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181393	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	3	0	0
T90	986	1	0	0
T91	12100	0	0	0
T167	0	1	0	0
T195	0	1	0	0
T196	704	0	0	0
T197	427	0	0	0
T198	38537	0	0	0
T199	409	0	0	0
T200	402	0	0	0
T201	16895	0	0	0
T202	455	0	0	0
T203	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	125629	0	0
T10	20651	104	0	0
T11	832	156	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	116078	0	0
T16	0	251	0	0
T18	0	174	0	0
T29	0	151	0	0
T32	0	109	0	0
T43	0	126	0	0
T44	0	11	0	0
T84	0	43	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	1	0	0
T29	0	2	0	0
T32	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T84	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6462515	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6464705	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	79	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	1	0	0
T20	0	1	0	0
T29	0	2	0	0
T44	0	2	0	0
T56	0	1	0	0
T84	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	71	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	1	0	0
T29	0	2	0	0
T32	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T84	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	1	0	0
T29	0	2	0	0
T32	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T84	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68	0	0
T10	20651	2	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	1	0	0
T29	0	2	0	0
T32	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T84	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	125532	0	0
T10	20651	101	0	0
T11	832	155	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T15	0	116076	0	0
T16	0	249	0	0
T18	0	172	0	0
T29	0	148	0	0
T32	0	106	0	0
T43	0	123	0	0
T44	0	10	0	0
T84	0	39	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	38	0	0
T10	20651	1	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T84	0	2	0	0
T121	0	1	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T167	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T29,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T11,T29,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T29,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T15
1	0	Covered	T1,T3,T4
1	1	Covered	T11,T29,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T29,T43
0	1	Covered	T167,T172,T204
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T29,T43
0	1	Covered	T29,T43,T90
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T29,T43
1	-	Covered	T29,T43,T90

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T29,T56
DetectSt	168	Covered	T11,T29,T43
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T11,T29,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T29,T43
DebounceSt->IdleSt	163	Covered	T56,T173,T192
DetectSt->IdleSt	186	Covered	T167,T172,T204
DetectSt->StableSt	191	Covered	T11,T29,T43
IdleSt->DebounceSt	148	Covered	T11,T29,T56
StableSt->IdleSt	206	Covered	T29,T43,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T29,T56
0	1	Covered	T11,T29,T56
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T29,T43
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T29,T56
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T29,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T173,T192,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T29,T56
DetectSt	-	-	-	-	1	-	-	Covered	T167,T172,T204
DetectSt	-	-	-	-	0	1	-	Covered	T11,T29,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T43,T90
StableSt	-	-	-	-	-	-	0	Covered	T11,T29,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	91	0	0
CntIncr_A	7822273	8810	0	0
CntNoWrap_A	7822273	7181452	0	0
DetectStDropOut_A	7822273	3	0	0
DetectedOut_A	7822273	3051	0	0
DetectedPulseOut_A	7822273	40	0	0
DisabledIdleSt_A	7822273	6834182	0	0
DisabledNoDetection_A	7822273	6836375	0	0
EnterDebounceSt_A	7822273	48	0	0
EnterDetectSt_A	7822273	43	0	0
EnterStableSt_A	7822273	40	0	0
PulseIsPulse_A	7822273	40	0	0
StayInStableSt	7822273	2993	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6309	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	91	0	0
T11	832	2	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T43	0	2	0	0
T52	2227	0	0	0
T56	0	1	0	0
T80	0	2	0	0
T85	0	2	0	0
T90	0	4	0	0
T91	0	10	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T173	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	8810	0	0
T11	832	68	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	65	0	0
T32	0	76	0	0
T43	0	36	0	0
T52	2227	0	0	0
T56	0	19	0	0
T80	0	28	0	0
T85	0	53	0	0
T90	0	152	0	0
T91	0	360	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T173	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181452	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	3	0	0
T167	18346	1	0	0
T172	0	1	0	0
T174	5690	0	0	0
T204	0	1	0	0
T205	418	0	0	0
T206	1305	0	0	0
T207	4971	0	0	0
T208	502	0	0	0
T209	6225	0	0	0
T210	501	0	0	0
T211	523	0	0	0
T212	1411	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	3051	0	0
T11	832	38	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	25	0	0
T32	0	42	0	0
T43	0	22	0	0
T52	2227	0	0	0
T80	0	19	0	0
T85	0	151	0	0
T90	0	325	0	0
T91	0	237	0	0
T97	28371	0	0	0
T121	0	107	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T213	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T52	2227	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T97	28371	0	0	0
T121	0	1	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6834182	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6836375	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	48	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T52	2227	0	0	0
T56	0	1	0	0
T80	0	1	0	0
T85	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T97	28371	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	43	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T52	2227	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T97	28371	0	0	0
T121	0	1	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T52	2227	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T97	28371	0	0	0
T121	0	1	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T52	2227	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T97	28371	0	0	0
T121	0	1	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2993	0	0
T11	832	36	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T29	0	24	0	0
T32	0	40	0	0
T43	0	21	0	0
T52	2227	0	0	0
T80	0	18	0	0
T85	0	150	0	0
T90	0	322	0	0
T91	0	230	0	0
T97	28371	0	0	0
T121	0	106	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T213	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6309	0	0
T1	25224	28	0	0
T2	579	0	0	0
T3	9127	13	0	0
T4	270392	46	0	0
T5	20621	8	0	0
T6	0	10	0	0
T7	0	29	0	0
T22	4419	0	0	0
T23	425	1	0	0
T24	18732	31	0	0
T25	845	0	0	0
T26	5266	26	0	0
T28	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	21	0	0
T29	12777	1	0	0
T43	0	1	0	0
T55	1149	0	0	0
T59	427003	0	0	0
T64	492	0	0	0
T85	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T121	0	1	0	0
T167	0	2	0	0
T168	0	1	0	0
T213	0	1	0	0
T214	0	1	0	0
T215	405	0	0	0
T216	2365	0	0	0
T217	64541	0	0	0
T218	528	0	0	0
T219	2443	0	0	0
T220	679	0	0	0