Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T11
0	1	Covered	T221
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T11
0	1	Covered	T10,T11,T16
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T10,T11
1	-	Covered	T10,T11,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T11
DetectSt	168	Covered	T2,T10,T11
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T11
DebounceSt->IdleSt	163	Covered	T56,T32,T91
DetectSt->IdleSt	186	Covered	T221
DetectSt->StableSt	191	Covered	T2,T10,T11
IdleSt->DebounceSt	148	Covered	T2,T10,T11
StableSt->IdleSt	206	Covered	T10,T11,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T10,T11
0	1	Covered	T2,T10,T11
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T91,T222
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T221
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T16
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	135	0	0
CntIncr_A	7822273	158029	0	0
CntNoWrap_A	7822273	7181408	0	0
DetectStDropOut_A	7822273	1	0	0
DetectedOut_A	7822273	67818	0	0
DetectedPulseOut_A	7822273	65	0	0
DisabledIdleSt_A	7822273	6665988	0	0
DisabledNoDetection_A	7822273	6668180	0	0
EnterDebounceSt_A	7822273	70	0	0
EnterDetectSt_A	7822273	66	0	0
EnterStableSt_A	7822273	65	0	0
PulseIsPulse_A	7822273	65	0	0
StayInStableSt	7822273	67730	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	135	0	0
T2	579	2	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T15	0	2	0	0
T16	0	2	0	0
T18	0	4	0	0
T19	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	4	0	0
T56	0	1	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	158029	0	0
T2	579	85	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	26	0	0
T11	0	68	0	0
T15	0	54720	0	0
T16	0	40	0	0
T18	0	26	0	0
T19	0	11	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	130	0	0
T56	0	19	0	0
T84	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181408	0	0
T1	25224	24762	0	0
T2	579	176	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1	0	0
T221	3396	1	0	0
T223	14845	0	0	0
T224	596	0	0	0
T225	521	0	0	0
T226	501	0	0	0
T227	532	0	0	0
T228	493	0	0	0
T229	568	0	0	0
T230	495	0	0	0
T231	441	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	67818	0	0
T2	579	41	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	86	0	0
T11	0	136	0	0
T15	0	61317	0	0
T16	0	117	0	0
T18	0	63	0	0
T19	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	26	0	0
T84	0	97	0	0
T155	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	65	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	2	0	0
T84	0	2	0	0
T155	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6665988	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6668180	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	70	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	2	0	0
T56	0	1	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	66	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	2	0	0
T84	0	2	0	0
T155	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	65	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	2	0	0
T84	0	2	0	0
T155	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	65	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	2	0	0
T84	0	2	0	0
T155	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	67730	0	0
T2	579	39	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T10	0	85	0	0
T11	0	135	0	0
T15	0	61315	0	0
T16	0	116	0	0
T18	0	61	0	0
T19	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	24	0	0
T84	0	94	0	0
T155	0	156	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T10	20651	1	0	0
T11	832	1	0	0
T12	14937	0	0	0
T13	24272	0	0	0
T14	1253	0	0	0
T16	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T29	0	2	0	0
T84	0	1	0	0
T91	0	3	0	0
T126	423	0	0	0
T127	911	0	0	0
T128	421	0	0	0
T129	404	0	0	0
T130	754	0	0	0
T155	0	2	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T4,T11,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T4,T11,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T18
0	1	Covered	T4,T18,T29
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T18
1	-	Covered	T4,T18,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T18
DetectSt	168	Covered	T4,T11,T18
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T4,T11,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T18
DebounceSt->IdleSt	163	Covered	T56,T169
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T11,T18
IdleSt->DebounceSt	148	Covered	T4,T11,T18
StableSt->IdleSt	206	Covered	T4,T18,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T18
0	1	Covered	T4,T11,T18
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T169
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T18,T29
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	104	0	0
CntIncr_A	7822273	35755	0	0
CntNoWrap_A	7822273	7181439	0	0
DetectStDropOut_A	7822273	0	0	0
DetectedOut_A	7822273	11028	0	0
DetectedPulseOut_A	7822273	51	0	0
DisabledIdleSt_A	7822273	6752652	0	0
DisabledNoDetection_A	7822273	6754839	0	0
EnterDebounceSt_A	7822273	53	0	0
EnterDetectSt_A	7822273	51	0	0
EnterStableSt_A	7822273	51	0	0
PulseIsPulse_A	7822273	51	0	0
StayInStableSt	7822273	10948	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6282	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	104	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	2	0	0
T18	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	4	0	0
T32	0	2	0	0
T56	0	1	0	0
T91	0	12	0	0
T155	0	4	0	0
T156	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	35755	0	0
T4	270392	100	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	68	0	0
T18	0	26	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	130	0	0
T32	0	76	0	0
T56	0	18	0	0
T91	0	308	0	0
T155	0	192	0	0
T156	0	67	0	0
T173	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181439	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261825	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	11028	0	0
T4	270392	203	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	150	0	0
T18	0	93	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	83	0	0
T32	0	43	0	0
T91	0	580	0	0
T155	0	222	0	0
T156	0	44	0	0
T158	0	39	0	0
T173	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	51	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	1	0	0
T18	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T91	0	6	0	0
T155	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6752652	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261267	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6754839	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261296	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	53	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	1	0	0
T18	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T56	0	1	0	0
T91	0	6	0	0
T155	0	2	0	0
T156	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	51	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	1	0	0
T18	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T91	0	6	0	0
T155	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	51	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	1	0	0
T18	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T91	0	6	0	0
T155	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	51	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	1	0	0
T18	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	2	0	0
T32	0	1	0	0
T91	0	6	0	0
T155	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	10948	0	0
T4	270392	202	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T11	0	148	0	0
T18	0	90	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	80	0	0
T32	0	41	0	0
T91	0	571	0	0
T155	0	219	0	0
T156	0	42	0	0
T158	0	37	0	0
T173	0	50	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6282	0	0
T1	25224	32	0	0
T2	579	0	0	0
T3	9127	11	0	0
T4	270392	46	0	0
T5	20621	10	0	0
T6	0	11	0	0
T7	0	37	0	0
T22	4419	0	0	0
T23	425	1	0	0
T24	18732	36	0	0
T25	845	0	0	0
T26	5266	24	0	0
T28	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	21	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T18	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T29	0	1	0	0
T91	0	3	0	0
T121	0	1	0	0
T155	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T214	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T2,T4,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T4,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T10
0	1	Covered	T91,T167,T221
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T10
0	1	Covered	T4,T15,T84
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T10
1	-	Covered	T4,T15,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T10
DetectSt	168	Covered	T2,T4,T10
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T2,T4,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T10
DebounceSt->IdleSt	163	Covered	T56,T32,T157
DetectSt->IdleSt	186	Covered	T91,T167,T221
DetectSt->StableSt	191	Covered	T2,T4,T10
IdleSt->DebounceSt	148	Covered	T2,T4,T10
StableSt->IdleSt	206	Covered	T4,T15,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T10
0	1	Covered	T2,T4,T10
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T157,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T10
DetectSt	-	-	-	-	1	-	-	Covered	T91,T167,T221
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T15,T84
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	142	0	0
CntIncr_A	7822273	272743	0	0
CntNoWrap_A	7822273	7181401	0	0
DetectStDropOut_A	7822273	5	0	0
DetectedOut_A	7822273	135847	0	0
DetectedPulseOut_A	7822273	64	0	0
DisabledIdleSt_A	7822273	6538864	0	0
DisabledNoDetection_A	7822273	6541056	0	0
EnterDebounceSt_A	7822273	73	0	0
EnterDetectSt_A	7822273	69	0	0
EnterStableSt_A	7822273	64	0	0
PulseIsPulse_A	7822273	64	0	0
StayInStableSt	7822273	135754	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	142	0	0
T2	579	2	0	0
T3	9127	0	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T10	0	2	0	0
T15	0	4	0	0
T20	0	2	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	2	0	0
T43	0	2	0	0
T50	0	2	0	0
T56	0	1	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	272743	0	0
T2	579	85	0	0
T3	9127	0	0	0
T4	270392	100	0	0
T5	20621	0	0	0
T10	0	26	0	0
T15	0	109440	0	0
T20	0	49	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	50	0	0
T43	0	36	0	0
T50	0	75	0	0
T56	0	20	0	0
T84	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181401	0	0
T1	25224	24762	0	0
T2	579	176	0	0
T3	9127	8705	0	0
T4	270392	261825	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	5	0	0
T91	12100	1	0	0
T146	0	1	0	0
T167	0	2	0	0
T199	409	0	0	0
T200	402	0	0	0
T201	16895	0	0	0
T202	455	0	0	0
T203	420	0	0	0
T221	0	1	0	0
T233	2064	0	0	0
T234	530	0	0	0
T235	509	0	0	0
T236	14809	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	135847	0	0
T2	579	84	0	0
T3	9127	0	0	0
T4	270392	59	0	0
T5	20621	0	0	0
T10	0	200	0	0
T15	0	56193	0	0
T20	0	84	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	73	0	0
T32	0	60367	0	0
T43	0	6	0	0
T50	0	65	0	0
T84	0	114	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	64	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T10	0	1	0	0
T15	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0
T84	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6538864	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261267	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6541056	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261296	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	73	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T10	0	1	0	0
T15	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T56	0	1	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	69	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T10	0	1	0	0
T15	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0
T84	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	64	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T10	0	1	0	0
T15	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0
T84	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	64	0	0
T2	579	1	0	0
T3	9127	0	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T10	0	1	0	0
T15	0	2	0	0
T20	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0
T84	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	135754	0	0
T2	579	82	0	0
T3	9127	0	0	0
T4	270392	58	0	0
T5	20621	0	0	0
T10	0	198	0	0
T15	0	56190	0	0
T20	0	82	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T29	0	71	0	0
T32	0	60365	0	0
T43	0	5	0	0
T50	0	63	0	0
T84	0	111	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	34	0	0
T4	270392	1	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T15	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T32	0	2	0	0
T43	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T90	0	2	0	0
T155	0	1	0	0
T156	0	2	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T15,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T15
1	0	Covered	T1,T3,T4
1	1	Covered	T15,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T84,T91
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T17
1	-	Covered	T15,T84,T91

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T16,T17
DetectSt	168	Covered	T15,T16,T17
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T15,T16,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T16,T17
DebounceSt->IdleSt	163	Covered	T56
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T15,T16,T17
IdleSt->DebounceSt	148	Covered	T15,T16,T17
StableSt->IdleSt	206	Covered	T15,T84,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T17
0	1	Covered	T15,T16,T17
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T17
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T84,T91
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	85	0	0
CntIncr_A	7822273	119299	0	0
CntNoWrap_A	7822273	7181458	0	0
DetectStDropOut_A	7822273	1	0	0
DetectedOut_A	7822273	8917	0	0
DetectedPulseOut_A	7822273	41	0	0
DisabledIdleSt_A	7822273	6830104	0	0
DisabledNoDetection_A	7822273	6832299	0	0
EnterDebounceSt_A	7822273	43	0	0
EnterDetectSt_A	7822273	42	0	0
EnterStableSt_A	7822273	41	0	0
PulseIsPulse_A	7822273	41	0	0
StayInStableSt	7822273	8855	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6260	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	85	0	0
T15	227320	2	0	0
T16	0	2	0	0
T17	0	2	0	0
T41	635	0	0	0
T43	0	2	0	0
T56	0	1	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T84	0	2	0	0
T85	0	4	0	0
T91	0	6	0	0
T124	25350	0	0	0
T156	0	4	0	0
T157	0	2	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	119299	0	0
T15	227320	54720	0	0
T16	0	40	0	0
T17	0	11	0	0
T41	635	0	0	0
T43	0	36	0	0
T56	0	19	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T84	0	13	0	0
T85	0	106	0	0
T91	0	169	0	0
T124	25350	0	0	0
T156	0	134	0	0
T157	0	59541	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181458	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1	0	0
T85	906	1	0	0
T158	718	0	0	0
T159	406	0	0	0
T160	11228	0	0	0
T161	63252	0	0	0
T162	418	0	0	0
T163	932	0	0	0
T164	402	0	0	0
T165	776	0	0	0
T166	11013	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	8917	0	0
T15	227320	6556	0	0
T16	0	95	0	0
T17	0	41	0	0
T41	635	0	0	0
T43	0	180	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T80	0	20	0	0
T84	0	53	0	0
T85	0	39	0	0
T91	0	141	0	0
T124	25350	0	0	0
T156	0	85	0	0
T157	0	45	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T15	227320	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T41	635	0	0	0
T43	0	1	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T91	0	3	0	0
T124	25350	0	0	0
T156	0	2	0	0
T157	0	1	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6830104	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6832299	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	43	0	0
T15	227320	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T41	635	0	0	0
T43	0	1	0	0
T56	0	1	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T84	0	1	0	0
T85	0	2	0	0
T91	0	3	0	0
T124	25350	0	0	0
T156	0	2	0	0
T157	0	1	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	42	0	0
T15	227320	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T41	635	0	0	0
T43	0	1	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T91	0	3	0	0
T124	25350	0	0	0
T156	0	2	0	0
T157	0	1	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T15	227320	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T41	635	0	0	0
T43	0	1	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T91	0	3	0	0
T124	25350	0	0	0
T156	0	2	0	0
T157	0	1	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41	0	0
T15	227320	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T41	635	0	0	0
T43	0	1	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T91	0	3	0	0
T124	25350	0	0	0
T156	0	2	0	0
T157	0	1	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	8855	0	0
T15	227320	6555	0	0
T16	0	93	0	0
T17	0	39	0	0
T41	635	0	0	0
T43	0	178	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T80	0	19	0	0
T84	0	52	0	0
T85	0	38	0	0
T91	0	137	0	0
T124	25350	0	0	0
T156	0	82	0	0
T157	0	43	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6260	0	0
T1	25224	34	0	0
T2	579	0	0	0
T3	9127	7	0	0
T4	270392	57	0	0
T5	20621	11	0	0
T6	0	9	0	0
T7	0	35	0	0
T22	4419	0	0	0
T23	425	2	0	0
T24	18732	28	0	0
T25	845	0	0	0
T26	5266	25	0	0
T28	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	19	0	0
T15	227320	1	0	0
T41	635	0	0	0
T60	505	0	0	0
T65	502	0	0	0
T71	4820	0	0	0
T72	7716	0	0	0
T81	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T91	0	2	0	0
T124	25350	0	0	0
T156	0	1	0	0
T167	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T214	0	1	0	0
T237	412	0	0	0
T238	448	0	0	0
T239	428	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T17,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T132,T214,T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T18,T19,T84
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T18,T19
1	-	Covered	T18,T19,T84

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T18,T19
DetectSt	168	Covered	T17,T18,T19
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T17,T18,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T18,T19
DebounceSt->IdleSt	163	Covered	T56,T32,T90
DetectSt->IdleSt	186	Covered	T132,T214,T169
DetectSt->StableSt	191	Covered	T17,T18,T19
IdleSt->DebounceSt	148	Covered	T17,T18,T19
StableSt->IdleSt	206	Covered	T18,T19,T84

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T18,T19
0	1	Covered	T17,T18,T19
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T90,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T132,T214,T169
DetectSt	-	-	-	-	0	1	-	Covered	T17,T18,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T19,T84
StableSt	-	-	-	-	-	-	0	Covered	T17,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	136	0	0
CntIncr_A	7822273	212795	0	0
CntNoWrap_A	7822273	7181407	0	0
DetectStDropOut_A	7822273	3	0	0
DetectedOut_A	7822273	99242	0	0
DetectedPulseOut_A	7822273	63	0	0
DisabledIdleSt_A	7822273	6766481	0	0
DisabledNoDetection_A	7822273	6768677	0	0
EnterDebounceSt_A	7822273	70	0	0
EnterDetectSt_A	7822273	66	0	0
EnterStableSt_A	7822273	63	0	0
PulseIsPulse_A	7822273	63	0	0
StayInStableSt	7822273	99157	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	136	0	0
T17	473	2	0	0
T18	620	4	0	0
T19	473	2	0	0
T20	0	2	0	0
T32	0	3	0	0
T56	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	4	0	0
T90	0	1	0	0
T91	0	8	0	0
T100	4424	0	0	0
T155	0	2	0	0
T193	421	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	212795	0	0
T17	473	11	0	0
T18	620	26	0	0
T19	473	11	0	0
T20	0	49	0	0
T32	0	99986	0	0
T56	0	19	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	26	0	0
T90	0	76	0	0
T91	0	179	0	0
T100	4424	0	0	0
T155	0	96	0	0
T193	421	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181407	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	3	0	0
T85	906	0	0	0
T132	14481	1	0	0
T158	718	0	0	0
T159	406	0	0	0
T160	11228	0	0	0
T161	63252	0	0	0
T162	418	0	0	0
T163	932	0	0	0
T164	402	0	0	0
T169	0	1	0	0
T173	562	0	0	0
T214	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	99242	0	0
T17	473	40	0	0
T18	620	130	0	0
T19	473	2	0	0
T20	0	42	0	0
T32	0	10292	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	113	0	0
T85	0	151	0	0
T91	0	298	0	0
T100	4424	0	0	0
T155	0	42	0	0
T157	0	22002	0	0
T193	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	63	0	0
T17	473	1	0	0
T18	620	2	0	0
T19	473	1	0	0
T20	0	1	0	0
T32	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	2	0	0
T85	0	1	0	0
T91	0	4	0	0
T100	4424	0	0	0
T155	0	1	0	0
T157	0	1	0	0
T193	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6766481	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6768677	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	70	0	0
T17	473	1	0	0
T18	620	2	0	0
T19	473	1	0	0
T20	0	1	0	0
T32	0	2	0	0
T56	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	2	0	0
T90	0	1	0	0
T91	0	4	0	0
T100	4424	0	0	0
T155	0	1	0	0
T193	421	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	66	0	0
T17	473	1	0	0
T18	620	2	0	0
T19	473	1	0	0
T20	0	1	0	0
T32	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	2	0	0
T85	0	1	0	0
T91	0	4	0	0
T100	4424	0	0	0
T132	0	1	0	0
T155	0	1	0	0
T193	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	63	0	0
T17	473	1	0	0
T18	620	2	0	0
T19	473	1	0	0
T20	0	1	0	0
T32	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	2	0	0
T85	0	1	0	0
T91	0	4	0	0
T100	4424	0	0	0
T155	0	1	0	0
T157	0	1	0	0
T193	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	63	0	0
T17	473	1	0	0
T18	620	2	0	0
T19	473	1	0	0
T20	0	1	0	0
T32	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	2	0	0
T85	0	1	0	0
T91	0	4	0	0
T100	4424	0	0	0
T155	0	1	0	0
T157	0	1	0	0
T193	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	99157	0	0
T17	473	38	0	0
T18	620	127	0	0
T19	473	1	0	0
T20	0	40	0	0
T32	0	10291	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	110	0	0
T85	0	150	0	0
T91	0	292	0	0
T100	4424	0	0	0
T155	0	41	0	0
T157	0	22000	0	0
T193	421	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40	0	0
T18	620	1	0	0
T19	473	1	0	0
T32	0	1	0	0
T58	17530	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T91	0	2	0	0
T100	4424	0	0	0
T105	0	1	0	0
T121	0	1	0	0
T155	0	1	0	0
T193	421	0	0	0
T214	0	1	0	0
T240	422	0	0	0
T241	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T16,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T16
1	0	Covered	T1,T3,T4
1	1	Covered	T16,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T18,T29,T32
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T19
1	-	Covered	T18,T29,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T18,T19
DetectSt	168	Covered	T16,T18,T19
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T16,T18,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T18,T19
DebounceSt->IdleSt	163	Covered	T56,T242
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T18,T19
IdleSt->DebounceSt	148	Covered	T16,T18,T19
StableSt->IdleSt	206	Covered	T18,T29,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T242
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T29,T32
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	76	0	0
CntIncr_A	7822273	101879	0	0
CntNoWrap_A	7822273	7181467	0	0
DetectStDropOut_A	7822273	0	0	0
DetectedOut_A	7822273	4734	0	0
DetectedPulseOut_A	7822273	37	0	0
DisabledIdleSt_A	7822273	6767775	0	0
DisabledNoDetection_A	7822273	6769970	0	0
EnterDebounceSt_A	7822273	39	0	0
EnterDetectSt_A	7822273	37	0	0
EnterStableSt_A	7822273	37	0	0
PulseIsPulse_A	7822273	37	0	0
StayInStableSt	7822273	4672	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7822273	6901	0	0
gen_low_level_sva.LowLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	76	0	0
T16	701	2	0	0
T17	473	0	0	0
T18	620	2	0	0
T19	473	2	0	0
T29	0	2	0	0
T32	0	8	0	0
T43	0	2	0	0
T46	690	0	0	0
T56	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	2	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	4	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	101879	0	0
T16	701	40	0	0
T17	473	0	0	0
T18	620	13	0	0
T19	473	11	0	0
T29	0	65	0	0
T32	0	100138	0	0
T43	0	36	0	0
T46	690	0	0	0
T56	0	20	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	72	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	96	0	0
T155	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7181467	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	4734	0	0
T16	701	53	0	0
T17	473	0	0	0
T18	620	40	0	0
T19	473	39	0	0
T29	0	44	0	0
T32	0	2410	0	0
T43	0	44	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	63	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	257	0	0
T155	0	163	0	0
T173	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	37	0	0
T16	701	1	0	0
T17	473	0	0	0
T18	620	1	0	0
T19	473	1	0	0
T29	0	1	0	0
T32	0	4	0	0
T43	0	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	2	0	0
T155	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6767775	0	0
T1	25224	24762	0	0
T2	579	4	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6769970	0	0
T1	25224	24771	0	0
T2	579	4	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	39	0	0
T16	701	1	0	0
T17	473	0	0	0
T18	620	1	0	0
T19	473	1	0	0
T29	0	1	0	0
T32	0	4	0	0
T43	0	1	0	0
T46	690	0	0	0
T56	0	1	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	2	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	37	0	0
T16	701	1	0	0
T17	473	0	0	0
T18	620	1	0	0
T19	473	1	0	0
T29	0	1	0	0
T32	0	4	0	0
T43	0	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	2	0	0
T155	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	37	0	0
T16	701	1	0	0
T17	473	0	0	0
T18	620	1	0	0
T19	473	1	0	0
T29	0	1	0	0
T32	0	4	0	0
T43	0	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	2	0	0
T155	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	37	0	0
T16	701	1	0	0
T17	473	0	0	0
T18	620	1	0	0
T19	473	1	0	0
T29	0	1	0	0
T32	0	4	0	0
T43	0	1	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	1	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	2	0	0
T155	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	4672	0	0
T16	701	51	0	0
T17	473	0	0	0
T18	620	39	0	0
T19	473	37	0	0
T29	0	43	0	0
T32	0	2404	0	0
T43	0	42	0	0
T46	690	0	0	0
T58	17530	0	0	0
T67	522	0	0	0
T68	502	0	0	0
T91	0	61	0	0
T99	422	0	0	0
T100	4424	0	0	0
T132	0	253	0	0
T155	0	161	0	0
T173	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6901	0	0
T1	25224	29	0	0
T2	579	0	0	0
T3	9127	10	0	0
T4	270392	72	0	0
T5	20621	10	0	0
T6	0	13	0	0
T7	0	17	0	0
T22	4419	0	0	0
T23	425	1	0	0
T24	18732	30	0	0
T25	845	5	0	0
T26	5266	23	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	11	0	0
T18	620	1	0	0
T19	473	0	0	0
T29	0	1	0	0
T32	0	2	0	0
T58	17530	0	0	0
T68	502	0	0	0
T69	506	0	0	0
T77	7850	0	0	0
T100	4424	0	0	0
T138	0	1	0	0
T170	0	1	0	0
T193	421	0	0	0
T229	0	1	0	0
T240	422	0	0	0
T241	407	0	0	0
T243	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0