Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T26
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T26
1	0	Covered	T1,T24,T7
1	1	Covered	T1,T24,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T26
0	1	Covered	T26,T71,T72
1	0	Covered	T72,T101,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T28
0	1	Covered	T1,T24,T7
1	0	Covered	T247

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T24,T28
1	-	Covered	T1,T24,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T24,T26
DetectSt	168	Covered	T1,T24,T26
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T24,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T24,T26
DebounceSt->IdleSt	163	Covered	T56,T248,T80
DetectSt->IdleSt	186	Covered	T26,T71,T72
DetectSt->StableSt	191	Covered	T1,T24,T28
IdleSt->DebounceSt	148	Covered	T1,T24,T26
StableSt->IdleSt	206	Covered	T1,T24,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T24,T26
0	1	Covered	T1,T24,T26
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T24,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T24,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T24,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T248,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T24,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T1,T24,T28
DetectSt	-	-	-	-	0	0	-	Covered	T1,T24,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T24,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T24,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	2801	0	0
CntIncr_A	7822273	90429	0	0
CntNoWrap_A	7822273	7178742	0	0
DetectStDropOut_A	7822273	434	0	0
DetectedOut_A	7822273	64179	0	0
DetectedPulseOut_A	7822273	806	0	0
DisabledIdleSt_A	7822273	6743897	0	0
DisabledNoDetection_A	7822273	6745937	0	0
EnterDebounceSt_A	7822273	1420	0	0
EnterDetectSt_A	7822273	1381	0	0
EnterStableSt_A	7822273	806	0	0
PulseIsPulse_A	7822273	806	0	0
StayInStableSt	7822273	63260	0	0
gen_high_event_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	692	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2801	0	0
T1	25224	26	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	20	0	0
T8	0	54	0	0
T13	0	18	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	14	0	0
T25	845	0	0	0
T26	5266	50	0	0
T28	0	2	0	0
T71	0	48	0	0
T72	0	38	0	0
T73	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	90429	0	0
T1	25224	819	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	470	0	0
T8	0	2349	0	0
T13	0	567	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	294	0	0
T25	845	0	0	0
T26	5266	1325	0	0
T28	0	21	0	0
T71	0	1060	0	0
T72	0	1316	0	0
T73	0	585	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7178742	0	0
T1	25224	24736	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18276	0	0
T25	845	444	0	0
T26	5266	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	434	0	0
T6	20867	0	0	0
T7	21158	0	0	0
T8	22721	0	0	0
T9	2607	0	0	0
T26	5266	25	0	0
T27	432	0	0	0
T28	469	0	0	0
T35	498	0	0	0
T56	0	1	0	0
T71	0	24	0	0
T72	0	13	0	0
T101	0	8	0	0
T102	0	7	0	0
T103	0	28	0	0
T125	858	0	0	0
T141	0	13	0	0
T249	0	24	0	0
T250	0	1	0	0
T251	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	64179	0	0
T1	25224	342	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	945	0	0
T8	0	1726	0	0
T13	0	495	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	401	0	0
T25	845	0	0	0
T26	5266	0	0	0
T28	0	44	0	0
T73	0	849	0	0
T74	0	803	0	0
T252	0	5069	0	0
T253	0	1012	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	806	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	27	0	0
T13	0	9	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T28	0	1	0	0
T73	0	9	0	0
T74	0	22	0	0
T252	0	23	0	0
T253	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6743897	0	0
T1	25224	20542	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	13996	0	0
T25	845	444	0	0
T26	5266	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6745937	0	0
T1	25224	20550	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	14001	0	0
T25	845	445	0	0
T26	5266	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1420	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	27	0	0
T13	0	9	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	25	0	0
T28	0	1	0	0
T71	0	24	0	0
T72	0	19	0	0
T73	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1381	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	27	0	0
T13	0	9	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	25	0	0
T28	0	1	0	0
T71	0	24	0	0
T72	0	19	0	0
T73	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	806	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	27	0	0
T13	0	9	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T28	0	1	0	0
T73	0	9	0	0
T74	0	22	0	0
T252	0	23	0	0
T253	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	806	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	27	0	0
T13	0	9	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T28	0	1	0	0
T73	0	9	0	0
T74	0	22	0	0
T252	0	23	0	0
T253	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	63260	0	0
T1	25224	329	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	931	0	0
T8	0	1696	0	0
T13	0	485	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	394	0	0
T25	845	0	0	0
T26	5266	0	0	0
T28	0	42	0	0
T73	0	838	0	0
T74	0	779	0	0
T252	0	5041	0	0
T253	0	1001	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	692	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	6	0	0
T8	0	24	0	0
T13	0	8	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	7	0	0
T74	0	20	0	0
T252	0	18	0	0
T253	0	11	0	0
T254	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T3,T4,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T4,T82,T83
1	0	Covered	T56,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
1	0	Covered	T8,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T6
1	-	Covered	T3,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T5
DetectSt	168	Covered	T3,T4,T5
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T3,T5,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T5
DebounceSt->IdleSt	163	Covered	T5,T28,T10
DetectSt->IdleSt	186	Covered	T4,T82,T83
DetectSt->StableSt	191	Covered	T3,T5,T6
IdleSt->DebounceSt	148	Covered	T3,T4,T5
StableSt->IdleSt	206	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T28,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T5
DetectSt	-	-	-	-	1	-	-	Covered	T4,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T6
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T5
StableSt	-	-	-	-	-	-	1	Covered	T3,T5,T6
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	801	0	0
CntIncr_A	7822273	40249	0	0
CntNoWrap_A	7822273	7180742	0	0
DetectStDropOut_A	7822273	57	0	0
DetectedOut_A	7822273	12380	0	0
DetectedPulseOut_A	7822273	299	0	0
DisabledIdleSt_A	7822273	6827946	0	0
DisabledNoDetection_A	7822273	6829535	0	0
EnterDebounceSt_A	7822273	444	0	0
EnterDetectSt_A	7822273	360	0	0
EnterStableSt_A	7822273	299	0	0
PulseIsPulse_A	7822273	299	0	0
StayInStableSt	7822273	12055	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	269	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	801	0	0
T3	9127	4	0	0
T4	270392	6	0	0
T5	20621	5	0	0
T6	20867	6	0	0
T7	0	8	0	0
T8	0	6	0	0
T10	0	9	0	0
T12	0	6	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	0	1	0	0
T97	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	40249	0	0
T3	9127	154	0	0
T4	270392	177	0	0
T5	20621	229	0	0
T6	20867	336	0	0
T7	0	252	0	0
T8	0	237	0	0
T10	0	724	0	0
T12	0	435	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	0	20	0	0
T97	0	177	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7180742	0	0
T1	25224	24762	0	0
T2	579	178	0	0
T3	9127	8701	0	0
T4	270392	261821	0	0
T5	20621	20162	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	57	0	0
T4	270392	3	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	469	0	0	0
T82	0	4	0	0
T83	0	8	0	0
T104	0	8	0	0
T107	0	4	0	0
T108	0	6	0	0
T109	0	2	0	0
T110	0	1	0	0
T112	0	4	0	0
T113	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	12380	0	0
T3	9127	40	0	0
T4	270392	0	0	0
T5	20621	104	0	0
T6	20867	97	0	0
T7	0	179	0	0
T8	0	195	0	0
T10	0	341	0	0
T12	0	72	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T58	0	51	0	0
T97	0	166	0	0
T124	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	299	0	0
T3	9127	2	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	20867	3	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	4	0	0
T12	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T58	0	2	0	0
T97	0	3	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6827946	0	0
T1	25224	24420	0	0
T2	579	178	0	0
T3	9127	6043	0	0
T4	270392	259493	0	0
T5	20621	16116	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	17889	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6829535	0	0
T1	25224	24429	0	0
T2	579	179	0	0
T3	9127	6043	0	0
T4	270392	259514	0	0
T5	20621	16116	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	17895	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	444	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	3	0	0
T6	20867	3	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	5	0	0
T12	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T28	0	1	0	0
T97	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	360	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	2	0	0
T6	20867	3	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	4	0	0
T12	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	4	0	0
T97	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	299	0	0
T3	9127	2	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	20867	3	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	4	0	0
T12	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T58	0	2	0	0
T97	0	3	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	299	0	0
T3	9127	2	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	20867	3	0	0
T7	0	4	0	0
T8	0	3	0	0
T10	0	4	0	0
T12	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T58	0	2	0	0
T97	0	3	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	12055	0	0
T3	9127	38	0	0
T4	270392	0	0	0
T5	20621	102	0	0
T6	20867	94	0	0
T7	0	175	0	0
T8	0	192	0	0
T10	0	337	0	0
T12	0	69	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T58	0	49	0	0
T97	0	163	0	0
T124	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	269	0	0
T3	9127	2	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	20867	3	0	0
T7	0	4	0	0
T8	0	1	0	0
T10	0	4	0	0
T12	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T58	0	2	0	0
T97	0	3	0	0
T124	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T26
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T26
1	0	Covered	T1,T24,T7
1	1	Covered	T1,T24,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T26
0	1	Covered	T26,T71,T72
1	0	Covered	T72,T255,T256

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T7
0	1	Covered	T1,T24,T7
1	0	Covered	T56,T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T24,T7
1	-	Covered	T1,T24,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T24,T26
DetectSt	168	Covered	T1,T24,T26
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T24,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T24,T26
DebounceSt->IdleSt	163	Covered	T56,T248,T80
DetectSt->IdleSt	186	Covered	T26,T71,T72
DetectSt->StableSt	191	Covered	T1,T24,T7
IdleSt->DebounceSt	148	Covered	T1,T24,T26
StableSt->IdleSt	206	Covered	T1,T24,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T24,T26
0	1	Covered	T1,T24,T26
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T24,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T24,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T24,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T248,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T24,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T1,T24,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T24,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T24,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T24,T7
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	2765	0	0
CntIncr_A	7822273	85215	0	0
CntNoWrap_A	7822273	7178778	0	0
DetectStDropOut_A	7822273	397	0	0
DetectedOut_A	7822273	68842	0	0
DetectedPulseOut_A	7822273	837	0	0
DisabledIdleSt_A	7822273	6739570	0	0
DisabledNoDetection_A	7822273	6741602	0	0
EnterDebounceSt_A	7822273	1404	0	0
EnterDetectSt_A	7822273	1362	0	0
EnterStableSt_A	7822273	837	0	0
PulseIsPulse_A	7822273	837	0	0
StayInStableSt	7822273	67883	0	0
gen_high_event_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	713	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2765	0	0
T1	25224	26	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	26	0	0
T8	0	30	0	0
T13	0	6	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	60	0	0
T25	845	0	0	0
T26	5266	10	0	0
T71	0	12	0	0
T72	0	40	0	0
T73	0	64	0	0
T74	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	85215	0	0
T1	25224	715	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	559	0	0
T8	0	900	0	0
T13	0	246	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	1590	0	0
T25	845	0	0	0
T26	5266	260	0	0
T71	0	258	0	0
T72	0	1387	0	0
T73	0	2816	0	0
T74	0	638	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7178778	0	0
T1	25224	24736	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18230	0	0
T25	845	444	0	0
T26	5266	4855	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	397	0	0
T6	20867	0	0	0
T7	21158	0	0	0
T8	22721	0	0	0
T9	2607	0	0	0
T26	5266	5	0	0
T27	432	0	0	0
T28	469	0	0	0
T35	498	0	0	0
T56	0	1	0	0
T71	0	6	0	0
T72	0	16	0	0
T103	0	19	0	0
T125	858	0	0	0
T249	0	17	0	0
T251	407	0	0	0
T255	0	3	0	0
T256	0	3	0	0
T258	0	6	0	0
T259	0	21	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68842	0	0
T1	25224	446	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	1911	0	0
T8	0	1380	0	0
T13	0	64	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	2806	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	2997	0	0
T74	0	349	0	0
T252	0	909	0	0
T253	0	402	0	0
T254	0	663	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	837	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	13	0	0
T8	0	15	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	30	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	32	0	0
T74	0	11	0	0
T252	0	6	0	0
T253	0	6	0	0
T254	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6739570	0	0
T1	25224	20542	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	12091	0	0
T25	845	444	0	0
T26	5266	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6741602	0	0
T1	25224	20550	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	12091	0	0
T25	845	445	0	0
T26	5266	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1404	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	13	0	0
T8	0	15	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	30	0	0
T25	845	0	0	0
T26	5266	5	0	0
T71	0	6	0	0
T72	0	20	0	0
T73	0	32	0	0
T74	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1362	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	13	0	0
T8	0	15	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	30	0	0
T25	845	0	0	0
T26	5266	5	0	0
T71	0	6	0	0
T72	0	20	0	0
T73	0	32	0	0
T74	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	837	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	13	0	0
T8	0	15	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	30	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	32	0	0
T74	0	11	0	0
T252	0	6	0	0
T253	0	6	0	0
T254	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	837	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	13	0	0
T8	0	15	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	30	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	32	0	0
T74	0	11	0	0
T252	0	6	0	0
T253	0	6	0	0
T254	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	67883	0	0
T1	25224	433	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	1892	0	0
T8	0	1362	0	0
T13	0	61	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	2771	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	2953	0	0
T74	0	336	0	0
T252	0	902	0	0
T253	0	396	0	0
T254	0	656	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	713	0	0
T1	25224	13	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	7	0	0
T8	0	12	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	25	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	20	0	0
T74	0	9	0	0
T252	0	5	0	0
T253	0	6	0	0
T254	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T83,T160,T121
1	0	Covered	T56,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T4,T5
1	0	Covered	T56,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T5
1	-	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T3,T4,T5
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T5
DebounceSt->IdleSt	163	Covered	T1,T3,T4
DetectSt->IdleSt	186	Covered	T83,T56,T91
DetectSt->StableSt	191	Covered	T3,T4,T5
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T83,T56,T160
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T5
DetectSt	-	-	-	-	0	0	-	Covered	T3,T4,T5
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T5
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	890	0	0
CntIncr_A	7822273	49894	0	0
CntNoWrap_A	7822273	7180653	0	0
DetectStDropOut_A	7822273	75	0	0
DetectedOut_A	7822273	14922	0	0
DetectedPulseOut_A	7822273	341	0	0
DisabledIdleSt_A	7822273	6839051	0	0
DisabledNoDetection_A	7822273	6840697	0	0
EnterDebounceSt_A	7822273	472	0	0
EnterDetectSt_A	7822273	420	0	0
EnterStableSt_A	7822273	341	0	0
PulseIsPulse_A	7822273	341	0	0
StayInStableSt	7822273	14537	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	295	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	890	0	0
T1	25224	1	0	0
T2	579	0	0	0
T3	9127	5	0	0
T4	270392	13	0	0
T5	20621	14	0	0
T6	0	2	0	0
T7	0	10	0	0
T8	0	6	0	0
T12	0	8	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	10	0	0
T25	845	0	0	0
T26	5266	0	0	0
T97	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	49894	0	0
T1	25224	26	0	0
T2	579	0	0	0
T3	9127	212	0	0
T4	270392	321	0	0
T5	20621	878	0	0
T6	0	81	0	0
T7	0	330	0	0
T8	0	261	0	0
T12	0	612	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	350	0	0
T25	845	0	0	0
T26	5266	0	0	0
T97	0	117	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7180653	0	0
T1	25224	24761	0	0
T2	579	178	0	0
T3	9127	8700	0	0
T4	270392	261814	0	0
T5	20621	20153	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18280	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	75	0	0
T21	562	0	0	0
T44	576	0	0	0
T63	491	0	0	0
T83	15667	8	0	0
T87	29356	0	0	0
T103	5417	0	0	0
T104	0	7	0	0
T121	0	2	0	0
T148	0	1	0	0
T154	0	4	0	0
T160	0	3	0	0
T186	0	6	0	0
T223	0	6	0	0
T260	0	3	0	0
T261	0	10	0	0
T262	1016	0	0	0
T263	502	0	0	0
T264	8596	0	0	0
T265	160006	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	14922	0	0
T3	9127	19	0	0
T4	270392	66	0	0
T5	20621	67	0	0
T6	20867	63	0	0
T7	0	206	0	0
T8	0	171	0	0
T12	0	65	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	286	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	25	0	0
T97	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	341	0	0
T3	9127	2	0	0
T4	270392	6	0	0
T5	20621	6	0	0
T6	20867	1	0	0
T7	0	5	0	0
T8	0	3	0	0
T12	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	5	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	5	0	0
T97	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6839051	0	0
T1	25224	24316	0	0
T2	579	178	0	0
T3	9127	6043	0	0
T4	270392	259493	0	0
T5	20621	16116	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	15489	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6840697	0	0
T1	25224	24325	0	0
T2	579	179	0	0
T3	9127	6043	0	0
T4	270392	259514	0	0
T5	20621	16116	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	15490	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	472	0	0
T1	25224	1	0	0
T2	579	0	0	0
T3	9127	3	0	0
T4	270392	7	0	0
T5	20621	8	0	0
T6	0	1	0	0
T7	0	5	0	0
T8	0	3	0	0
T12	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	5	0	0
T25	845	0	0	0
T26	5266	0	0	0
T97	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	420	0	0
T3	9127	2	0	0
T4	270392	6	0	0
T5	20621	6	0	0
T6	20867	1	0	0
T7	0	5	0	0
T8	0	3	0	0
T12	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	5	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	5	0	0
T97	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	341	0	0
T3	9127	2	0	0
T4	270392	6	0	0
T5	20621	6	0	0
T6	20867	1	0	0
T7	0	5	0	0
T8	0	3	0	0
T12	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	5	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	5	0	0
T97	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	341	0	0
T3	9127	2	0	0
T4	270392	6	0	0
T5	20621	6	0	0
T6	20867	1	0	0
T7	0	5	0	0
T8	0	3	0	0
T12	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	5	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	5	0	0
T97	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	14537	0	0
T3	9127	17	0	0
T4	270392	60	0	0
T5	20621	61	0	0
T6	20867	62	0	0
T7	0	201	0	0
T8	0	168	0	0
T12	0	61	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	276	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	20	0	0
T97	0	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	295	0	0
T3	9127	2	0	0
T4	270392	6	0	0
T5	20621	6	0	0
T6	20867	1	0	0
T7	0	5	0	0
T8	0	3	0	0
T12	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T82	0	5	0	0
T97	0	1	0	0
T124	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T26
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T26
1	0	Covered	T1,T24,T7
1	1	Covered	T1,T24,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T26
0	1	Covered	T24,T26,T71
1	0	Covered	T24,T72,T253

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T87,T88,T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T8
1	-	Covered	T1,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T24,T26
DetectSt	168	Covered	T1,T24,T26
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T24,T26
DebounceSt->IdleSt	163	Covered	T56,T248,T80
DetectSt->IdleSt	186	Covered	T24,T26,T71
DetectSt->StableSt	191	Covered	T1,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T24,T26
StableSt->IdleSt	206	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T24,T26
0	1	Covered	T1,T24,T26
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T24,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T24,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T24,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T248,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T24,T26
DetectSt	-	-	-	-	1	-	-	Covered	T24,T26,T71
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T24,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	2984	0	0
CntIncr_A	7822273	99054	0	0
CntNoWrap_A	7822273	7178559	0	0
DetectStDropOut_A	7822273	435	0	0
DetectedOut_A	7822273	75984	0	0
DetectedPulseOut_A	7822273	856	0	0
DisabledIdleSt_A	7822273	6733558	0	0
DisabledNoDetection_A	7822273	6735613	0	0
EnterDebounceSt_A	7822273	1513	0	0
EnterDetectSt_A	7822273	1471	0	0
EnterStableSt_A	7822273	856	0	0
PulseIsPulse_A	7822273	856	0	0
StayInStableSt	7822273	75029	0	0
gen_high_event_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	720	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2984	0	0
T1	25224	56	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	20	0	0
T8	0	50	0	0
T13	0	46	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	50	0	0
T25	845	0	0	0
T26	5266	52	0	0
T71	0	66	0	0
T72	0	20	0	0
T73	0	24	0	0
T74	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	99054	0	0
T1	25224	1540	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	390	0	0
T8	0	1475	0	0
T13	0	1426	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	1964	0	0
T25	845	0	0	0
T26	5266	1375	0	0
T71	0	1456	0	0
T72	0	689	0	0
T73	0	1044	0	0
T74	0	1600	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7178559	0	0
T1	25224	24706	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18240	0	0
T25	845	444	0	0
T26	5266	4813	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	435	0	0
T6	20867	0	0	0
T7	21158	0	0	0
T8	22721	0	0	0
T24	18732	6	0	0
T25	845	0	0	0
T26	5266	26	0	0
T27	432	0	0	0
T28	469	0	0	0
T35	498	0	0	0
T56	0	1	0	0
T71	0	33	0	0
T72	0	7	0	0
T103	0	27	0	0
T141	0	7	0	0
T249	0	19	0	0
T251	407	0	0	0
T253	0	2	0	0
T259	0	30	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	75984	0	0
T1	25224	3169	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	1025	0	0
T8	0	3127	0	0
T13	0	2053	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	690	0	0
T74	0	1491	0	0
T101	0	2111	0	0
T252	0	5322	0	0
T254	0	1352	0	0
T255	0	1820	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	856	0	0
T1	25224	28	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	25	0	0
T13	0	23	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	12	0	0
T74	0	25	0	0
T101	0	25	0	0
T252	0	23	0	0
T254	0	14	0	0
T255	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6733558	0	0
T1	25224	18150	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	14154	0	0
T25	845	444	0	0
T26	5266	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6735613	0	0
T1	25224	18150	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	14159	0	0
T25	845	445	0	0
T26	5266	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1513	0	0
T1	25224	28	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	25	0	0
T13	0	23	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	25	0	0
T25	845	0	0	0
T26	5266	26	0	0
T71	0	33	0	0
T72	0	10	0	0
T73	0	12	0	0
T74	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1471	0	0
T1	25224	28	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	25	0	0
T13	0	23	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	25	0	0
T25	845	0	0	0
T26	5266	26	0	0
T71	0	33	0	0
T72	0	10	0	0
T73	0	12	0	0
T74	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	856	0	0
T1	25224	28	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	25	0	0
T13	0	23	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	12	0	0
T74	0	25	0	0
T101	0	25	0	0
T252	0	23	0	0
T254	0	14	0	0
T255	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	856	0	0
T1	25224	28	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	10	0	0
T8	0	25	0	0
T13	0	23	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	12	0	0
T74	0	25	0	0
T101	0	25	0	0
T252	0	23	0	0
T254	0	14	0	0
T255	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	75029	0	0
T1	25224	3133	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	1011	0	0
T8	0	3097	0	0
T13	0	2025	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	674	0	0
T74	0	1465	0	0
T101	0	2085	0	0
T252	0	5294	0	0
T254	0	1336	0	0
T255	0	1792	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	720	0	0
T1	25224	20	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	6	0	0
T8	0	20	0	0
T13	0	18	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T73	0	8	0	0
T74	0	24	0	0
T101	0	24	0	0
T252	0	18	0	0
T254	0	12	0	0
T255	0	28	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T180,T160,T167
1	0	Covered	T56,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T267,T268,T269

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T1,T3,T6
DetectSt->IdleSt	186	Covered	T56,T180,T91
DetectSt->StableSt	191	Covered	T1,T3,T4
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T56,T180,T160
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	743	0	0
CntIncr_A	7822273	42450	0	0
CntNoWrap_A	7822273	7180800	0	0
DetectStDropOut_A	7822273	49	0	0
DetectedOut_A	7822273	13766	0	0
DetectedPulseOut_A	7822273	300	0	0
DisabledIdleSt_A	7822273	6818827	0	0
DisabledNoDetection_A	7822273	6820498	0	0
EnterDebounceSt_A	7822273	391	0	0
EnterDetectSt_A	7822273	354	0	0
EnterStableSt_A	7822273	300	0	0
PulseIsPulse_A	7822273	300	0	0
StayInStableSt	7822273	13429	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	256	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	743	0	0
T1	25224	18	0	0
T2	579	0	0	0
T3	9127	5	0	0
T4	270392	6	0	0
T5	20621	20	0	0
T6	0	7	0	0
T7	0	8	0	0
T8	0	10	0	0
T10	0	7	0	0
T12	0	2	0	0
T13	0	6	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	42450	0	0
T1	25224	692	0	0
T2	579	0	0	0
T3	9127	204	0	0
T4	270392	150	0	0
T5	20621	1350	0	0
T6	0	343	0	0
T7	0	156	0	0
T8	0	435	0	0
T10	0	756	0	0
T12	0	133	0	0
T13	0	201	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7180800	0	0
T1	25224	24744	0	0
T2	579	178	0	0
T3	9127	8700	0	0
T4	270392	261821	0	0
T5	20621	20147	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	49	0	0
T90	986	0	0	0
T107	0	3	0	0
T109	0	1	0	0
T148	0	4	0	0
T155	1176	0	0	0
T160	0	1	0	0
T167	0	1	0	0
T180	16298	2	0	0
T196	704	0	0	0
T197	427	0	0	0
T198	38537	0	0	0
T261	0	2	0	0
T270	0	4	0	0
T271	0	4	0	0
T272	0	8	0	0
T273	404	0	0	0
T274	502	0	0	0
T275	426	0	0	0
T276	692	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	13766	0	0
T1	25224	422	0	0
T2	579	0	0	0
T3	9127	26	0	0
T4	270392	25	0	0
T5	20621	54	0	0
T6	0	138	0	0
T7	0	275	0	0
T8	0	283	0	0
T10	0	67	0	0
T12	0	36	0	0
T13	0	191	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	300	0	0
T1	25224	8	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	10	0	0
T6	0	3	0	0
T7	0	4	0	0
T8	0	5	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6818827	0	0
T1	25224	21601	0	0
T2	579	178	0	0
T3	9127	6043	0	0
T4	270392	259493	0	0
T5	20621	16116	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6820498	0	0
T1	25224	21602	0	0
T2	579	179	0	0
T3	9127	6043	0	0
T4	270392	259514	0	0
T5	20621	16116	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	391	0	0
T1	25224	10	0	0
T2	579	0	0	0
T3	9127	3	0	0
T4	270392	3	0	0
T5	20621	10	0	0
T6	0	4	0	0
T7	0	4	0	0
T8	0	5	0	0
T10	0	4	0	0
T12	0	1	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	354	0	0
T1	25224	8	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	10	0	0
T6	0	3	0	0
T7	0	4	0	0
T8	0	5	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	300	0	0
T1	25224	8	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	10	0	0
T6	0	3	0	0
T7	0	4	0	0
T8	0	5	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	300	0	0
T1	25224	8	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	10	0	0
T6	0	3	0	0
T7	0	4	0	0
T8	0	5	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	0	3	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	13429	0	0
T1	25224	414	0	0
T2	579	0	0	0
T3	9127	24	0	0
T4	270392	22	0	0
T5	20621	44	0	0
T6	0	135	0	0
T7	0	271	0	0
T8	0	278	0	0
T10	0	64	0	0
T12	0	35	0	0
T13	0	185	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	256	0	0
T1	25224	8	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	10	0	0
T6	0	3	0	0
T7	0	4	0	0
T8	0	5	0	0
T10	0	3	0	0
T12	0	1	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T97	0	11	0	0