Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T26
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T26
1	0	Covered	T1,T24,T7
1	1	Covered	T1,T24,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T26
0	1	Covered	T26,T7,T71
1	0	Covered	T7,T264,T258

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T24,T8
0	1	Covered	T1,T24,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T24,T8
1	-	Covered	T1,T24,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T24,T26
DetectSt	168	Covered	T1,T24,T26
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T24,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T24,T26
DebounceSt->IdleSt	163	Covered	T56,T248,T80
DetectSt->IdleSt	186	Covered	T26,T7,T71
DetectSt->StableSt	191	Covered	T1,T24,T8
IdleSt->DebounceSt	148	Covered	T1,T24,T26
StableSt->IdleSt	206	Covered	T1,T24,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T24,T26
0	1	Covered	T1,T24,T26
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T24,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T24,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T24,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T248,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T24,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T7,T71
DetectSt	-	-	-	-	0	1	-	Covered	T1,T24,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T24,T26
StableSt	-	-	-	-	-	-	1	Covered	T1,T24,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T24,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	2999	0	0
CntIncr_A	7822273	103995	0	0
CntNoWrap_A	7822273	7178544	0	0
DetectStDropOut_A	7822273	493	0	0
DetectedOut_A	7822273	68243	0	0
DetectedPulseOut_A	7822273	780	0	0
DisabledIdleSt_A	7822273	6739936	0	0
DisabledNoDetection_A	7822273	6741997	0	0
EnterDebounceSt_A	7822273	1521	0	0
EnterDetectSt_A	7822273	1479	0	0
EnterStableSt_A	7822273	780	0	0
PulseIsPulse_A	7822273	780	0	0
StayInStableSt	7822273	67371	0	0
gen_high_event_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	687	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	2999	0	0
T1	25224	18	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	30	0	0
T8	0	26	0	0
T13	0	52	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	14	0	0
T25	845	0	0	0
T26	5266	50	0	0
T71	0	28	0	0
T72	0	38	0	0
T73	0	44	0	0
T74	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	103995	0	0
T1	25224	396	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	717	0	0
T8	0	1118	0	0
T13	0	1482	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	518	0	0
T25	845	0	0	0
T26	5266	1322	0	0
T71	0	606	0	0
T72	0	1197	0	0
T73	0	1870	0	0
T74	0	390	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7178544	0	0
T1	25224	24744	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18276	0	0
T25	845	444	0	0
T26	5266	4815	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	493	0	0
T6	20867	0	0	0
T7	21158	8	0	0
T8	22721	0	0	0
T9	2607	0	0	0
T26	5266	25	0	0
T27	432	0	0	0
T28	469	0	0	0
T35	498	0	0	0
T56	0	1	0	0
T71	0	14	0	0
T103	0	7	0	0
T125	858	0	0	0
T141	0	18	0	0
T249	0	9	0	0
T251	407	0	0	0
T258	0	3	0	0
T259	0	24	0	0
T264	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	68243	0	0
T1	25224	1141	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T8	0	1085	0	0
T13	0	2728	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	177	0	0
T25	845	0	0	0
T26	5266	0	0	0
T72	0	1752	0	0
T73	0	1527	0	0
T74	0	403	0	0
T252	0	5506	0	0
T253	0	2629	0	0
T254	0	3310	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	780	0	0
T1	25224	9	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T8	0	13	0	0
T13	0	26	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T72	0	19	0	0
T73	0	22	0	0
T74	0	10	0	0
T252	0	23	0	0
T253	0	10	0	0
T254	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6739936	0	0
T1	25224	19870	0	0
T2	579	178	0	0
T3	9127	8705	0	0
T4	270392	261827	0	0
T5	20621	20167	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	14007	0	0
T25	845	444	0	0
T26	5266	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6741997	0	0
T1	25224	19875	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	14012	0	0
T25	845	445	0	0
T26	5266	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1521	0	0
T1	25224	9	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	15	0	0
T8	0	13	0	0
T13	0	26	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	25	0	0
T71	0	14	0	0
T72	0	19	0	0
T73	0	22	0	0
T74	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	1479	0	0
T1	25224	9	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T7	0	15	0	0
T8	0	13	0	0
T13	0	26	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	25	0	0
T71	0	14	0	0
T72	0	19	0	0
T73	0	22	0	0
T74	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	780	0	0
T1	25224	9	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T8	0	13	0	0
T13	0	26	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T72	0	19	0	0
T73	0	22	0	0
T74	0	10	0	0
T252	0	23	0	0
T253	0	10	0	0
T254	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	780	0	0
T1	25224	9	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T8	0	13	0	0
T13	0	26	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T72	0	19	0	0
T73	0	22	0	0
T74	0	10	0	0
T252	0	23	0	0
T253	0	10	0	0
T254	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	67371	0	0
T1	25224	1129	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T8	0	1069	0	0
T13	0	2698	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	170	0	0
T25	845	0	0	0
T26	5266	0	0	0
T72	0	1733	0	0
T73	0	1498	0	0
T74	0	392	0	0
T252	0	5478	0	0
T253	0	2614	0	0
T254	0	3283	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	687	0	0
T1	25224	6	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	0	0	0
T8	0	10	0	0
T13	0	22	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	7	0	0
T25	845	0	0	0
T26	5266	0	0	0
T72	0	19	0	0
T73	0	15	0	0
T74	0	9	0	0
T252	0	18	0	0
T253	0	5	0	0
T254	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T3	VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T83
1	0	Covered	T56,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T56,T277

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T6
1	-	Covered	T1,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T1,T2,T3
StableSt	191	Covered	T1,T5,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T4,T5,T97
DetectSt->IdleSt	186	Covered	T3,T4,T83
DetectSt->StableSt	191	Covered	T1,T5,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Excluded	T1,T2,T3	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T5,T97
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T3,T4,T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7822273	794	0	0
CntIncr_A	7822273	41778	0	0
CntNoWrap_A	7822273	7180749	0	0
DetectStDropOut_A	7822273	49	0	0
DetectedOut_A	7822273	14897	0	0
DetectedPulseOut_A	7822273	324	0	0
DisabledIdleSt_A	7822273	6831030	0	0
DisabledNoDetection_A	7822273	6832707	0	0
EnterDebounceSt_A	7822273	417	0	0
EnterDetectSt_A	7822273	378	0	0
EnterStableSt_A	7822273	324	0	0
PulseIsPulse_A	7822273	324	0	0
StayInStableSt	7822273	14531	0	0
gen_high_level_sva.HighLevelEvent_A	7822273	7183791	0	0
gen_not_sticky_sva.StableStDropOut_A	7822273	277	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	794	0	0
T1	25224	6	0	0
T2	579	0	0	0
T3	9127	4	0	0
T4	270392	6	0	0
T5	20621	5	0	0
T6	0	4	0	0
T8	0	2	0	0
T12	0	14	0	0
T13	0	8	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T82	0	6	0	0
T97	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	41778	0	0
T1	25224	135	0	0
T2	579	0	0	0
T3	9127	194	0	0
T4	270392	250	0	0
T5	20621	297	0	0
T6	0	270	0	0
T8	0	91	0	0
T12	0	1064	0	0
T13	0	184	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T82	0	339	0	0
T97	0	567	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7180749	0	0
T1	25224	24756	0	0
T2	579	178	0	0
T3	9127	8701	0	0
T4	270392	261821	0	0
T5	20621	20162	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18290	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	49	0	0
T3	9127	2	0	0
T4	270392	2	0	0
T5	20621	0	0	0
T6	20867	0	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T27	432	0	0	0
T31	0	1	0	0
T83	0	5	0	0
T139	0	1	0	0
T160	0	3	0	0
T168	0	6	0	0
T201	0	1	0	0
T261	0	2	0	0
T278	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	14897	0	0
T1	25224	265	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	36	0	0
T6	0	18	0	0
T8	0	52	0	0
T12	0	121	0	0
T13	0	342	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T58	0	80	0	0
T82	0	96	0	0
T97	0	139	0	0
T124	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	324	0	0
T1	25224	3	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	0	2	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T58	0	7	0	0
T82	0	3	0	0
T97	0	6	0	0
T124	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6831030	0	0
T1	25224	23624	0	0
T2	579	178	0	0
T3	9127	6043	0	0
T4	270392	259493	0	0
T5	20621	16116	0	0
T22	4419	10	0	0
T23	425	24	0	0
T24	18732	18112	0	0
T25	845	444	0	0
T26	5266	4865	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	6832707	0	0
T1	25224	23630	0	0
T2	579	179	0	0
T3	9127	6043	0	0
T4	270392	259514	0	0
T5	20621	16116	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18118	0	0
T25	845	445	0	0
T26	5266	4866	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	417	0	0
T1	25224	3	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	4	0	0
T5	20621	3	0	0
T6	0	2	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T82	0	3	0	0
T97	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	378	0	0
T1	25224	3	0	0
T2	579	0	0	0
T3	9127	2	0	0
T4	270392	3	0	0
T5	20621	2	0	0
T6	0	2	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T82	0	3	0	0
T97	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	324	0	0
T1	25224	3	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	0	2	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T58	0	7	0	0
T82	0	3	0	0
T97	0	6	0	0
T124	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	324	0	0
T1	25224	3	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	0	2	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T58	0	7	0	0
T82	0	3	0	0
T97	0	6	0	0
T124	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	14531	0	0
T1	25224	262	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	34	0	0
T6	0	16	0	0
T8	0	51	0	0
T12	0	114	0	0
T13	0	338	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T58	0	73	0	0
T82	0	93	0	0
T97	0	133	0	0
T124	0	10	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	7183791	0	0
T1	25224	24771	0	0
T2	579	179	0	0
T3	9127	8708	0	0
T4	270392	261857	0	0
T5	20621	20175	0	0
T22	4419	19	0	0
T23	425	25	0	0
T24	18732	18296	0	0
T25	845	445	0	0
T26	5266	4866	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7822273	277	0	0
T1	25224	3	0	0
T2	579	0	0	0
T3	9127	0	0	0
T4	270392	0	0	0
T5	20621	2	0	0
T6	0	2	0	0
T8	0	1	0	0
T12	0	7	0	0
T13	0	4	0	0
T22	4419	0	0	0
T23	425	0	0	0
T24	18732	0	0	0
T25	845	0	0	0
T26	5266	0	0	0
T58	0	7	0	0
T82	0	3	0	0
T97	0	6	0	0
T124	0	3	0	0