Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1257058637	11708	0	0
auto_block_debounce_ctl_rd_A	1257058637	1422	0	0
auto_block_out_ctl_rd_A	1257058637	2181	0	0
com_det_ctl_0_rd_A	1257058637	2873	0	0
com_det_ctl_1_rd_A	1257058637	2908	0	0
com_det_ctl_2_rd_A	1257058637	2843	0	0
com_det_ctl_3_rd_A	1257058637	2823	0	0
com_out_ctl_0_rd_A	1257058637	3380	0	0
com_out_ctl_1_rd_A	1257058637	3441	0	0
com_out_ctl_2_rd_A	1257058637	3336	0	0
com_out_ctl_3_rd_A	1257058637	3488	0	0
com_pre_det_ctl_0_rd_A	1257058637	1074	0	0
com_pre_det_ctl_1_rd_A	1257058637	1041	0	0
com_pre_det_ctl_2_rd_A	1257058637	1023	0	0
com_pre_det_ctl_3_rd_A	1257058637	994	0	0
com_pre_sel_ctl_0_rd_A	1257058637	3651	0	0
com_pre_sel_ctl_1_rd_A	1257058637	3471	0	0
com_pre_sel_ctl_2_rd_A	1257058637	3642	0	0
com_pre_sel_ctl_3_rd_A	1257058637	3438	0	0
com_sel_ctl_0_rd_A	1257058637	3443	0	0
com_sel_ctl_1_rd_A	1257058637	3570	0	0
com_sel_ctl_2_rd_A	1257058637	3740	0	0
com_sel_ctl_3_rd_A	1257058637	3687	0	0
ec_rst_ctl_rd_A	1257058637	1831	0	0
intr_enable_rd_A	1257058637	1546	0	0
key_intr_ctl_rd_A	1257058637	3833	0	0
key_intr_debounce_ctl_rd_A	1257058637	1026	0	0
key_invert_ctl_rd_A	1257058637	4331	0	0
pin_allowed_ctl_rd_A	1257058637	6336	0	0
pin_out_ctl_rd_A	1257058637	4573	0	0
pin_out_value_rd_A	1257058637	4838	0	0
regwen_rd_A	1257058637	1244	0	0
ulp_ac_debounce_ctl_rd_A	1257058637	1189	0	0
ulp_ctl_rd_A	1257058637	1021	0	0
ulp_lid_debounce_ctl_rd_A	1257058637	1121	0	0
ulp_pwrb_debounce_ctl_rd_A	1257058637	1153	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	11708	0	0
T4	122300	17	0	0
T5	247459	0	0	0
T6	219115	0	0	0
T22	397766	0	0	0
T23	50980	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	10	0	0
T31	0	5	0	0
T32	0	7	0	0
T39	0	20	0	0
T42	0	7	0	0
T43	0	5	0	0
T50	0	29	0	0
T91	0	4	0	0
T131	0	8	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1422	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	39	0	0
T32	0	25	0	0
T39	325776	26	0	0
T47	0	7	0	0
T48	0	6	0	0
T86	0	9	0	0
T91	0	10	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	38	0	0
T217	0	2	0	0
T220	0	15	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	2181	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	38	0	0
T32	0	25	0	0
T39	325776	32	0	0
T47	0	12	0	0
T86	0	2	0	0
T91	0	2	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	33	0	0
T217	0	8	0	0
T220	0	6	0	0
T297	0	13	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	2873	0	0
T5	247459	57	0	0
T6	219115	79	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	23	0	0
T32	0	11	0	0
T39	0	47	0	0
T73	0	112	0	0
T82	0	84	0	0
T139	0	52	0	0
T251	97849	0	0	0
T256	0	48	0	0
T264	0	42	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	2908	0	0
T5	247459	68	0	0
T6	219115	80	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	27	0	0
T32	0	12	0	0
T39	0	25	0	0
T73	0	90	0	0
T82	0	85	0	0
T139	0	38	0	0
T251	97849	0	0	0
T256	0	38	0	0
T264	0	30	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	2843	0	0
T5	247459	72	0	0
T6	219115	108	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	19	0	0
T32	0	12	0	0
T39	0	38	0	0
T73	0	82	0	0
T82	0	59	0	0
T139	0	35	0	0
T251	97849	0	0	0
T256	0	49	0	0
T264	0	16	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	2823	0	0
T5	247459	93	0	0
T6	219115	87	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	18	0	0
T32	0	10	0	0
T39	0	34	0	0
T73	0	99	0	0
T82	0	75	0	0
T139	0	54	0	0
T251	97849	0	0	0
T256	0	60	0	0
T264	0	22	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3380	0	0
T5	247459	68	0	0
T6	219115	48	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	16	0	0
T32	0	3	0	0
T39	0	35	0	0
T73	0	115	0	0
T82	0	61	0	0
T139	0	48	0	0
T251	97849	0	0	0
T256	0	65	0	0
T264	0	12	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3441	0	0
T5	247459	50	0	0
T6	219115	75	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	13	0	0
T32	0	12	0	0
T39	0	47	0	0
T73	0	82	0	0
T82	0	90	0	0
T139	0	46	0	0
T251	97849	0	0	0
T256	0	67	0	0
T264	0	17	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3336	0	0
T5	247459	60	0	0
T6	219115	57	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	24	0	0
T32	0	3	0	0
T39	0	19	0	0
T73	0	92	0	0
T82	0	54	0	0
T139	0	55	0	0
T251	97849	0	0	0
T256	0	67	0	0
T264	0	20	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3488	0	0
T5	247459	84	0	0
T6	219115	72	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	28	0	0
T32	0	17	0	0
T39	0	32	0	0
T73	0	107	0	0
T82	0	48	0	0
T139	0	32	0	0
T251	97849	0	0	0
T256	0	55	0	0
T264	0	26	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1074	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	14	0	0
T32	0	3	0	0
T39	325776	43	0	0
T81	0	6	0	0
T91	0	12	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	13	0	0
T146	0	10	0	0
T167	0	41	0	0
T174	0	34	0	0
T297	0	20	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1041	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	29	0	0
T32	0	9	0	0
T39	325776	34	0	0
T81	0	3	0	0
T91	0	6	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	7	0	0
T146	0	9	0	0
T167	0	9	0	0
T174	0	20	0	0
T297	0	22	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1023	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	22	0	0
T32	0	2	0	0
T39	325776	47	0	0
T81	0	12	0	0
T91	0	2	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	24	0	0
T146	0	6	0	0
T167	0	14	0	0
T174	0	34	0	0
T297	0	23	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	994	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	15	0	0
T32	0	5	0	0
T39	325776	46	0	0
T81	0	10	0	0
T91	0	9	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	2	0	0
T146	0	15	0	0
T167	0	23	0	0
T174	0	22	0	0
T297	0	10	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3651	0	0
T5	247459	59	0	0
T6	219115	61	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	18	0	0
T32	0	13	0	0
T39	0	41	0	0
T73	0	115	0	0
T82	0	50	0	0
T139	0	38	0	0
T251	97849	0	0	0
T256	0	46	0	0
T264	0	38	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3471	0	0
T5	247459	73	0	0
T6	219115	60	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	13	0	0
T32	0	8	0	0
T39	0	36	0	0
T73	0	116	0	0
T82	0	73	0	0
T139	0	59	0	0
T251	97849	0	0	0
T256	0	41	0	0
T264	0	21	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3642	0	0
T5	247459	71	0	0
T6	219115	65	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	20	0	0
T32	0	4	0	0
T39	0	31	0	0
T73	0	94	0	0
T82	0	50	0	0
T139	0	46	0	0
T251	97849	0	0	0
T256	0	62	0	0
T264	0	23	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3438	0	0
T5	247459	70	0	0
T6	219115	85	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	14	0	0
T32	0	7	0	0
T39	0	45	0	0
T73	0	83	0	0
T82	0	82	0	0
T139	0	54	0	0
T251	97849	0	0	0
T256	0	76	0	0
T264	0	28	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3443	0	0
T5	247459	83	0	0
T6	219115	44	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	16	0	0
T32	0	3	0	0
T39	0	48	0	0
T73	0	107	0	0
T82	0	86	0	0
T139	0	29	0	0
T251	97849	0	0	0
T256	0	58	0	0
T264	0	15	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3570	0	0
T5	247459	69	0	0
T6	219115	79	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	20	0	0
T32	0	6	0	0
T39	0	27	0	0
T73	0	103	0	0
T82	0	66	0	0
T139	0	36	0	0
T251	97849	0	0	0
T256	0	55	0	0
T264	0	29	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3740	0	0
T5	247459	57	0	0
T6	219115	83	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	19	0	0
T32	0	20	0	0
T39	0	44	0	0
T73	0	84	0	0
T82	0	96	0	0
T139	0	38	0	0
T251	97849	0	0	0
T256	0	74	0	0
T264	0	31	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3687	0	0
T5	247459	84	0	0
T6	219115	64	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T29	0	20	0	0
T32	0	21	0	0
T39	0	38	0	0
T73	0	80	0	0
T82	0	70	0	0
T139	0	57	0	0
T251	97849	0	0	0
T256	0	65	0	0
T264	0	18	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1831	0	0
T5	247459	25	0	0
T6	219115	19	0	0
T7	101555	0	0	0
T8	113606	0	0	0
T24	159223	0	0	0
T25	73353	0	0	0
T26	250163	0	0	0
T27	10807	0	0	0
T28	230083	0	0	0
T39	0	42	0	0
T73	0	48	0	0
T82	0	13	0	0
T127	0	3	0	0
T130	0	3	0	0
T251	97849	0	0	0
T264	0	5	0	0
T265	0	3	0	0
T298	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1546	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	28	0	0
T32	0	46	0	0
T39	325776	47	0	0
T91	0	40	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	74	0	0
T146	0	6	0	0
T167	0	46	0	0
T174	0	9	0	0
T297	0	20	0	0
T299	0	18	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	3833	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T15	0	7	0	0
T17	0	5	0	0
T29	0	33	0	0
T32	0	23	0	0
T39	325776	38	0	0
T56	0	82	0	0
T86	0	7	0	0
T91	0	28	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	22	0	0
T173	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1026	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	10	0	0
T32	0	5	0	0
T39	325776	44	0	0
T81	0	8	0	0
T91	0	17	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	16	0	0
T146	0	1	0	0
T167	0	22	0	0
T174	0	11	0	0
T297	0	16	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	4331	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	172	0	0
T32	0	7	0	0
T39	325776	131	0	0
T60	0	101	0	0
T61	0	93	0	0
T91	0	20	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	160	0	0
T167	0	44	0	0
T297	0	14	0	0
T300	0	74	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	6336	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	130	0	0
T32	0	50	0	0
T39	325776	116	0	0
T70	0	86	0	0
T91	0	77	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T263	0	45	0	0
T274	0	77	0	0
T301	0	84	0	0
T302	0	71	0	0
T303	0	73	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	4573	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	178	0	0
T32	0	86	0	0
T39	325776	91	0	0
T70	0	55	0	0
T91	0	72	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T263	0	45	0	0
T274	0	90	0	0
T301	0	80	0	0
T302	0	32	0	0
T303	0	86	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	4838	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	149	0	0
T32	0	69	0	0
T39	325776	93	0	0
T70	0	84	0	0
T91	0	82	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T263	0	45	0	0
T274	0	64	0	0
T301	0	61	0	0
T302	0	32	0	0
T303	0	72	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1244	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	0	0	0
T29	0	16	0	0
T32	0	8	0	0
T39	325776	21	0	0
T81	0	21	0	0
T91	0	7	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	9	0	0
T146	0	8	0	0
T167	0	40	0	0
T174	0	6	0	0
T297	0	25	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1189	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	15	0	0
T21	0	7	0	0
T29	0	15	0	0
T32	0	10	0	0
T39	325776	39	0	0
T91	0	6	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	17	0	0
T167	0	53	0	0
T174	0	26	0	0
T297	0	23	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1021	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	4	0	0
T29	0	21	0	0
T32	0	23	0	0
T39	325776	44	0	0
T91	0	6	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	4	0	0
T167	0	41	0	0
T174	0	12	0	0
T297	0	10	0	0
T304	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1121	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	1	0	0
T21	0	4	0	0
T29	0	14	0	0
T32	0	19	0	0
T39	325776	40	0	0
T91	0	16	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	15	0	0
T167	0	10	0	0
T174	0	8	0	0
T297	0	15	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1257058637	1153	0	0
T10	245965	0	0	0
T11	317328	0	0	0
T12	194194	0	0	0
T13	116506	0	0	0
T14	21415	8	0	0
T21	0	5	0	0
T29	0	16	0	0
T32	0	6	0	0
T39	325776	41	0	0
T91	0	16	0	0
T126	46598	0	0	0
T127	455925	0	0	0
T129	78948	0	0	0
T130	94348	0	0	0
T132	0	22	0	0
T167	0	26	0	0
T174	0	15	0	0
T297	0	14	0	0