| T427 |
/workspace/coverage/default/16.sysrst_ctrl_alert_test.154575467 |
|
|
Mar 05 01:30:01 PM PST 24 |
Mar 05 01:30:06 PM PST 24 |
2020098404 ps |
| T351 |
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3573939869 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:32:12 PM PST 24 |
52018692113 ps |
| T428 |
/workspace/coverage/default/46.sysrst_ctrl_smoke.978158980 |
|
|
Mar 05 01:31:35 PM PST 24 |
Mar 05 01:31:37 PM PST 24 |
2125278659 ps |
| T429 |
/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3818951348 |
|
|
Mar 05 01:29:03 PM PST 24 |
Mar 05 01:29:04 PM PST 24 |
2222750820 ps |
| T430 |
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.322199088 |
|
|
Mar 05 01:31:24 PM PST 24 |
Mar 05 01:31:32 PM PST 24 |
5537239189 ps |
| T431 |
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.577207774 |
|
|
Mar 05 01:29:21 PM PST 24 |
Mar 05 01:29:23 PM PST 24 |
2105472621 ps |
| T432 |
/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.793309929 |
|
|
Mar 05 01:30:40 PM PST 24 |
Mar 05 01:30:45 PM PST 24 |
2620763146 ps |
| T433 |
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4099193999 |
|
|
Mar 05 01:29:23 PM PST 24 |
Mar 05 01:29:27 PM PST 24 |
2616659273 ps |
| T105 |
/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3481055055 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:31:12 PM PST 24 |
38167379907 ps |
| T339 |
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1336000195 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:32:31 PM PST 24 |
65504646555 ps |
| T434 |
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.4260850288 |
|
|
Mar 05 01:31:52 PM PST 24 |
Mar 05 01:35:41 PM PST 24 |
86252520383 ps |
| T435 |
/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1345799671 |
|
|
Mar 05 01:30:08 PM PST 24 |
Mar 05 01:30:09 PM PST 24 |
2169834412 ps |
| T214 |
/workspace/coverage/default/27.sysrst_ctrl_edge_detect.113761947 |
|
|
Mar 05 01:30:37 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
4996054987 ps |
| T436 |
/workspace/coverage/default/27.sysrst_ctrl_smoke.2068698756 |
|
|
Mar 05 01:30:35 PM PST 24 |
Mar 05 01:30:36 PM PST 24 |
2218679331 ps |
| T437 |
/workspace/coverage/default/24.sysrst_ctrl_alert_test.4223859589 |
|
|
Mar 05 01:30:29 PM PST 24 |
Mar 05 01:30:30 PM PST 24 |
2050837709 ps |
| T335 |
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.274190081 |
|
|
Mar 05 01:31:49 PM PST 24 |
Mar 05 01:36:28 PM PST 24 |
108854955703 ps |
| T438 |
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1258276263 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:31:23 PM PST 24 |
167214329474 ps |
| T439 |
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3232058434 |
|
|
Mar 05 01:31:26 PM PST 24 |
Mar 05 01:31:29 PM PST 24 |
2628418575 ps |
| T440 |
/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2253405430 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:06 PM PST 24 |
2629974390 ps |
| T441 |
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1213112815 |
|
|
Mar 05 01:29:27 PM PST 24 |
Mar 05 01:29:30 PM PST 24 |
2536475176 ps |
| T442 |
/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3145786847 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:11 PM PST 24 |
2887614828 ps |
| T443 |
/workspace/coverage/default/7.sysrst_ctrl_smoke.222034421 |
|
|
Mar 05 01:29:20 PM PST 24 |
Mar 05 01:29:26 PM PST 24 |
2113430452 ps |
| T444 |
/workspace/coverage/default/17.sysrst_ctrl_smoke.2056329604 |
|
|
Mar 05 01:30:00 PM PST 24 |
Mar 05 01:30:03 PM PST 24 |
2119986090 ps |
| T299 |
/workspace/coverage/default/46.sysrst_ctrl_stress_all.887945290 |
|
|
Mar 05 01:31:32 PM PST 24 |
Mar 05 01:31:42 PM PST 24 |
7110724439 ps |
| T445 |
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.237626972 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:31:49 PM PST 24 |
3300048785 ps |
| T446 |
/workspace/coverage/default/9.sysrst_ctrl_smoke.1677499541 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:29:28 PM PST 24 |
2133085246 ps |
| T337 |
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3266422997 |
|
|
Mar 05 01:31:56 PM PST 24 |
Mar 05 01:32:26 PM PST 24 |
74065875613 ps |
| T447 |
/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2926354214 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:10 PM PST 24 |
2454474275 ps |
| T448 |
/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2425890280 |
|
|
Mar 05 01:30:45 PM PST 24 |
Mar 05 01:30:48 PM PST 24 |
6758864065 ps |
| T449 |
/workspace/coverage/default/43.sysrst_ctrl_smoke.2375164183 |
|
|
Mar 05 01:31:23 PM PST 24 |
Mar 05 01:31:30 PM PST 24 |
2112700109 ps |
| T364 |
/workspace/coverage/default/30.sysrst_ctrl_stress_all.4290011286 |
|
|
Mar 05 01:30:55 PM PST 24 |
Mar 05 01:31:19 PM PST 24 |
16189113593 ps |
| T450 |
/workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1360955019 |
|
|
Mar 05 01:31:09 PM PST 24 |
Mar 05 01:31:11 PM PST 24 |
2637770316 ps |
| T106 |
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3833718928 |
|
|
Mar 05 01:31:33 PM PST 24 |
Mar 05 01:32:16 PM PST 24 |
62195261968 ps |
| T451 |
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1306169627 |
|
|
Mar 05 01:31:55 PM PST 24 |
Mar 05 01:32:48 PM PST 24 |
68316670339 ps |
| T300 |
/workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.317837026 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:28:58 PM PST 24 |
2479061146 ps |
| T452 |
/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.91534751 |
|
|
Mar 05 01:30:28 PM PST 24 |
Mar 05 01:33:30 PM PST 24 |
263669995135 ps |
| T453 |
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2177888628 |
|
|
Mar 05 01:31:25 PM PST 24 |
Mar 05 01:31:29 PM PST 24 |
2519120631 ps |
| T454 |
/workspace/coverage/default/10.sysrst_ctrl_stress_all.3416866231 |
|
|
Mar 05 01:29:33 PM PST 24 |
Mar 05 01:29:53 PM PST 24 |
7053619680 ps |
| T455 |
/workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2891000706 |
|
|
Mar 05 01:30:40 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
2856942612 ps |
| T456 |
/workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2908664532 |
|
|
Mar 05 01:30:44 PM PST 24 |
Mar 05 01:30:48 PM PST 24 |
5189379224 ps |
| T457 |
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3987720758 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:31:42 PM PST 24 |
3205400381 ps |
| T458 |
/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.625389838 |
|
|
Mar 05 01:30:18 PM PST 24 |
Mar 05 01:30:19 PM PST 24 |
2269923792 ps |
| T343 |
/workspace/coverage/default/25.sysrst_ctrl_combo_detect.2876126653 |
|
|
Mar 05 01:30:30 PM PST 24 |
Mar 05 01:31:39 PM PST 24 |
118199752305 ps |
| T459 |
/workspace/coverage/default/36.sysrst_ctrl_smoke.652133577 |
|
|
Mar 05 01:31:06 PM PST 24 |
Mar 05 01:31:10 PM PST 24 |
2118925232 ps |
| T460 |
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4097864501 |
|
|
Mar 05 01:31:48 PM PST 24 |
Mar 05 01:32:20 PM PST 24 |
39080798259 ps |
| T461 |
/workspace/coverage/default/45.sysrst_ctrl_stress_all.3998479933 |
|
|
Mar 05 01:31:34 PM PST 24 |
Mar 05 01:32:06 PM PST 24 |
12458098797 ps |
| T133 |
/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.385306250 |
|
|
Mar 05 01:31:13 PM PST 24 |
Mar 05 01:31:20 PM PST 24 |
6222714538 ps |
| T462 |
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4223930601 |
|
|
Mar 05 01:31:25 PM PST 24 |
Mar 05 01:31:29 PM PST 24 |
3071751611 ps |
| T183 |
/workspace/coverage/default/39.sysrst_ctrl_edge_detect.3241397098 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:31:28 PM PST 24 |
4205136239 ps |
| T167 |
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.778002236 |
|
|
Mar 05 01:31:41 PM PST 24 |
Mar 05 01:32:28 PM PST 24 |
91734915075 ps |
| T205 |
/workspace/coverage/default/34.sysrst_ctrl_alert_test.4035098819 |
|
|
Mar 05 01:31:04 PM PST 24 |
Mar 05 01:31:05 PM PST 24 |
2096198282 ps |
| T174 |
/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1903515434 |
|
|
Mar 05 01:30:31 PM PST 24 |
Mar 05 01:31:31 PM PST 24 |
28451403326 ps |
| T206 |
/workspace/coverage/default/6.sysrst_ctrl_stress_all.702761457 |
|
|
Mar 05 01:29:18 PM PST 24 |
Mar 05 01:29:27 PM PST 24 |
6527834000 ps |
| T207 |
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2146860602 |
|
|
Mar 05 01:31:52 PM PST 24 |
Mar 05 01:32:09 PM PST 24 |
24858030206 ps |
| T208 |
/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4017193091 |
|
|
Mar 05 01:30:59 PM PST 24 |
Mar 05 01:31:06 PM PST 24 |
2509353989 ps |
| T209 |
/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2887037498 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:31:37 PM PST 24 |
31127586299 ps |
| T210 |
/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3422673114 |
|
|
Mar 05 01:30:56 PM PST 24 |
Mar 05 01:31:03 PM PST 24 |
2507402957 ps |
| T211 |
/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.615320512 |
|
|
Mar 05 01:29:54 PM PST 24 |
Mar 05 01:29:58 PM PST 24 |
2617900858 ps |
| T212 |
/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2920250757 |
|
|
Mar 05 01:30:29 PM PST 24 |
Mar 05 01:30:36 PM PST 24 |
7061591803 ps |
| T463 |
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2459678249 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:31 PM PST 24 |
3238692856 ps |
| T464 |
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3971363115 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:31:39 PM PST 24 |
2510541309 ps |
| T465 |
/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.336503818 |
|
|
Mar 05 01:30:58 PM PST 24 |
Mar 05 01:31:06 PM PST 24 |
2512246834 ps |
| T95 |
/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.388943439 |
|
|
Mar 05 01:30:03 PM PST 24 |
Mar 05 01:30:07 PM PST 24 |
3280731795 ps |
| T466 |
/workspace/coverage/default/23.sysrst_ctrl_alert_test.3116747991 |
|
|
Mar 05 01:30:28 PM PST 24 |
Mar 05 01:30:30 PM PST 24 |
2035942714 ps |
| T467 |
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3119721557 |
|
|
Mar 05 01:29:25 PM PST 24 |
Mar 05 01:29:32 PM PST 24 |
2456234090 ps |
| T468 |
/workspace/coverage/default/49.sysrst_ctrl_smoke.2133156754 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:31:42 PM PST 24 |
2129551821 ps |
| T469 |
/workspace/coverage/default/48.sysrst_ctrl_stress_all.748865616 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:31:55 PM PST 24 |
10727823464 ps |
| T470 |
/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2273444979 |
|
|
Mar 05 01:30:46 PM PST 24 |
Mar 05 01:30:54 PM PST 24 |
2612769919 ps |
| T471 |
/workspace/coverage/default/17.sysrst_ctrl_edge_detect.1937052112 |
|
|
Mar 05 01:30:04 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
2459913470 ps |
| T472 |
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3668287199 |
|
|
Mar 05 01:31:43 PM PST 24 |
Mar 05 01:31:45 PM PST 24 |
2098406003 ps |
| T473 |
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3637606065 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:30 PM PST 24 |
2519178550 ps |
| T474 |
/workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3738679793 |
|
|
Mar 05 01:31:01 PM PST 24 |
Mar 05 01:31:03 PM PST 24 |
3187901646 ps |
| T475 |
/workspace/coverage/default/14.sysrst_ctrl_alert_test.858264016 |
|
|
Mar 05 01:29:53 PM PST 24 |
Mar 05 01:29:55 PM PST 24 |
2037734408 ps |
| T476 |
/workspace/coverage/default/2.sysrst_ctrl_stress_all.1587727542 |
|
|
Mar 05 01:29:13 PM PST 24 |
Mar 05 01:29:26 PM PST 24 |
9189964903 ps |
| T477 |
/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3742571037 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:31:03 PM PST 24 |
3266336653 ps |
| T107 |
/workspace/coverage/default/15.sysrst_ctrl_stress_all.1116523390 |
|
|
Mar 05 01:30:01 PM PST 24 |
Mar 05 01:30:59 PM PST 24 |
87094603496 ps |
| T478 |
/workspace/coverage/default/31.sysrst_ctrl_stress_all.3944642020 |
|
|
Mar 05 01:30:56 PM PST 24 |
Mar 05 01:31:05 PM PST 24 |
6590730176 ps |
| T479 |
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.4005260304 |
|
|
Mar 05 01:31:41 PM PST 24 |
Mar 05 01:40:24 PM PST 24 |
199572016895 ps |
| T480 |
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.830871871 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:30:59 PM PST 24 |
69165813655 ps |
| T481 |
/workspace/coverage/default/11.sysrst_ctrl_smoke.1032856968 |
|
|
Mar 05 01:29:37 PM PST 24 |
Mar 05 01:29:42 PM PST 24 |
2109004222 ps |
| T482 |
/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1379942449 |
|
|
Mar 05 01:30:42 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
2184735920 ps |
| T483 |
/workspace/coverage/default/45.sysrst_ctrl_smoke.418961460 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:36 PM PST 24 |
2113722513 ps |
| T352 |
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1180543526 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:32:29 PM PST 24 |
61978519000 ps |
| T484 |
/workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3666401015 |
|
|
Mar 05 01:31:06 PM PST 24 |
Mar 05 01:31:07 PM PST 24 |
3737138142 ps |
| T485 |
/workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2583677960 |
|
|
Mar 05 01:30:22 PM PST 24 |
Mar 05 01:30:25 PM PST 24 |
2500511307 ps |
| T486 |
/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.234440723 |
|
|
Mar 05 01:28:55 PM PST 24 |
Mar 05 01:29:03 PM PST 24 |
2612807267 ps |
| T487 |
/workspace/coverage/default/35.sysrst_ctrl_edge_detect.2569475799 |
|
|
Mar 05 01:31:06 PM PST 24 |
Mar 05 01:31:08 PM PST 24 |
3050834215 ps |
| T221 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all.4290427312 |
|
|
Mar 05 01:30:22 PM PST 24 |
Mar 05 01:30:44 PM PST 24 |
16981632337 ps |
| T223 |
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2073012368 |
|
|
Mar 05 01:29:21 PM PST 24 |
Mar 05 01:30:59 PM PST 24 |
74227397648 ps |
| T224 |
/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.36662886 |
|
|
Mar 05 01:30:18 PM PST 24 |
Mar 05 01:30:23 PM PST 24 |
2981779955 ps |
| T225 |
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2567112146 |
|
|
Mar 05 01:29:25 PM PST 24 |
Mar 05 01:29:34 PM PST 24 |
2612219274 ps |
| T226 |
/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.4049029802 |
|
|
Mar 05 01:30:32 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
2507580079 ps |
| T227 |
/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2340783987 |
|
|
Mar 05 01:30:58 PM PST 24 |
Mar 05 01:31:00 PM PST 24 |
2661455663 ps |
| T228 |
/workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2733669266 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:30:58 PM PST 24 |
2462902145 ps |
| T229 |
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3002256790 |
|
|
Mar 05 01:31:45 PM PST 24 |
Mar 05 01:31:54 PM PST 24 |
2842386263 ps |
| T230 |
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3856637158 |
|
|
Mar 05 01:29:28 PM PST 24 |
Mar 05 01:29:30 PM PST 24 |
2480067668 ps |
| T231 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.649454995 |
|
|
Mar 05 01:29:01 PM PST 24 |
Mar 05 01:29:07 PM PST 24 |
2207801423 ps |
| T260 |
/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1130470087 |
|
|
Mar 05 01:30:04 PM PST 24 |
Mar 05 01:33:05 PM PST 24 |
211627410654 ps |
| T488 |
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.616907230 |
|
|
Mar 05 01:29:20 PM PST 24 |
Mar 05 01:29:27 PM PST 24 |
2455054055 ps |
| T489 |
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.732037695 |
|
|
Mar 05 01:31:51 PM PST 24 |
Mar 05 01:32:40 PM PST 24 |
70764753171 ps |
| T222 |
/workspace/coverage/default/0.sysrst_ctrl_edge_detect.3452985369 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:30:03 PM PST 24 |
243958303814 ps |
| T490 |
/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3475365344 |
|
|
Mar 05 01:29:52 PM PST 24 |
Mar 05 01:29:54 PM PST 24 |
2199759708 ps |
| T491 |
/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3722988830 |
|
|
Mar 05 01:30:36 PM PST 24 |
Mar 05 01:30:44 PM PST 24 |
3145000149 ps |
| T492 |
/workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3442411668 |
|
|
Mar 05 01:30:10 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
2242950133 ps |
| T493 |
/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1195305944 |
|
|
Mar 05 01:30:36 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
2222764545 ps |
| T88 |
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3387843130 |
|
|
Mar 05 01:31:48 PM PST 24 |
Mar 05 01:32:44 PM PST 24 |
154266757442 ps |
| T494 |
/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2241898564 |
|
|
Mar 05 01:30:01 PM PST 24 |
Mar 05 01:30:09 PM PST 24 |
2446303918 ps |
| T495 |
/workspace/coverage/default/43.sysrst_ctrl_alert_test.3860192271 |
|
|
Mar 05 01:31:29 PM PST 24 |
Mar 05 01:31:36 PM PST 24 |
2012342629 ps |
| T496 |
/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1855832229 |
|
|
Mar 05 01:30:45 PM PST 24 |
Mar 05 01:30:47 PM PST 24 |
6602365803 ps |
| T497 |
/workspace/coverage/default/1.sysrst_ctrl_stress_all.852398823 |
|
|
Mar 05 01:29:02 PM PST 24 |
Mar 05 01:40:59 PM PST 24 |
268599234410 ps |
| T498 |
/workspace/coverage/default/2.sysrst_ctrl_edge_detect.182182330 |
|
|
Mar 05 01:29:15 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
2553118609 ps |
| T499 |
/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1992347885 |
|
|
Mar 05 01:30:38 PM PST 24 |
Mar 05 01:30:44 PM PST 24 |
3471860078 ps |
| T281 |
/workspace/coverage/default/2.sysrst_ctrl_sec_cm.853309856 |
|
|
Mar 05 01:29:11 PM PST 24 |
Mar 05 01:30:11 PM PST 24 |
22011636362 ps |
| T500 |
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1531354071 |
|
|
Mar 05 01:29:32 PM PST 24 |
Mar 05 01:29:35 PM PST 24 |
4852814591 ps |
| T501 |
/workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3390513843 |
|
|
Mar 05 01:29:13 PM PST 24 |
Mar 05 01:29:20 PM PST 24 |
2436226940 ps |
| T502 |
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2072381268 |
|
|
Mar 05 01:29:19 PM PST 24 |
Mar 05 01:29:29 PM PST 24 |
3945513230 ps |
| T503 |
/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.83674931 |
|
|
Mar 05 01:31:05 PM PST 24 |
Mar 05 01:31:08 PM PST 24 |
2252784020 ps |
| T279 |
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2723283971 |
|
|
Mar 05 01:31:27 PM PST 24 |
Mar 05 01:32:27 PM PST 24 |
20656876473 ps |
| T504 |
/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2472831829 |
|
|
Mar 05 01:31:08 PM PST 24 |
Mar 05 01:31:15 PM PST 24 |
2206991105 ps |
| T305 |
/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.957169129 |
|
|
Mar 05 01:31:07 PM PST 24 |
Mar 05 01:31:43 PM PST 24 |
149196781889 ps |
| T293 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.799565317 |
|
|
Mar 05 01:30:56 PM PST 24 |
Mar 05 01:32:37 PM PST 24 |
38408619774 ps |
| T505 |
/workspace/coverage/default/12.sysrst_ctrl_alert_test.1118952849 |
|
|
Mar 05 01:29:42 PM PST 24 |
Mar 05 01:29:44 PM PST 24 |
2027852712 ps |
| T261 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect.1765775881 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:31:25 PM PST 24 |
57794800513 ps |
| T506 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all.3502576502 |
|
|
Mar 05 01:30:19 PM PST 24 |
Mar 05 01:30:23 PM PST 24 |
7151328887 ps |
| T191 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all.1092213810 |
|
|
Mar 05 01:30:11 PM PST 24 |
Mar 05 01:30:31 PM PST 24 |
11475425325 ps |
| T507 |
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3030200099 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:29:33 PM PST 24 |
2215422187 ps |
| T508 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1105496574 |
|
|
Mar 05 01:29:13 PM PST 24 |
Mar 05 01:29:19 PM PST 24 |
2270171317 ps |
| T509 |
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3502713076 |
|
|
Mar 05 01:31:42 PM PST 24 |
Mar 05 01:31:44 PM PST 24 |
2084865009 ps |
| T510 |
/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2058921904 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:13 PM PST 24 |
2526986417 ps |
| T511 |
/workspace/coverage/default/14.sysrst_ctrl_smoke.2645964506 |
|
|
Mar 05 01:29:51 PM PST 24 |
Mar 05 01:29:53 PM PST 24 |
2123066348 ps |
| T512 |
/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.19758332 |
|
|
Mar 05 01:29:03 PM PST 24 |
Mar 05 01:29:07 PM PST 24 |
2484672920 ps |
| T513 |
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3069066962 |
|
|
Mar 05 01:31:32 PM PST 24 |
Mar 05 01:31:36 PM PST 24 |
3204684495 ps |
| T307 |
/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2939952826 |
|
|
Mar 05 01:29:49 PM PST 24 |
Mar 05 01:31:20 PM PST 24 |
37711194851 ps |
| T514 |
/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1840873700 |
|
|
Mar 05 01:30:10 PM PST 24 |
Mar 05 01:30:14 PM PST 24 |
3753587041 ps |
| T515 |
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1499921203 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:35:39 PM PST 24 |
327006926407 ps |
| T516 |
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3113148177 |
|
|
Mar 05 01:31:51 PM PST 24 |
Mar 05 01:32:44 PM PST 24 |
77048906044 ps |
| T517 |
/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2916908561 |
|
|
Mar 05 01:29:36 PM PST 24 |
Mar 05 01:29:38 PM PST 24 |
2292944690 ps |
| T518 |
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.514919166 |
|
|
Mar 05 01:29:18 PM PST 24 |
Mar 05 01:29:21 PM PST 24 |
3245587206 ps |
| T304 |
/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1992566754 |
|
|
Mar 05 01:30:36 PM PST 24 |
Mar 05 01:30:43 PM PST 24 |
3563029354 ps |
| T247 |
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2326843234 |
|
|
Mar 05 01:31:45 PM PST 24 |
Mar 05 01:32:11 PM PST 24 |
45739772947 ps |
| T519 |
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.289377592 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
92890870051 ps |
| T96 |
/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1745518297 |
|
|
Mar 05 01:29:43 PM PST 24 |
Mar 05 01:29:51 PM PST 24 |
6365097873 ps |
| T520 |
/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4146512218 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:29:41 PM PST 24 |
4233009556 ps |
| T270 |
/workspace/coverage/default/17.sysrst_ctrl_combo_detect.2860179910 |
|
|
Mar 05 01:29:59 PM PST 24 |
Mar 05 01:34:12 PM PST 24 |
95836567393 ps |
| T168 |
/workspace/coverage/default/41.sysrst_ctrl_stress_all.856302799 |
|
|
Mar 05 01:31:21 PM PST 24 |
Mar 05 01:35:04 PM PST 24 |
87912779237 ps |
| T521 |
/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3035286788 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:30:54 PM PST 24 |
2572637089 ps |
| T522 |
/workspace/coverage/default/3.sysrst_ctrl_smoke.947856436 |
|
|
Mar 05 01:29:11 PM PST 24 |
Mar 05 01:29:13 PM PST 24 |
2120785067 ps |
| T523 |
/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2870149065 |
|
|
Mar 05 01:29:34 PM PST 24 |
Mar 05 01:29:42 PM PST 24 |
3082207241 ps |
| T524 |
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.868730997 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:31:41 PM PST 24 |
3741437871 ps |
| T368 |
/workspace/coverage/default/18.sysrst_ctrl_stress_all.2558964231 |
|
|
Mar 05 01:30:08 PM PST 24 |
Mar 05 01:30:27 PM PST 24 |
77551666011 ps |
| T525 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1401386211 |
|
|
Mar 05 01:29:11 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
2236817997 ps |
| T361 |
/workspace/coverage/default/14.sysrst_ctrl_combo_detect.4248683457 |
|
|
Mar 05 01:29:51 PM PST 24 |
Mar 05 01:33:58 PM PST 24 |
97037976625 ps |
| T526 |
/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2985163827 |
|
|
Mar 05 01:31:15 PM PST 24 |
Mar 05 01:31:26 PM PST 24 |
3703286472 ps |
| T277 |
/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2615955198 |
|
|
Mar 05 01:30:57 PM PST 24 |
Mar 05 01:32:30 PM PST 24 |
34862082656 ps |
| T184 |
/workspace/coverage/default/24.sysrst_ctrl_edge_detect.4173814938 |
|
|
Mar 05 01:30:30 PM PST 24 |
Mar 05 01:30:38 PM PST 24 |
5261433473 ps |
| T527 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2133210729 |
|
|
Mar 05 01:30:35 PM PST 24 |
Mar 05 01:33:07 PM PST 24 |
99585379258 ps |
| T528 |
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2649028651 |
|
|
Mar 05 01:31:51 PM PST 24 |
Mar 05 01:33:42 PM PST 24 |
83708954145 ps |
| T529 |
/workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2103210358 |
|
|
Mar 05 01:31:06 PM PST 24 |
Mar 05 01:31:07 PM PST 24 |
2657995153 ps |
| T530 |
/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3054335765 |
|
|
Mar 05 01:31:15 PM PST 24 |
Mar 05 01:31:24 PM PST 24 |
3227980511 ps |
| T531 |
/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2047286385 |
|
|
Mar 05 01:31:13 PM PST 24 |
Mar 05 01:31:16 PM PST 24 |
3400531945 ps |
| T532 |
/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.3244365740 |
|
|
Mar 05 01:30:38 PM PST 24 |
Mar 05 01:30:45 PM PST 24 |
2509414199 ps |
| T185 |
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3576139465 |
|
|
Mar 05 01:31:22 PM PST 24 |
Mar 05 01:31:49 PM PST 24 |
44923208040 ps |
| T533 |
/workspace/coverage/default/1.sysrst_ctrl_smoke.922543129 |
|
|
Mar 05 01:29:02 PM PST 24 |
Mar 05 01:29:06 PM PST 24 |
2120536748 ps |
| T534 |
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.809594298 |
|
|
Mar 05 01:31:16 PM PST 24 |
Mar 05 01:31:18 PM PST 24 |
2553780685 ps |
| T535 |
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2185240105 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:32 PM PST 24 |
2523902945 ps |
| T536 |
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.891421235 |
|
|
Mar 05 01:31:17 PM PST 24 |
Mar 05 01:31:19 PM PST 24 |
2643911475 ps |
| T537 |
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1511102773 |
|
|
Mar 05 01:31:21 PM PST 24 |
Mar 05 01:31:28 PM PST 24 |
2508700561 ps |
| T538 |
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3927570604 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:31:54 PM PST 24 |
2465468706 ps |
| T194 |
/workspace/coverage/default/31.sysrst_ctrl_edge_detect.1079474170 |
|
|
Mar 05 01:30:57 PM PST 24 |
Mar 05 01:31:03 PM PST 24 |
4973819884 ps |
| T539 |
/workspace/coverage/default/37.sysrst_ctrl_edge_detect.1145198094 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:12 PM PST 24 |
2495021866 ps |
| T540 |
/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1670468471 |
|
|
Mar 05 01:28:54 PM PST 24 |
Mar 05 01:28:57 PM PST 24 |
3524917282 ps |
| T541 |
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.574487616 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:31:26 PM PST 24 |
2465540187 ps |
| T542 |
/workspace/coverage/default/41.sysrst_ctrl_smoke.3995681084 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:31:20 PM PST 24 |
2141551416 ps |
| T543 |
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.4174206445 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:32:33 PM PST 24 |
40850531135 ps |
| T544 |
/workspace/coverage/default/9.sysrst_ctrl_alert_test.641872194 |
|
|
Mar 05 01:29:37 PM PST 24 |
Mar 05 01:29:39 PM PST 24 |
2026667185 ps |
| T545 |
/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.569897794 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:30:56 PM PST 24 |
3087250577 ps |
| T546 |
/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.926038579 |
|
|
Mar 05 01:29:10 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
2610331537 ps |
| T355 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1254341895 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:33:56 PM PST 24 |
98501941268 ps |
| T341 |
/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1416717519 |
|
|
Mar 05 01:30:36 PM PST 24 |
Mar 05 01:33:18 PM PST 24 |
61195516995 ps |
| T547 |
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2912605888 |
|
|
Mar 05 01:31:23 PM PST 24 |
Mar 05 01:31:26 PM PST 24 |
2180194921 ps |
| T548 |
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1321705752 |
|
|
Mar 05 01:29:12 PM PST 24 |
Mar 05 01:29:20 PM PST 24 |
2610177128 ps |
| T549 |
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1422697073 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:29:31 PM PST 24 |
5226280250 ps |
| T550 |
/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3742859625 |
|
|
Mar 05 01:29:51 PM PST 24 |
Mar 05 01:30:01 PM PST 24 |
3092429191 ps |
| T551 |
/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3401292892 |
|
|
Mar 05 01:28:57 PM PST 24 |
Mar 05 01:29:03 PM PST 24 |
2761340346 ps |
| T192 |
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2819477732 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:31:55 PM PST 24 |
3337197658 ps |
| T552 |
/workspace/coverage/default/44.sysrst_ctrl_smoke.4062474078 |
|
|
Mar 05 01:31:32 PM PST 24 |
Mar 05 01:31:38 PM PST 24 |
2111434763 ps |
| T553 |
/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2983921275 |
|
|
Mar 05 01:30:45 PM PST 24 |
Mar 05 01:30:51 PM PST 24 |
2234108829 ps |
| T554 |
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2926175500 |
|
|
Mar 05 01:31:48 PM PST 24 |
Mar 05 01:32:45 PM PST 24 |
21330780414 ps |
| T555 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2511400311 |
|
|
Mar 05 01:28:57 PM PST 24 |
Mar 05 01:29:04 PM PST 24 |
24381346718 ps |
| T345 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.901899741 |
|
|
Mar 05 01:29:18 PM PST 24 |
Mar 05 01:29:50 PM PST 24 |
117105455264 ps |
| T278 |
/workspace/coverage/default/34.sysrst_ctrl_stress_all.2087620678 |
|
|
Mar 05 01:31:03 PM PST 24 |
Mar 05 01:33:03 PM PST 24 |
44870972190 ps |
| T556 |
/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1176917235 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:09 PM PST 24 |
2111640738 ps |
| T557 |
/workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1715095456 |
|
|
Mar 05 01:29:14 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
4675642631 ps |
| T558 |
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2078875293 |
|
|
Mar 05 01:31:21 PM PST 24 |
Mar 05 01:31:24 PM PST 24 |
4621072141 ps |
| T559 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2937980583 |
|
|
Mar 05 01:28:59 PM PST 24 |
Mar 05 01:29:01 PM PST 24 |
2213095905 ps |
| T560 |
/workspace/coverage/default/18.sysrst_ctrl_alert_test.2573205986 |
|
|
Mar 05 01:30:08 PM PST 24 |
Mar 05 01:30:10 PM PST 24 |
2031110407 ps |
| T561 |
/workspace/coverage/default/38.sysrst_ctrl_edge_detect.618907838 |
|
|
Mar 05 01:31:08 PM PST 24 |
Mar 05 01:31:15 PM PST 24 |
3086984217 ps |
| T562 |
/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.600976938 |
|
|
Mar 05 01:30:55 PM PST 24 |
Mar 05 01:31:01 PM PST 24 |
2206122955 ps |
| T563 |
/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3442841881 |
|
|
Mar 05 01:30:19 PM PST 24 |
Mar 05 01:30:23 PM PST 24 |
3549093321 ps |
| T195 |
/workspace/coverage/default/12.sysrst_ctrl_edge_detect.3719888223 |
|
|
Mar 05 01:29:43 PM PST 24 |
Mar 05 01:29:46 PM PST 24 |
5571944702 ps |
| T108 |
/workspace/coverage/default/10.sysrst_ctrl_combo_detect.4266088099 |
|
|
Mar 05 01:29:36 PM PST 24 |
Mar 05 01:33:04 PM PST 24 |
79709428219 ps |
| T564 |
/workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.549805868 |
|
|
Mar 05 01:31:04 PM PST 24 |
Mar 05 01:31:07 PM PST 24 |
3666207168 ps |
| T565 |
/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.457826181 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:28:59 PM PST 24 |
2225501703 ps |
| T566 |
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1921398727 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:29:31 PM PST 24 |
2630371797 ps |
| T567 |
/workspace/coverage/default/17.sysrst_ctrl_stress_all.2052546840 |
|
|
Mar 05 01:30:03 PM PST 24 |
Mar 05 01:30:17 PM PST 24 |
17609618199 ps |
| T181 |
/workspace/coverage/default/16.sysrst_ctrl_edge_detect.2742580297 |
|
|
Mar 05 01:30:03 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
4926919736 ps |
| T92 |
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1402072594 |
|
|
Mar 05 01:29:34 PM PST 24 |
Mar 05 01:29:41 PM PST 24 |
3042737763 ps |
| T146 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3692515831 |
|
|
Mar 05 01:30:15 PM PST 24 |
Mar 05 01:30:37 PM PST 24 |
32117783898 ps |
| T147 |
/workspace/coverage/default/31.sysrst_ctrl_smoke.4247497750 |
|
|
Mar 05 01:30:56 PM PST 24 |
Mar 05 01:31:01 PM PST 24 |
2108026825 ps |
| T148 |
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3366248364 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:34:39 PM PST 24 |
132067764722 ps |
| T149 |
/workspace/coverage/default/29.sysrst_ctrl_edge_detect.1178763837 |
|
|
Mar 05 01:30:46 PM PST 24 |
Mar 05 01:30:53 PM PST 24 |
2690068419 ps |
| T150 |
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1232884418 |
|
|
Mar 05 01:29:21 PM PST 24 |
Mar 05 01:29:29 PM PST 24 |
2510922736 ps |
| T151 |
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1029295833 |
|
|
Mar 05 01:31:37 PM PST 24 |
Mar 05 01:32:38 PM PST 24 |
91738469628 ps |
| T152 |
/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2373478380 |
|
|
Mar 05 01:30:26 PM PST 24 |
Mar 05 01:30:31 PM PST 24 |
2472413103 ps |
| T153 |
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3108734496 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:29:33 PM PST 24 |
3924827935 ps |
| T154 |
/workspace/coverage/default/33.sysrst_ctrl_combo_detect.1433732858 |
|
|
Mar 05 01:30:55 PM PST 24 |
Mar 05 01:34:34 PM PST 24 |
96866409538 ps |
| T186 |
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1424398121 |
|
|
Mar 05 01:31:51 PM PST 24 |
Mar 05 01:32:27 PM PST 24 |
53376662490 ps |
| T187 |
/workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3916082498 |
|
|
Mar 05 01:31:02 PM PST 24 |
Mar 05 01:31:06 PM PST 24 |
2514426476 ps |
| T188 |
/workspace/coverage/default/23.sysrst_ctrl_smoke.1089098807 |
|
|
Mar 05 01:30:23 PM PST 24 |
Mar 05 01:30:30 PM PST 24 |
2110360005 ps |
| T189 |
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.248590481 |
|
|
Mar 05 01:31:39 PM PST 24 |
Mar 05 01:31:41 PM PST 24 |
2066791934 ps |
| T568 |
/workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2595185648 |
|
|
Mar 05 01:29:02 PM PST 24 |
Mar 05 01:29:04 PM PST 24 |
2496521937 ps |
| T569 |
/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1511267394 |
|
|
Mar 05 01:30:18 PM PST 24 |
Mar 05 01:30:25 PM PST 24 |
2512932360 ps |
| T570 |
/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1778760762 |
|
|
Mar 05 01:29:54 PM PST 24 |
Mar 05 01:29:57 PM PST 24 |
3146898415 ps |
| T571 |
/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.239806568 |
|
|
Mar 05 01:29:52 PM PST 24 |
Mar 05 01:29:55 PM PST 24 |
2624853354 ps |
| T572 |
/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.459635461 |
|
|
Mar 05 01:30:19 PM PST 24 |
Mar 05 01:30:21 PM PST 24 |
2498096655 ps |
| T573 |
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.936800849 |
|
|
Mar 05 01:31:39 PM PST 24 |
Mar 05 01:31:41 PM PST 24 |
2555441248 ps |
| T574 |
/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1989596172 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:05 PM PST 24 |
2575842066 ps |
| T575 |
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2451344219 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:29:43 PM PST 24 |
16752050816 ps |
| T576 |
/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.4288596501 |
|
|
Mar 05 01:30:47 PM PST 24 |
Mar 05 01:30:54 PM PST 24 |
2464202960 ps |
| T577 |
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2570037939 |
|
|
Mar 05 01:31:39 PM PST 24 |
Mar 05 01:31:47 PM PST 24 |
2609347755 ps |
| T271 |
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3964711753 |
|
|
Mar 05 01:31:35 PM PST 24 |
Mar 05 01:35:41 PM PST 24 |
98620676736 ps |
| T306 |
/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4158223358 |
|
|
Mar 05 01:31:06 PM PST 24 |
Mar 05 01:32:13 PM PST 24 |
25025106988 ps |
| T578 |
/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3430860848 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:31:00 PM PST 24 |
2611591817 ps |
| T579 |
/workspace/coverage/default/34.sysrst_ctrl_smoke.62643757 |
|
|
Mar 05 01:30:58 PM PST 24 |
Mar 05 01:31:01 PM PST 24 |
2138248179 ps |
| T580 |
/workspace/coverage/default/39.sysrst_ctrl_stress_all.1383196649 |
|
|
Mar 05 01:31:17 PM PST 24 |
Mar 05 01:31:40 PM PST 24 |
12905421472 ps |
| T581 |
/workspace/coverage/default/35.sysrst_ctrl_alert_test.3162546458 |
|
|
Mar 05 01:31:02 PM PST 24 |
Mar 05 01:31:07 PM PST 24 |
2011724333 ps |
| T582 |
/workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1174150921 |
|
|
Mar 05 01:30:09 PM PST 24 |
Mar 05 01:30:21 PM PST 24 |
4055686014 ps |
| T583 |
/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2459075924 |
|
|
Mar 05 01:30:03 PM PST 24 |
Mar 05 01:30:08 PM PST 24 |
2513434220 ps |
| T109 |
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2567510245 |
|
|
Mar 05 01:29:20 PM PST 24 |
Mar 05 01:29:34 PM PST 24 |
27842424012 ps |
| T584 |
/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3742220558 |
|
|
Mar 05 01:30:35 PM PST 24 |
Mar 05 01:30:42 PM PST 24 |
2458096768 ps |
| T585 |
/workspace/coverage/default/37.sysrst_ctrl_smoke.3025118699 |
|
|
Mar 05 01:31:09 PM PST 24 |
Mar 05 01:31:15 PM PST 24 |
2111304445 ps |
| T586 |
/workspace/coverage/default/30.sysrst_ctrl_edge_detect.3623364150 |
|
|
Mar 05 01:30:47 PM PST 24 |
Mar 05 01:30:49 PM PST 24 |
3388810460 ps |
| T295 |
/workspace/coverage/default/3.sysrst_ctrl_sec_cm.2559158234 |
|
|
Mar 05 01:29:10 PM PST 24 |
Mar 05 01:30:03 PM PST 24 |
42029756987 ps |
| T587 |
/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.816163015 |
|
|
Mar 05 01:30:01 PM PST 24 |
Mar 05 01:30:04 PM PST 24 |
2523470721 ps |
| T588 |
/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3481155067 |
|
|
Mar 05 01:30:29 PM PST 24 |
Mar 05 01:30:32 PM PST 24 |
2811606381 ps |
| T589 |
/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.62801137 |
|
|
Mar 05 01:31:00 PM PST 24 |
Mar 05 01:31:04 PM PST 24 |
3327027019 ps |
| T350 |
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1086112066 |
|
|
Mar 05 01:31:23 PM PST 24 |
Mar 05 01:32:07 PM PST 24 |
65962437066 ps |
| T336 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all.6817836 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:32:39 PM PST 24 |
109572595138 ps |
| T169 |
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3000803139 |
|
|
Mar 05 01:31:25 PM PST 24 |
Mar 05 01:31:34 PM PST 24 |
3535746499 ps |
| T590 |
/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2608280046 |
|
|
Mar 05 01:30:17 PM PST 24 |
Mar 05 01:30:19 PM PST 24 |
3259147154 ps |