| T591 |
/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2933280199 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:29:40 PM PST 24 |
6414242662 ps |
| T592 |
/workspace/coverage/default/24.sysrst_ctrl_smoke.1752625423 |
|
|
Mar 05 01:30:29 PM PST 24 |
Mar 05 01:30:36 PM PST 24 |
2111874557 ps |
| T593 |
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.970724013 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:32:38 PM PST 24 |
65392982108 ps |
| T110 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect.660503602 |
|
|
Mar 05 01:30:36 PM PST 24 |
Mar 05 01:34:16 PM PST 24 |
80236332150 ps |
| T594 |
/workspace/coverage/default/38.sysrst_ctrl_smoke.1980563896 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:12 PM PST 24 |
2156391744 ps |
| T272 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect.4079927094 |
|
|
Mar 05 01:29:12 PM PST 24 |
Mar 05 01:31:02 PM PST 24 |
65048082713 ps |
| T595 |
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2827465190 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:32:47 PM PST 24 |
21581077796 ps |
| T596 |
/workspace/coverage/default/32.sysrst_ctrl_smoke.760080248 |
|
|
Mar 05 01:30:52 PM PST 24 |
Mar 05 01:30:58 PM PST 24 |
2109925314 ps |
| T597 |
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2031011288 |
|
|
Mar 05 01:31:41 PM PST 24 |
Mar 05 01:31:48 PM PST 24 |
2252927414 ps |
| T598 |
/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2686453096 |
|
|
Mar 05 01:30:22 PM PST 24 |
Mar 05 01:30:25 PM PST 24 |
2527108783 ps |
| T599 |
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2271693268 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:32:10 PM PST 24 |
22339207291 ps |
| T296 |
/workspace/coverage/default/0.sysrst_ctrl_sec_cm.760776119 |
|
|
Mar 05 01:28:54 PM PST 24 |
Mar 05 01:30:42 PM PST 24 |
42013468673 ps |
| T600 |
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3670060857 |
|
|
Mar 05 01:29:18 PM PST 24 |
Mar 05 01:29:24 PM PST 24 |
2009288888 ps |
| T81 |
/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2600759237 |
|
|
Mar 05 01:29:12 PM PST 24 |
Mar 05 01:30:35 PM PST 24 |
75140301115 ps |
| T601 |
/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.318451504 |
|
|
Mar 05 01:29:06 PM PST 24 |
Mar 05 01:29:08 PM PST 24 |
2537347719 ps |
| T602 |
/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3865053402 |
|
|
Mar 05 01:30:51 PM PST 24 |
Mar 05 01:30:57 PM PST 24 |
2061504422 ps |
| T232 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2806725027 |
|
|
Mar 05 01:30:17 PM PST 24 |
Mar 05 01:31:37 PM PST 24 |
60228677492 ps |
| T603 |
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3990063038 |
|
|
Mar 05 01:29:23 PM PST 24 |
Mar 05 01:29:27 PM PST 24 |
2621445525 ps |
| T604 |
/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2420250094 |
|
|
Mar 05 01:30:09 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
2521739295 ps |
| T605 |
/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.4120128354 |
|
|
Mar 05 01:29:03 PM PST 24 |
Mar 05 01:29:06 PM PST 24 |
3349125663 ps |
| T606 |
/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.644434074 |
|
|
Mar 05 01:30:59 PM PST 24 |
Mar 05 01:31:03 PM PST 24 |
2456540621 ps |
| T607 |
/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.24400248 |
|
|
Mar 05 01:30:40 PM PST 24 |
Mar 05 01:30:44 PM PST 24 |
2513635143 ps |
| T608 |
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2582248066 |
|
|
Mar 05 01:31:56 PM PST 24 |
Mar 05 01:32:01 PM PST 24 |
22920911650 ps |
| T182 |
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.362328590 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:30 PM PST 24 |
4958894010 ps |
| T609 |
/workspace/coverage/default/0.sysrst_ctrl_smoke.3877285372 |
|
|
Mar 05 01:28:56 PM PST 24 |
Mar 05 01:29:02 PM PST 24 |
2111522160 ps |
| T610 |
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2143998440 |
|
|
Mar 05 01:31:51 PM PST 24 |
Mar 05 01:32:09 PM PST 24 |
23857922702 ps |
| T611 |
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1915311955 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:32:21 PM PST 24 |
77469799255 ps |
| T612 |
/workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.2618067671 |
|
|
Mar 05 01:30:08 PM PST 24 |
Mar 05 01:30:10 PM PST 24 |
2531911308 ps |
| T613 |
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1906565523 |
|
|
Mar 05 01:32:23 PM PST 24 |
Mar 05 01:32:39 PM PST 24 |
23352889448 ps |
| T614 |
/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.100188653 |
|
|
Mar 05 01:30:27 PM PST 24 |
Mar 05 01:30:35 PM PST 24 |
8559184021 ps |
| T615 |
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3881669253 |
|
|
Mar 05 01:31:41 PM PST 24 |
Mar 05 01:31:44 PM PST 24 |
2494271248 ps |
| T616 |
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1735550979 |
|
|
Mar 05 01:29:13 PM PST 24 |
Mar 05 01:29:18 PM PST 24 |
2049447484 ps |
| T617 |
/workspace/coverage/default/22.sysrst_ctrl_edge_detect.2053846787 |
|
|
Mar 05 01:30:17 PM PST 24 |
Mar 05 01:30:21 PM PST 24 |
2860145510 ps |
| T618 |
/workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.4060140754 |
|
|
Mar 05 01:31:11 PM PST 24 |
Mar 05 01:32:19 PM PST 24 |
26183583866 ps |
| T356 |
/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2028348761 |
|
|
Mar 05 01:30:33 PM PST 24 |
Mar 05 01:30:43 PM PST 24 |
43036102612 ps |
| T619 |
/workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2388642158 |
|
|
Mar 05 01:30:27 PM PST 24 |
Mar 05 01:30:29 PM PST 24 |
2527661643 ps |
| T362 |
/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1769938760 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:26 PM PST 24 |
27105721474 ps |
| T620 |
/workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3241971599 |
|
|
Mar 05 01:29:42 PM PST 24 |
Mar 05 01:29:45 PM PST 24 |
2750105430 ps |
| T621 |
/workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.882163642 |
|
|
Mar 05 01:30:45 PM PST 24 |
Mar 05 01:30:52 PM PST 24 |
2609647681 ps |
| T622 |
/workspace/coverage/default/26.sysrst_ctrl_smoke.981740127 |
|
|
Mar 05 01:30:39 PM PST 24 |
Mar 05 01:30:41 PM PST 24 |
2132054482 ps |
| T623 |
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3398898264 |
|
|
Mar 05 01:31:26 PM PST 24 |
Mar 05 01:31:32 PM PST 24 |
2033577568 ps |
| T624 |
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2232508295 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:31:25 PM PST 24 |
2012322828 ps |
| T625 |
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3154951090 |
|
|
Mar 05 01:31:45 PM PST 24 |
Mar 05 01:31:53 PM PST 24 |
3522092131 ps |
| T626 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.4194849213 |
|
|
Mar 05 01:29:06 PM PST 24 |
Mar 05 01:29:10 PM PST 24 |
2402349406 ps |
| T627 |
/workspace/coverage/default/19.sysrst_ctrl_smoke.266272143 |
|
|
Mar 05 01:30:08 PM PST 24 |
Mar 05 01:30:14 PM PST 24 |
2108420452 ps |
| T628 |
/workspace/coverage/default/20.sysrst_ctrl_smoke.1863213996 |
|
|
Mar 05 01:30:08 PM PST 24 |
Mar 05 01:30:15 PM PST 24 |
2111911477 ps |
| T629 |
/workspace/coverage/default/32.sysrst_ctrl_combo_detect.1094643890 |
|
|
Mar 05 01:30:55 PM PST 24 |
Mar 05 01:31:47 PM PST 24 |
78961227760 ps |
| T630 |
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3752424181 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:31:51 PM PST 24 |
22261248734 ps |
| T366 |
/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.922423090 |
|
|
Mar 05 01:30:35 PM PST 24 |
Mar 05 01:32:07 PM PST 24 |
1000029935532 ps |
| T631 |
/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3147055196 |
|
|
Mar 05 01:30:44 PM PST 24 |
Mar 05 01:30:52 PM PST 24 |
2609384823 ps |
| T111 |
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4211911655 |
|
|
Mar 05 01:29:14 PM PST 24 |
Mar 05 01:29:23 PM PST 24 |
3167593452 ps |
| T632 |
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.918845617 |
|
|
Mar 05 01:31:40 PM PST 24 |
Mar 05 01:31:47 PM PST 24 |
2508463093 ps |
| T633 |
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3230890434 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:31:33 PM PST 24 |
2639556089 ps |
| T634 |
/workspace/coverage/default/33.sysrst_ctrl_smoke.1312408748 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:30:58 PM PST 24 |
2117959058 ps |
| T635 |
/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3450094098 |
|
|
Mar 05 01:30:38 PM PST 24 |
Mar 05 01:30:40 PM PST 24 |
2635531111 ps |
| T267 |
/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1659595997 |
|
|
Mar 05 01:30:01 PM PST 24 |
Mar 05 01:30:42 PM PST 24 |
93653460213 ps |
| T340 |
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3919000324 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:34:46 PM PST 24 |
78586400263 ps |
| T636 |
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3454827918 |
|
|
Mar 05 01:31:33 PM PST 24 |
Mar 05 01:31:39 PM PST 24 |
2015198147 ps |
| T637 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4044817754 |
|
|
Mar 05 01:29:03 PM PST 24 |
Mar 05 01:29:10 PM PST 24 |
2339921442 ps |
| T638 |
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3898314056 |
|
|
Mar 05 01:31:48 PM PST 24 |
Mar 05 01:32:56 PM PST 24 |
27333930473 ps |
| T639 |
/workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4268326297 |
|
|
Mar 05 01:29:45 PM PST 24 |
Mar 05 01:29:48 PM PST 24 |
2631988513 ps |
| T640 |
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3417725350 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:36 PM PST 24 |
2184390194 ps |
| T641 |
/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1331336052 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:12 PM PST 24 |
2635866561 ps |
| T642 |
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2257609855 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:31:36 PM PST 24 |
2180497497 ps |
| T367 |
/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3681843700 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:31:00 PM PST 24 |
197419466387 ps |
| T643 |
/workspace/coverage/default/2.sysrst_ctrl_alert_test.2947157767 |
|
|
Mar 05 01:29:13 PM PST 24 |
Mar 05 01:29:15 PM PST 24 |
2019935368 ps |
| T644 |
/workspace/coverage/default/29.sysrst_ctrl_smoke.1820732006 |
|
|
Mar 05 01:30:45 PM PST 24 |
Mar 05 01:30:48 PM PST 24 |
2119203987 ps |
| T358 |
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3336684408 |
|
|
Mar 05 01:31:42 PM PST 24 |
Mar 05 01:32:37 PM PST 24 |
73754175366 ps |
| T645 |
/workspace/coverage/default/3.sysrst_ctrl_edge_detect.2341142425 |
|
|
Mar 05 01:29:13 PM PST 24 |
Mar 05 01:29:16 PM PST 24 |
2645528003 ps |
| T646 |
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1166762560 |
|
|
Mar 05 01:29:23 PM PST 24 |
Mar 05 01:29:28 PM PST 24 |
2982296496 ps |
| T647 |
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.344635594 |
|
|
Mar 05 01:29:27 PM PST 24 |
Mar 05 01:29:32 PM PST 24 |
3329013470 ps |
| T78 |
/workspace/coverage/default/38.sysrst_ctrl_combo_detect.2615489756 |
|
|
Mar 05 01:31:13 PM PST 24 |
Mar 05 01:38:42 PM PST 24 |
178106392027 ps |
| T648 |
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.968647378 |
|
|
Mar 05 01:29:20 PM PST 24 |
Mar 05 01:29:24 PM PST 24 |
2512328707 ps |
| T649 |
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2599894833 |
|
|
Mar 05 01:31:16 PM PST 24 |
Mar 05 01:31:24 PM PST 24 |
7012633113 ps |
| T650 |
/workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2640540313 |
|
|
Mar 05 01:30:00 PM PST 24 |
Mar 05 01:30:04 PM PST 24 |
3817403261 ps |
| T365 |
/workspace/coverage/default/47.sysrst_ctrl_stress_all.3192215546 |
|
|
Mar 05 01:31:44 PM PST 24 |
Mar 05 01:36:16 PM PST 24 |
810168028844 ps |
| T651 |
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.441813439 |
|
|
Mar 05 01:31:35 PM PST 24 |
Mar 05 01:31:43 PM PST 24 |
3324467114 ps |
| T652 |
/workspace/coverage/default/27.sysrst_ctrl_combo_detect.2156956343 |
|
|
Mar 05 01:30:36 PM PST 24 |
Mar 05 01:32:24 PM PST 24 |
160096822185 ps |
| T653 |
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3767209172 |
|
|
Mar 05 01:31:22 PM PST 24 |
Mar 05 01:31:25 PM PST 24 |
8743942356 ps |
| T654 |
/workspace/coverage/default/36.sysrst_ctrl_stress_all.1746953122 |
|
|
Mar 05 01:31:08 PM PST 24 |
Mar 05 01:31:12 PM PST 24 |
8352869888 ps |
| T655 |
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3204662024 |
|
|
Mar 05 01:31:42 PM PST 24 |
Mar 05 01:31:45 PM PST 24 |
8841612812 ps |
| T112 |
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.1083104359 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:33:37 PM PST 24 |
56922473584 ps |
| T656 |
/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3883160630 |
|
|
Mar 05 01:30:27 PM PST 24 |
Mar 05 01:31:04 PM PST 24 |
26082624834 ps |
| T308 |
/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1210768030 |
|
|
Mar 05 01:29:43 PM PST 24 |
Mar 05 01:30:06 PM PST 24 |
9073580087 ps |
| T344 |
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1348613526 |
|
|
Mar 05 01:31:34 PM PST 24 |
Mar 05 01:36:44 PM PST 24 |
119480541818 ps |
| T292 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2301416609 |
|
|
Mar 05 01:30:09 PM PST 24 |
Mar 05 01:31:35 PM PST 24 |
35116268291 ps |
| T657 |
/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3632194570 |
|
|
Mar 05 01:30:37 PM PST 24 |
Mar 05 01:30:43 PM PST 24 |
2196389567 ps |
| T658 |
/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3593291433 |
|
|
Mar 05 01:31:11 PM PST 24 |
Mar 05 01:31:22 PM PST 24 |
4595382733 ps |
| T659 |
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1424460841 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:31:39 PM PST 24 |
2610405856 ps |
| T660 |
/workspace/coverage/default/20.sysrst_ctrl_edge_detect.2663093255 |
|
|
Mar 05 01:30:09 PM PST 24 |
Mar 05 01:30:14 PM PST 24 |
3094823001 ps |
| T661 |
/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1540458601 |
|
|
Mar 05 01:30:38 PM PST 24 |
Mar 05 01:30:41 PM PST 24 |
2470581428 ps |
| T662 |
/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3022837804 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:18 PM PST 24 |
2454015549 ps |
| T663 |
/workspace/coverage/default/25.sysrst_ctrl_stress_all.297640857 |
|
|
Mar 05 01:30:37 PM PST 24 |
Mar 05 01:30:47 PM PST 24 |
15903318596 ps |
| T664 |
/workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2626512099 |
|
|
Mar 05 01:29:41 PM PST 24 |
Mar 05 01:29:48 PM PST 24 |
2508569618 ps |
| T665 |
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.812493288 |
|
|
Mar 05 01:31:41 PM PST 24 |
Mar 05 01:31:43 PM PST 24 |
4161876298 ps |
| T666 |
/workspace/coverage/default/17.sysrst_ctrl_alert_test.1576776585 |
|
|
Mar 05 01:30:05 PM PST 24 |
Mar 05 01:30:11 PM PST 24 |
2012324706 ps |
| T667 |
/workspace/coverage/default/37.sysrst_ctrl_alert_test.2740947110 |
|
|
Mar 05 01:31:09 PM PST 24 |
Mar 05 01:31:11 PM PST 24 |
2031043966 ps |
| T668 |
/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1374505012 |
|
|
Mar 05 01:31:15 PM PST 24 |
Mar 05 01:32:04 PM PST 24 |
18223817803 ps |
| T669 |
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.313165450 |
|
|
Mar 05 01:29:21 PM PST 24 |
Mar 05 01:29:27 PM PST 24 |
2027010033 ps |
| T670 |
/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3936427266 |
|
|
Mar 05 01:30:45 PM PST 24 |
Mar 05 01:30:47 PM PST 24 |
2496658414 ps |
| T93 |
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1480577569 |
|
|
Mar 05 01:29:25 PM PST 24 |
Mar 05 01:31:34 PM PST 24 |
702630614857 ps |
| T671 |
/workspace/coverage/default/20.sysrst_ctrl_combo_detect.128101125 |
|
|
Mar 05 01:30:13 PM PST 24 |
Mar 05 01:36:46 PM PST 24 |
153059418785 ps |
| T672 |
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1453669841 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:30:55 PM PST 24 |
129838748078 ps |
| T190 |
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.906088899 |
|
|
Mar 05 01:31:45 PM PST 24 |
Mar 05 01:31:50 PM PST 24 |
5044625091 ps |
| T673 |
/workspace/coverage/default/12.sysrst_ctrl_smoke.3023819440 |
|
|
Mar 05 01:29:44 PM PST 24 |
Mar 05 01:29:46 PM PST 24 |
2139011931 ps |
| T674 |
/workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1696590006 |
|
|
Mar 05 01:29:43 PM PST 24 |
Mar 05 01:36:22 PM PST 24 |
166447637206 ps |
| T675 |
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.4031736698 |
|
|
Mar 05 01:31:52 PM PST 24 |
Mar 05 01:32:24 PM PST 24 |
50549891461 ps |
| T676 |
/workspace/coverage/default/47.sysrst_ctrl_alert_test.490217396 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:31:52 PM PST 24 |
2011850428 ps |
| T677 |
/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.4244079886 |
|
|
Mar 05 01:29:52 PM PST 24 |
Mar 05 01:29:56 PM PST 24 |
3712932376 ps |
| T678 |
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2233720349 |
|
|
Mar 05 01:29:25 PM PST 24 |
Mar 05 01:31:53 PM PST 24 |
56324119234 ps |
| T679 |
/workspace/coverage/default/24.sysrst_ctrl_stress_all.3567691822 |
|
|
Mar 05 01:30:27 PM PST 24 |
Mar 05 01:32:18 PM PST 24 |
43849572910 ps |
| T243 |
/workspace/coverage/default/1.sysrst_ctrl_edge_detect.1007955660 |
|
|
Mar 05 01:29:06 PM PST 24 |
Mar 05 01:29:08 PM PST 24 |
4983237119 ps |
| T170 |
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3228802300 |
|
|
Mar 05 01:31:23 PM PST 24 |
Mar 05 01:34:02 PM PST 24 |
253973785290 ps |
| T680 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1662757103 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:30:10 PM PST 24 |
56153144429 ps |
| T681 |
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3560450871 |
|
|
Mar 05 01:31:30 PM PST 24 |
Mar 05 01:31:38 PM PST 24 |
2451127838 ps |
| T682 |
/workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2618204152 |
|
|
Mar 05 01:31:02 PM PST 24 |
Mar 05 01:31:08 PM PST 24 |
3535299786 ps |
| T683 |
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2753421629 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:29:37 PM PST 24 |
6764309312 ps |
| T684 |
/workspace/coverage/default/32.sysrst_ctrl_edge_detect.321118330 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:31:15 PM PST 24 |
569970511888 ps |
| T685 |
/workspace/coverage/default/15.sysrst_ctrl_smoke.400223415 |
|
|
Mar 05 01:29:49 PM PST 24 |
Mar 05 01:29:56 PM PST 24 |
2111923982 ps |
| T686 |
/workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.53079747 |
|
|
Mar 05 01:30:11 PM PST 24 |
Mar 05 01:30:14 PM PST 24 |
5319898171 ps |
| T687 |
/workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.4210253132 |
|
|
Mar 05 01:29:02 PM PST 24 |
Mar 05 01:29:05 PM PST 24 |
8221354192 ps |
| T688 |
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2856024207 |
|
|
Mar 05 01:31:51 PM PST 24 |
Mar 05 01:34:14 PM PST 24 |
54643793717 ps |
| T689 |
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3707604583 |
|
|
Mar 05 01:31:16 PM PST 24 |
Mar 05 01:31:19 PM PST 24 |
2629457827 ps |
| T171 |
/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3933923339 |
|
|
Mar 05 01:29:53 PM PST 24 |
Mar 05 01:30:07 PM PST 24 |
6182661194 ps |
| T268 |
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3780810722 |
|
|
Mar 05 01:31:48 PM PST 24 |
Mar 05 01:32:54 PM PST 24 |
48464019923 ps |
| T338 |
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.529354610 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:30:28 PM PST 24 |
134935313995 ps |
| T690 |
/workspace/coverage/default/12.sysrst_ctrl_combo_detect.168461506 |
|
|
Mar 05 01:29:42 PM PST 24 |
Mar 05 01:36:28 PM PST 24 |
160338771082 ps |
| T691 |
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2901807349 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:33:34 PM PST 24 |
161312378491 ps |
| T692 |
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.4244022564 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:13 PM PST 24 |
2528985222 ps |
| T172 |
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.1301686606 |
|
|
Mar 05 01:29:23 PM PST 24 |
Mar 05 01:30:56 PM PST 24 |
101653176647 ps |
| T693 |
/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2613360618 |
|
|
Mar 05 01:30:12 PM PST 24 |
Mar 05 01:30:21 PM PST 24 |
3150483021 ps |
| T694 |
/workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1391491691 |
|
|
Mar 05 01:29:37 PM PST 24 |
Mar 05 01:29:42 PM PST 24 |
5191840386 ps |
| T695 |
/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2780087791 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:31:00 PM PST 24 |
2512151452 ps |
| T696 |
/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.912134712 |
|
|
Mar 05 01:30:38 PM PST 24 |
Mar 05 01:32:33 PM PST 24 |
88845938371 ps |
| T697 |
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.599124901 |
|
|
Mar 05 01:31:28 PM PST 24 |
Mar 05 01:31:32 PM PST 24 |
2624274334 ps |
| T698 |
/workspace/coverage/default/13.sysrst_ctrl_edge_detect.3743457628 |
|
|
Mar 05 01:29:53 PM PST 24 |
Mar 05 01:29:57 PM PST 24 |
4543541611 ps |
| T699 |
/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.4061919926 |
|
|
Mar 05 01:30:23 PM PST 24 |
Mar 05 01:30:28 PM PST 24 |
4699889855 ps |
| T700 |
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.4238385583 |
|
|
Mar 05 01:31:43 PM PST 24 |
Mar 05 01:32:06 PM PST 24 |
29097358114 ps |
| T701 |
/workspace/coverage/default/38.sysrst_ctrl_stress_all.2440858742 |
|
|
Mar 05 01:31:12 PM PST 24 |
Mar 05 01:31:30 PM PST 24 |
7075850611 ps |
| T702 |
/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.916628422 |
|
|
Mar 05 01:31:13 PM PST 24 |
Mar 05 01:31:16 PM PST 24 |
2479635916 ps |
| T703 |
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1839085860 |
|
|
Mar 05 01:29:14 PM PST 24 |
Mar 05 01:29:18 PM PST 24 |
3652386053 ps |
| T704 |
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.661305137 |
|
|
Mar 05 01:29:19 PM PST 24 |
Mar 05 01:29:22 PM PST 24 |
2531263590 ps |
| T705 |
/workspace/coverage/default/2.sysrst_ctrl_pin_access_test.1762123532 |
|
|
Mar 05 01:29:09 PM PST 24 |
Mar 05 01:29:11 PM PST 24 |
2208093857 ps |
| T244 |
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1732193835 |
|
|
Mar 05 01:31:42 PM PST 24 |
Mar 05 01:34:16 PM PST 24 |
64236570737 ps |
| T706 |
/workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2161428428 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:31:00 PM PST 24 |
2456408557 ps |
| T707 |
/workspace/coverage/default/30.sysrst_ctrl_alert_test.1907712568 |
|
|
Mar 05 01:30:54 PM PST 24 |
Mar 05 01:30:56 PM PST 24 |
2028458370 ps |
| T357 |
/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3822963285 |
|
|
Mar 05 01:31:16 PM PST 24 |
Mar 05 01:36:44 PM PST 24 |
118301874563 ps |
| T708 |
/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.569638759 |
|
|
Mar 05 01:31:04 PM PST 24 |
Mar 05 01:31:05 PM PST 24 |
2151651469 ps |
| T709 |
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3194868266 |
|
|
Mar 05 01:29:27 PM PST 24 |
Mar 05 01:29:30 PM PST 24 |
3437050649 ps |
| T710 |
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3947599198 |
|
|
Mar 05 01:31:47 PM PST 24 |
Mar 05 01:31:54 PM PST 24 |
28161437236 ps |
| T711 |
/workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.597368303 |
|
|
Mar 05 01:30:44 PM PST 24 |
Mar 05 01:30:48 PM PST 24 |
3239903457 ps |
| T712 |
/workspace/coverage/default/20.sysrst_ctrl_alert_test.3146533698 |
|
|
Mar 05 01:30:11 PM PST 24 |
Mar 05 01:30:14 PM PST 24 |
2031575555 ps |
| T713 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1799128939 |
|
|
Mar 05 01:29:19 PM PST 24 |
Mar 05 01:30:24 PM PST 24 |
23580179015 ps |
| T714 |
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.676721582 |
|
|
Mar 05 01:31:25 PM PST 24 |
Mar 05 01:31:32 PM PST 24 |
2456897819 ps |
| T715 |
/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1783585119 |
|
|
Mar 05 01:30:24 PM PST 24 |
Mar 05 01:30:27 PM PST 24 |
2524639497 ps |
| T716 |
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1308655880 |
|
|
Mar 05 01:31:23 PM PST 24 |
Mar 05 01:31:33 PM PST 24 |
6367970104 ps |
| T717 |
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.4293167534 |
|
|
Mar 05 01:31:27 PM PST 24 |
Mar 05 01:36:12 PM PST 24 |
119630457514 ps |
| T718 |
/workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1667099041 |
|
|
Mar 05 01:30:00 PM PST 24 |
Mar 05 01:30:09 PM PST 24 |
2611595897 ps |
| T719 |
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1493375427 |
|
|
Mar 05 01:31:18 PM PST 24 |
Mar 05 01:32:41 PM PST 24 |
33024377961 ps |
| T720 |
/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.289460712 |
|
|
Mar 05 01:31:12 PM PST 24 |
Mar 05 01:31:16 PM PST 24 |
2116445481 ps |
| T257 |
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3207400119 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:30:38 PM PST 24 |
87329398800 ps |
| T721 |
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3547174359 |
|
|
Mar 05 01:31:31 PM PST 24 |
Mar 05 01:31:39 PM PST 24 |
2511574844 ps |
| T722 |
/workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2997835817 |
|
|
Mar 05 01:30:27 PM PST 24 |
Mar 05 01:30:29 PM PST 24 |
2623265989 ps |
| T723 |
/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2546384806 |
|
|
Mar 05 01:30:43 PM PST 24 |
Mar 05 01:30:55 PM PST 24 |
8474148544 ps |
| T724 |
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3443126161 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:29:34 PM PST 24 |
2509080097 ps |
| T269 |
/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.1618457732 |
|
|
Mar 05 01:31:01 PM PST 24 |
Mar 05 01:33:08 PM PST 24 |
50274474227 ps |
| T725 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect.1427798587 |
|
|
Mar 05 01:29:12 PM PST 24 |
Mar 05 01:32:35 PM PST 24 |
75687925663 ps |
| T346 |
/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3351649872 |
|
|
Mar 05 01:30:07 PM PST 24 |
Mar 05 01:30:26 PM PST 24 |
122363105274 ps |
| T113 |
/workspace/coverage/default/35.sysrst_ctrl_combo_detect.140942562 |
|
|
Mar 05 01:31:04 PM PST 24 |
Mar 05 01:36:17 PM PST 24 |
114571389493 ps |
| T726 |
/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2319480782 |
|
|
Mar 05 01:30:03 PM PST 24 |
Mar 05 01:30:06 PM PST 24 |
4019768542 ps |
| T727 |
/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2072500023 |
|
|
Mar 05 01:29:59 PM PST 24 |
Mar 05 01:30:03 PM PST 24 |
2541269340 ps |
| T728 |
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.48253840 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:29:29 PM PST 24 |
3018204494 ps |
| T729 |
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2384746906 |
|
|
Mar 05 01:29:26 PM PST 24 |
Mar 05 01:29:34 PM PST 24 |
2443281126 ps |
| T730 |
/workspace/coverage/default/5.sysrst_ctrl_smoke.23885963 |
|
|
Mar 05 01:29:18 PM PST 24 |
Mar 05 01:29:24 PM PST 24 |
2111497186 ps |
| T731 |
/workspace/coverage/default/33.sysrst_ctrl_stress_all.2247938269 |
|
|
Mar 05 01:30:59 PM PST 24 |
Mar 05 01:31:04 PM PST 24 |
6597096899 ps |
| T732 |
/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1476392303 |
|
|
Mar 05 01:30:10 PM PST 24 |
Mar 05 01:30:13 PM PST 24 |
3581035319 ps |
| T733 |
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.891710908 |
|
|
Mar 05 01:29:37 PM PST 24 |
Mar 05 01:29:44 PM PST 24 |
3102154783 ps |
| T245 |
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.4289251652 |
|
|
Mar 05 01:31:25 PM PST 24 |
Mar 05 01:31:35 PM PST 24 |
3962836059 ps |
| T734 |
/workspace/coverage/default/11.sysrst_ctrl_alert_test.1214112564 |
|
|
Mar 05 01:29:43 PM PST 24 |
Mar 05 01:29:44 PM PST 24 |
2037858882 ps |
| T735 |
/workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.290987567 |
|
|
Mar 05 01:29:39 PM PST 24 |
Mar 05 01:29:43 PM PST 24 |
2615987784 ps |
| T736 |
/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.906853886 |
|
|
Mar 05 01:30:03 PM PST 24 |
Mar 05 01:30:07 PM PST 24 |
4902819492 ps |
| T737 |
/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2328946392 |
|
|
Mar 05 01:30:37 PM PST 24 |
Mar 05 01:30:38 PM PST 24 |
3774376407 ps |
| T738 |
/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2005521154 |
|
|
Mar 05 01:29:45 PM PST 24 |
Mar 05 01:29:47 PM PST 24 |
2075514199 ps |
| T739 |
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3460524451 |
|
|
Mar 05 01:29:15 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
2496212324 ps |
| T135 |
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2571672896 |
|
|
Mar 05 01:31:33 PM PST 24 |
Mar 05 01:32:32 PM PST 24 |
49876057241 ps |
| T740 |
/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2200786030 |
|
|
Mar 05 01:29:10 PM PST 24 |
Mar 05 01:29:17 PM PST 24 |
2219772766 ps |
| T741 |
/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1356543739 |
|
|
Mar 05 01:30:37 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
2184156534 ps |
| T742 |
/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3383892317 |
|
|
Mar 05 01:30:07 PM PST 24 |
Mar 05 01:30:27 PM PST 24 |
28849718217 ps |
| T94 |
/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4156161260 |
|
|
Mar 05 01:30:18 PM PST 24 |
Mar 05 01:30:57 PM PST 24 |
59438122698 ps |
| T743 |
/workspace/coverage/default/39.sysrst_ctrl_smoke.4199269727 |
|
|
Mar 05 01:31:13 PM PST 24 |
Mar 05 01:31:16 PM PST 24 |
2128217876 ps |
| T744 |
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1699311348 |
|
|
Mar 05 01:31:17 PM PST 24 |
Mar 05 01:31:20 PM PST 24 |
2052928774 ps |
| T745 |
/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2840059566 |
|
|
Mar 05 01:30:56 PM PST 24 |
Mar 05 01:31:04 PM PST 24 |
2612711536 ps |
| T746 |
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3573010983 |
|
|
Mar 05 01:31:22 PM PST 24 |
Mar 05 01:33:15 PM PST 24 |
40236512862 ps |
| T747 |
/workspace/coverage/default/27.sysrst_ctrl_alert_test.173287340 |
|
|
Mar 05 01:30:37 PM PST 24 |
Mar 05 01:30:40 PM PST 24 |
2014990479 ps |
| T748 |
/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2702966223 |
|
|
Mar 05 01:31:10 PM PST 24 |
Mar 05 01:31:19 PM PST 24 |
2611153527 ps |
| T266 |
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3840466480 |
|
|
Mar 05 01:31:52 PM PST 24 |
Mar 05 01:34:17 PM PST 24 |
116533102740 ps |
| T749 |
/workspace/coverage/default/27.sysrst_ctrl_stress_all.1620068372 |
|
|
Mar 05 01:30:42 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
6589954610 ps |
| T750 |
/workspace/coverage/default/47.sysrst_ctrl_smoke.3559687483 |
|
|
Mar 05 01:31:30 PM PST 24 |
Mar 05 01:31:34 PM PST 24 |
2115899129 ps |
| T751 |
/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1070883485 |
|
|
Mar 05 01:30:15 PM PST 24 |
Mar 05 01:30:18 PM PST 24 |
2028357545 ps |
| T752 |
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2556360769 |
|
|
Mar 05 01:31:46 PM PST 24 |
Mar 05 01:35:02 PM PST 24 |
78276551682 ps |
| T753 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1423360791 |
|
|
Mar 05 01:29:19 PM PST 24 |
Mar 05 01:30:47 PM PST 24 |
65440640435 ps |
| T754 |
/workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1208807362 |
|
|
Mar 05 01:29:17 PM PST 24 |
Mar 05 01:29:18 PM PST 24 |
8112119240 ps |
| T755 |
/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3473796548 |
|
|
Mar 05 01:31:04 PM PST 24 |
Mar 05 01:31:06 PM PST 24 |
2537383133 ps |
| T242 |
/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.517156255 |
|
|
Mar 05 01:30:46 PM PST 24 |
Mar 05 01:31:35 PM PST 24 |
71644889846 ps |
| T756 |
/workspace/coverage/default/21.sysrst_ctrl_alert_test.3906931715 |
|
|
Mar 05 01:30:18 PM PST 24 |
Mar 05 01:30:20 PM PST 24 |
2026460741 ps |
| T757 |
/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.734281902 |
|
|
Mar 05 01:29:35 PM PST 24 |
Mar 05 01:29:41 PM PST 24 |
2448142317 ps |
| T136 |
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2104459622 |
|
|
Mar 05 01:31:12 PM PST 24 |
Mar 05 01:33:16 PM PST 24 |
927060088400 ps |
| T758 |
/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1695943941 |
|
|
Mar 05 01:30:40 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
2612315132 ps |
| T309 |
/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.523711813 |
|
|
Mar 05 01:30:35 PM PST 24 |
Mar 05 01:31:22 PM PST 24 |
76420623658 ps |
| T759 |
/workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2815797372 |
|
|
Mar 05 01:31:02 PM PST 24 |
Mar 05 01:31:05 PM PST 24 |
7388884146 ps |
| T760 |
/workspace/coverage/default/16.sysrst_ctrl_stress_all.3391025541 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:07 PM PST 24 |
10555615615 ps |
| T761 |
/workspace/coverage/default/13.sysrst_ctrl_smoke.3757440223 |
|
|
Mar 05 01:29:43 PM PST 24 |
Mar 05 01:29:45 PM PST 24 |
2135511686 ps |
| T762 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2842860859 |
|
|
Mar 05 01:28:54 PM PST 24 |
Mar 05 01:28:57 PM PST 24 |
2354872095 ps |
| T763 |
/workspace/coverage/default/36.sysrst_ctrl_alert_test.2721127004 |
|
|
Mar 05 01:31:15 PM PST 24 |
Mar 05 01:31:21 PM PST 24 |
2014608693 ps |
| T764 |
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1384100634 |
|
|
Mar 05 01:29:18 PM PST 24 |
Mar 05 01:29:26 PM PST 24 |
3149750103 ps |
| T765 |
/workspace/coverage/default/25.sysrst_ctrl_alert_test.1836520201 |
|
|
Mar 05 01:30:40 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
2009218148 ps |
| T766 |
/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2298675711 |
|
|
Mar 05 01:30:10 PM PST 24 |
Mar 05 01:30:15 PM PST 24 |
2614060935 ps |
| T767 |
/workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2492676379 |
|
|
Mar 05 01:30:43 PM PST 24 |
Mar 05 01:30:45 PM PST 24 |
3154488337 ps |
| T768 |
/workspace/coverage/default/28.sysrst_ctrl_combo_detect.2377329930 |
|
|
Mar 05 01:30:46 PM PST 24 |
Mar 05 01:37:52 PM PST 24 |
164644836305 ps |
| T769 |
/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.87196436 |
|
|
Mar 05 01:30:09 PM PST 24 |
Mar 05 01:30:12 PM PST 24 |
2637746059 ps |
| T770 |
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3447611780 |
|
|
Mar 05 01:29:29 PM PST 24 |
Mar 05 01:29:31 PM PST 24 |
2037761435 ps |
| T771 |
/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.4014460703 |
|
|
Mar 05 01:30:10 PM PST 24 |
Mar 05 01:30:17 PM PST 24 |
2449539853 ps |
| T772 |
/workspace/coverage/default/15.sysrst_ctrl_edge_detect.760227775 |
|
|
Mar 05 01:30:00 PM PST 24 |
Mar 05 01:30:07 PM PST 24 |
4482152594 ps |
| T773 |
/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.28685354 |
|
|
Mar 05 01:30:42 PM PST 24 |
Mar 05 01:30:45 PM PST 24 |
2481433271 ps |
| T774 |
/workspace/coverage/default/13.sysrst_ctrl_combo_detect.2958948271 |
|
|
Mar 05 01:29:50 PM PST 24 |
Mar 05 01:30:09 PM PST 24 |
46810662130 ps |
| T775 |
/workspace/coverage/default/35.sysrst_ctrl_smoke.2333169610 |
|
|
Mar 05 01:31:03 PM PST 24 |
Mar 05 01:31:10 PM PST 24 |
2109756976 ps |
| T246 |
/workspace/coverage/default/34.sysrst_ctrl_edge_detect.1440332942 |
|
|
Mar 05 01:31:03 PM PST 24 |
Mar 05 01:31:15 PM PST 24 |
5177255525 ps |
| T776 |
/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1002519562 |
|
|
Mar 05 01:29:45 PM PST 24 |
Mar 05 01:29:55 PM PST 24 |
3224282475 ps |
| T777 |
/workspace/coverage/default/26.sysrst_ctrl_alert_test.1092036008 |
|
|
Mar 05 01:30:35 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
2021420501 ps |
| T778 |
/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3938816641 |
|
|
Mar 05 01:30:16 PM PST 24 |
Mar 05 01:30:23 PM PST 24 |
2511683527 ps |
| T779 |
/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3979066155 |
|
|
Mar 05 01:31:12 PM PST 24 |
Mar 05 01:32:09 PM PST 24 |
427456225638 ps |
| T780 |
/workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3610916959 |
|
|
Mar 05 01:30:53 PM PST 24 |
Mar 05 01:31:02 PM PST 24 |
2704644070 ps |
| T781 |
/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2921077650 |
|
|
Mar 05 01:30:43 PM PST 24 |
Mar 05 01:30:46 PM PST 24 |
3437597521 ps |
| T204 |
/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3443728259 |
|
|
Mar 05 01:29:52 PM PST 24 |
Mar 05 01:30:39 PM PST 24 |
66338644687 ps |
| T137 |
/workspace/coverage/default/12.sysrst_ctrl_stress_all.185660436 |
|
|
Mar 05 01:29:41 PM PST 24 |
Mar 05 01:29:57 PM PST 24 |
15094623968 ps |
| T114 |
/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2276571231 |
|
|
Mar 05 01:29:21 PM PST 24 |
Mar 05 01:31:50 PM PST 24 |
112959146701 ps |
| T89 |
/workspace/coverage/default/35.sysrst_ctrl_stress_all.3047757370 |
|
|
Mar 05 01:31:03 PM PST 24 |
Mar 05 01:31:09 PM PST 24 |
12613537660 ps |
| T782 |
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3905631096 |
|
|
Mar 05 01:31:24 PM PST 24 |
Mar 05 01:31:30 PM PST 24 |
2482822480 ps |
| T783 |
/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1766404536 |
|
|
Mar 05 01:29:44 PM PST 24 |
Mar 05 01:29:51 PM PST 24 |
2455316974 ps |
| T363 |
/workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2420448435 |
|
|
Mar 05 01:30:16 PM PST 24 |
Mar 05 01:30:42 PM PST 24 |
37440446568 ps |
| T784 |
/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2672253479 |
|
|
Mar 05 01:29:36 PM PST 24 |
Mar 05 01:29:39 PM PST 24 |
2622788899 ps |
| T785 |
/workspace/coverage/default/25.sysrst_ctrl_edge_detect.24471745 |
|
|
Mar 05 01:30:33 PM PST 24 |
Mar 05 01:30:40 PM PST 24 |
3527252644 ps |
| T138 |
/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1986932922 |
|
|
Mar 05 01:30:10 PM PST 24 |
Mar 05 01:32:48 PM PST 24 |
1203324411390 ps |
| T786 |
/workspace/coverage/default/15.sysrst_ctrl_alert_test.2164711687 |
|
|
Mar 05 01:30:02 PM PST 24 |
Mar 05 01:30:06 PM PST 24 |
2038441705 ps |
| T787 |
/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3544579399 |
|
|
Mar 05 01:30:30 PM PST 24 |
Mar 05 01:30:33 PM PST 24 |
2123394346 ps |
| T788 |
/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2383487788 |
|
|
Mar 05 01:29:53 PM PST 24 |
Mar 05 01:30:00 PM PST 24 |
2512866549 ps |
| T789 |
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3475918920 |
|
|
Mar 05 01:31:21 PM PST 24 |
Mar 05 01:31:23 PM PST 24 |
4969816423 ps |
| T790 |
/workspace/coverage/default/22.sysrst_ctrl_alert_test.1708216654 |
|
|
Mar 05 01:30:18 PM PST 24 |
Mar 05 01:30:24 PM PST 24 |
2012193007 ps |
| T791 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect.3918884376 |
|
|
Mar 05 01:29:11 PM PST 24 |
Mar 05 01:29:19 PM PST 24 |
24493779601 ps |
| T792 |
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.443156797 |
|
|
Mar 05 12:41:08 PM PST 24 |
Mar 05 12:41:14 PM PST 24 |
2010475148 ps |