Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1989

1

T1

18

T26

4

T3

10

auto[1]

641

1

T1

6

T26

2

T3

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2028

1

T1

18

T3

12

T8

3

auto[1]

602

1

T1

6

T26

6

T3

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2073

1

T1

24

T26

2

T3

12

auto[1]

557

1

T26

4

T3

4

T8

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1946

1

T1

24

T26

2

T3

14

auto[1]

684

1

T26

4

T3

2

T8

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2456

1

T1

24

T26

6

T3

16

auto[1]

174

1

T38

3

T15

4

T118

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2386

1

T1

24

T26

6

T3

14

auto[1]

244

1

T3

2

T69

10

T118

9

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2282

1

T1

18

T26

6

T3

14

auto[1]

348

1

T1

6

T3

2

T38

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2423

1

T1

18

T26

6

T3

12

auto[1]

207

1

T1

6

T3

4

T80

10

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2341

1

T1

24

T26

6

T3

10

auto[1]

289

1

T3

6

T118

21

T80

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1995

1

T1

24

T26

6

T3

16

auto[1]

635

1

T8

3

T9

7

T10

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

895

1

T26

6

T8

13

T9

9

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

72

1

T15

4

T236

2

T237

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

111

1

T118

12

T167

2

T89

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T354

3

T355

2

-

-

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

76

1

T356

4

T357

1

T358

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T359

4

T360

2

T361

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T3

4

T362

5

T360

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

96

1

T69

13

T118

11

T120

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T38

3

T118

4

T236

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T89

1

T356

2

T363

15

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T238

1

T364

4

T365

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

17

1

T1

6

T366

1

T364

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

22

1

T80

6

T363

10

T367

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

56

1

T238

6

T89

3

T357

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T354

1

T238

5

T368

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

9

1

T369

1

T370

4

T371

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T345

1

T372

1

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

10

1

T120

3

T373

1

T365

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T359

3

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T374

3

T375

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T69

10

T80

8

T376

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T339

6

T364

5

T377

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T3

2

T118

9

T367

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T378

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T80

4

T359

3

T276

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T367

4

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

185

1

T69

10

T118

12

T241

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

101

1

T11

9

T16

12

T80

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

59

1

T8

3

T9

4

T80

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

125

1

T58

9

T118

9

T354

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

86

1

T3

2

T11

6

T13

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

86

1

T13

1

T15

4

T69

13

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T243

1

T379

3

T101

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60

1

T96

7

T238

6

T345

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

41

1

T13

2

T59

4

T100

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

126

1

T9

1

T16

8

T96

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T9

2

T120

3

T344

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

64

1

T354

1

T334

1

T306

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T97

3

T95

3

T59

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T335

3

T244

3

T365

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T135

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

223

1

T13

1

T289

11

T100

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

41

1

T1

6

T26

2

T80

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T380

4

T357

1

T358

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T94

1

T97

2

T155

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T8

4

T118

11

T59

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T156

2

T168

4

T81

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

29

1

T10

1

T38

3

T58

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T59

2

T381

1

T219

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T8

6

T168

5

T91

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T3

4

T9

2

T382

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T95

2

T237

2

T383

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T94

1

T81

6

T243

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T26

4

T156

3

T167

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T335

2

T381

1

T344

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T156

2

T168

1

T250

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T96

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded