Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T8

10

T9

21

T13

16

auto[1]

1116

1

T8

10

T9

15

T13

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T8

7

T9

7

T13

9

from_0to1

523

1

T8

6

T9

7

T13

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T8

11

T9

18

T13

27

auto[1]

1037

1

T8

9

T9

18

T13

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T8

6

T9

17

T13

19

auto[1]

1121

1

T8

14

T9

19

T13

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T9

1

T313

1

T398

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T8

2

T13

2

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T9

3

T13

1

T313

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T8

1

T9

1

T13

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T9

1

T13

3

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T8

1

T13

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T8

1

T73

2

T157

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T8

1

T9

1

T13

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T13

2

T73

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T8

2

T9

1

T13

2

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T9

1

T13

1

T19

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T8

2

T73

2

T21

3

auto[1]

from_0to1

auto[0]

auto[0]

88

1

T8

2

T9

1

T13

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T8

1

T9

3

T13

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T13

1

T73

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T9

1

T73

1

T19

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T8

10

T9

18

T13

15

auto[1]

1073

1

T8

10

T9

18

T13

25

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T8

6

T9

8

T13

9

from_0to1

527

1

T8

5

T9

7

T13

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T8

11

T9

24

T13

21

auto[1]

1073

1

T8

9

T9

12

T13

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T8

10

T9

19

T13

21

auto[1]

1114

1

T8

10

T9

17

T13

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T9

2

T13

1

T73

3

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T8

1

T9

1

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T8

1

T9

2

T13

2

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T13

1

T19

3

T157

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T9

1

T13

2

T313

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T9

1

T13

1

T73

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T8

3

T13

1

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T19

1

T21

1

T157

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T8

1

T9

1

T19

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T8

1

T13

2

T297

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T8

1

T9

2

T13

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T8

1

T13

2

T21

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T9

2

T13

2

T159

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T8

2

T9

3

T73

2

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T13

2

T73

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T13

1

T19

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T8

10

T9

20

T13

25

auto[1]

1108

1

T8

10

T9

16

T13

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T8

7

T9

11

T13

12

from_0to1

535

1

T8

8

T9

10

T13

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T8

11

T9

19

T13

21

auto[1]

1091

1

T8

9

T9

17

T13

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T8

8

T9

21

T13

23

auto[1]

1106

1

T8

12

T9

15

T13

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T9

4

T13

4

T19

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T8

1

T73

1

T19

2

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T8

1

T9

2

T13

3

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T8

1

T13

2

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T13

1

T157

1

T159

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T8

1

T13

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T8

1

T9

2

T13

3

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T8

1

T9

2

T13

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T8

1

T9

1

T13

2

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T8

1

T9

2

T157

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T8

1

T9

1

T313

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T8

1

T9

1

T13

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T8

1

T9

1

T13

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T8

3

T9

3

T13

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T8

1

T9

2

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T13

3

T19

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T8

13

T9

16

T13

24

auto[1]

1111

1

T8

7

T9

20

T13

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

536

1

T8

7

T9

10

T13

6

from_0to1

539

1

T8

7

T9

10

T13

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T8

14

T9

20

T13

20

auto[1]

1072

1

T8

6

T9

16

T13

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T8

13

T9

19

T13

23

auto[1]

1081

1

T8

7

T9

17

T13

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T8

3

T9

1

T19

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T8

2

T9

1

T159

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T19

3

T313

2

T297

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T13

2

T73

1

T19

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T8

1

T9

2

T13

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T8

2

T13

1

T19

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T8

1

T9

2

T13

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T8

1

T9

1

T73

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T8

2

T9

1

T13

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T9

2

T13

3

T73

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T9

3

T73

1

T21

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T9

2

T19

2

T313

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T8

1

T9

1

T13

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T9

3

T19

3

T159

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T9

1

T13

2

T73

3

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T8

1

T13

1

T73

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T8

9

T9

13

T13

18

auto[1]

1150

1

T8

11

T9

23

T13

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T8

7

T9

9

T13

10

from_0to1

534

1

T8

7

T9

8

T13

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T8

12

T9

17

T13

16

auto[1]

1060

1

T8

8

T9

19

T13

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T8

11

T9

20

T13

17

auto[1]

1081

1

T8

9

T9

16

T13

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T8

2

T9

3

T73

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T19

1

T313

3

T157

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T13

2

T73

1

T313

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T9

1

T73

2

T19

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T9

1

T13

1

T73

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T8

2

T9

2

T13

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T8

2

T13

1

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T13

3

T313

2

T157

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T8

2

T9

1

T13

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T8

1

T9

2

T13

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T8

2

T9

1

T13

3

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T9

1

T13

3

T19

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T9

1

T13

1

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T8

1

T9

1

T13

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T8

1

T9

1

T73

2

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T8

1

T9

2

T13

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T8

13

T9

22

T13

18

auto[1]

1097

1

T8

7

T9

14

T13

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

517

1

T8

6

T9

10

T13

9

from_0to1

522

1

T8

6

T9

9

T13

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T8

7

T9

14

T13

20

auto[1]

1152

1

T8

13

T9

22

T13

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T8

8

T9

19

T13

19

auto[1]

1098

1

T8

12

T9

17

T13

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T9

3

T13

1

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T13

1

T73

1

T19

3

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T8

2

T13

1

T19

4

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T8

3

T9

1

T13

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T9

4

T73

2

T19

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T8

2

T19

3

T157

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T8

1

T9

3

T13

3

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T8

1

T9

1

T19

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T9

1

T73

1

T157

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T9

1

T13

2

T73

3

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T9

3

T13

1

T73

2

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T8

1

T9

1

T13

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T13

2

T73

1

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T8

1

T9

1

T13

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T8

1

T13

1

T73

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T13

1

T73

2

T19

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T8

10

T9

23

T13

21

auto[1]

1082

1

T8

10

T9

13

T13

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T8

6

T9

8

T13

10

from_0to1

531

1

T8

7

T9

7

T13

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T8

13

T9

21

T13

15

auto[1]

1126

1

T8

7

T9

15

T13

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T8

13

T9

20

T13

21

auto[1]

1127

1

T8

7

T9

16

T13

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T8

1

T9

1

T19

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T9

2

T73

1

T313

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T9

1

T13

4

T19

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T8

1

T9

1

T13

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T8

2

T9

2

T13

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T8

1

T13

2

T19

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T8

1

T73

1

T19

3

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T9

2

T13

1

T19

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T8

3

T9

1

T13

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T73

2

T19

1

T21

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T8

1

T9

1

T13

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T9

1

T13

2

T313

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T8

1

T9

1

T13

2

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T8

1

T9

1

T73

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T13

2

T73

2

T313

2

auto[1]

from_0to1

auto[1]

auto[1]

80

1

T8

1

T9

1

T13

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T8

12

T9

19

T13

19

auto[1]

1120

1

T8

8

T9

17

T13

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

534

1

T8

4

T9

10

T13

10

from_0to1

528

1

T8

4

T9

9

T13

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T8

12

T9

18

T13

20

auto[1]

1100

1

T8

8

T9

18

T13

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T8

14

T9

14

T13

19

auto[1]

1077

1

T8

6

T9

22

T13

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

87

1

T9

3

T73

1

T19

2

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T9

1

T73

1

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T9

1

T13

1

T73

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T8

1

T9

1

T13

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T8

3

T9

1

T13

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T19

1

T157

1

T159

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T13

1

T398

3

T399

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T9

4

T13

2

T73

2

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T8

1

T13

1

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T8

1

T9

2

T13

3

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T8

1

T9

1

T19

2

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T9

1

T13

3

T19

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T9

1

T13

2

T73

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T8

1

T9

2

T13

2

auto[1]

from_0to1

auto[1]

auto[0]

82

1

T13

1

T73

2

T19

3

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T9

1

T19

1

T21

1