Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122838

1

T4

3

T5

2

T6

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146574	1			T4	3		T5	3		T6	2
values[0x0]	67218	1			T4	1		T5	1		T6	25
values[0x1]	67091	1			T4	1		T5	2		T6	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152773

1

T4

3

T5

3

T6

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	936	1			T54	4		T1	21		T3	1
valid_sources[0x01]	1920	1			T55	1		T32	1		T8	8
valid_sources[0x02]	1091	1			T43	1		T46	1		T3	7
valid_sources[0x03]	2425	1			T55	2		T54	1		T3	18
valid_sources[0x04]	743	1			T72	3		T56	1		T1	10
valid_sources[0x05]	2713	1			T46	1		T55	2		T54	5
valid_sources[0x06]	1811	1			T54	1		T1	32		T3	5
valid_sources[0x07]	1137	1			T46	2		T56	1		T3	4
valid_sources[0x08]	2706	1			T54	6		T57	4		T3	2
valid_sources[0x09]	947	1			T55	2		T54	2		T56	1
valid_sources[0x0a]	1102	1			T48	1		T54	7		T3	3
valid_sources[0x0b]	2191	1			T55	1		T54	1		T3	9
valid_sources[0x0c]	997	1			T54	2		T56	1		T3	11
valid_sources[0x0d]	840	1			T54	2		T3	8		T8	1
valid_sources[0x0e]	842	1			T1	25		T8	10		T10	5
valid_sources[0x0f]	1119	1			T55	1		T56	2		T3	1
valid_sources[0x10]	1051	1			T54	2		T32	1		T33	1
valid_sources[0x11]	1129	1			T55	1		T54	3		T3	4
valid_sources[0x12]	1076	1			T54	3		T3	1		T29	1
valid_sources[0x13]	901	1			T56	2		T3	6		T32	3
valid_sources[0x14]	1436	1			T55	1		T54	1		T1	13
valid_sources[0x15]	1073	1			T54	1		T1	19		T3	1
valid_sources[0x16]	818	1			T56	1		T3	1		T32	3
valid_sources[0x17]	1015	1			T54	3		T1	33		T3	2
valid_sources[0x18]	867	1			T54	1		T29	1		T32	2
valid_sources[0x19]	1109	1			T54	1		T3	1		T8	2
valid_sources[0x1a]	927	1			T54	3		T3	2		T27	2
valid_sources[0x1b]	1183	1			T46	4		T1	11		T3	4
valid_sources[0x1c]	908	1			T54	2		T3	3		T32	4
valid_sources[0x1d]	1452	1			T54	1		T56	2		T1	24
valid_sources[0x1e]	1190	1			T54	1		T3	4		T8	7
valid_sources[0x1f]	951	1			T55	1		T54	3		T56	1
valid_sources[0x20]	1092	1			T54	3		T1	42		T3	6
valid_sources[0x21]	1111	1			T42	2		T1	14		T3	1
valid_sources[0x22]	877	1			T54	6		T3	11		T8	4
valid_sources[0x23]	1066	1			T54	1		T3	1		T32	2
valid_sources[0x24]	1364	1			T54	2		T1	12		T3	8
valid_sources[0x25]	1070	1			T54	3		T1	13		T8	1
valid_sources[0x26]	1167	1			T54	3		T3	9		T8	5
valid_sources[0x27]	1732	1			T48	1		T54	1		T56	1
valid_sources[0x28]	998	1			T45	1		T3	3		T8	2
valid_sources[0x29]	1050	1			T54	1		T1	5		T29	1
valid_sources[0x2a]	897	1			T72	1		T54	3		T27	4
valid_sources[0x2b]	827	1			T54	2		T3	1		T28	8
valid_sources[0x2c]	1376	1			T46	7		T54	4		T32	8
valid_sources[0x2d]	1004	1			T54	4		T8	1		T36	1
valid_sources[0x2e]	977	1			T55	2		T54	4		T3	2
valid_sources[0x2f]	783	1			T45	2		T48	1		T54	2
valid_sources[0x30]	871	1			T1	9		T29	1		T8	6
valid_sources[0x31]	964	1			T55	4		T54	2		T1	23
valid_sources[0x32]	1325	1			T54	3		T8	6		T11	4
valid_sources[0x33]	754	1			T54	5		T3	5		T28	11
valid_sources[0x34]	1135	1			T72	1		T54	3		T3	1
valid_sources[0x35]	822	1			T54	1		T1	25		T27	1
valid_sources[0x36]	1090	1			T55	1		T54	1		T56	1
valid_sources[0x37]	1075	1			T54	3		T3	5		T29	1
valid_sources[0x38]	854	1			T54	1		T3	12		T29	1
valid_sources[0x39]	1312	1			T54	3		T57	1		T1	19
valid_sources[0x3a]	991	1			T1	1		T3	9		T32	2
valid_sources[0x3b]	904	1			T55	2		T54	2		T1	8
valid_sources[0x3c]	856	1			T55	1		T54	1		T1	2
valid_sources[0x3d]	1269	1			T54	3		T3	2		T8	6
valid_sources[0x3e]	859	1			T3	1		T8	1		T66	1
valid_sources[0x3f]	2106	1			T54	3		T32	2		T8	3
valid_sources[0x40]	1515	1			T3	11		T29	1		T32	1
valid_sources[0x41]	961	1			T54	2		T1	2		T2	2
valid_sources[0x42]	839	1			T55	1		T72	1		T1	7
valid_sources[0x43]	1196	1			T54	2		T32	3		T8	2
valid_sources[0x44]	1035	1			T54	3		T3	4		T32	4
valid_sources[0x45]	1168	1			T54	4		T3	2		T32	6
valid_sources[0x46]	784	1			T72	2		T54	2		T1	1
valid_sources[0x47]	816	1			T54	2		T3	5		T31	1
valid_sources[0x48]	945	1			T3	4		T27	3		T8	3
valid_sources[0x49]	1340	1			T54	1		T2	1		T3	2
valid_sources[0x4a]	1334	1			T54	2		T56	2		T1	31
valid_sources[0x4b]	904	1			T54	1		T8	3		T66	1
valid_sources[0x4c]	1138	1			T71	4		T54	1		T3	13
valid_sources[0x4d]	855	1			T55	1		T54	1		T1	2
valid_sources[0x4e]	878	1			T54	3		T8	6		T66	1
valid_sources[0x4f]	837	1			T72	3		T57	5		T29	1
valid_sources[0x50]	1853	1			T54	1		T3	2		T8	4
valid_sources[0x51]	1825	1			T54	1		T56	3		T3	4
valid_sources[0x52]	966	1			T55	1		T54	4		T28	5
valid_sources[0x53]	1266	1			T54	1		T29	3		T32	1
valid_sources[0x54]	848	1			T72	1		T54	2		T1	3
valid_sources[0x55]	964	1			T54	2		T3	2		T29	1
valid_sources[0x56]	889	1			T54	3		T1	22		T3	2
valid_sources[0x57]	862	1			T46	1		T54	2		T3	1
valid_sources[0x58]	860	1			T47	2		T56	2		T3	2
valid_sources[0x59]	1212	1			T72	1		T54	2		T29	1
valid_sources[0x5a]	1313	1			T43	1		T1	4		T3	10
valid_sources[0x5b]	1505	1			T3	2		T30	62		T32	2
valid_sources[0x5c]	989	1			T55	1		T72	1		T54	2
valid_sources[0x5d]	831	1			T54	1		T2	1		T3	1
valid_sources[0x5e]	1719	1			T5	3		T72	1		T56	1
valid_sources[0x5f]	1034	1			T54	3		T32	1		T8	4
valid_sources[0x60]	1090	1			T54	3		T56	1		T3	4
valid_sources[0x61]	980	1			T54	1		T28	6		T29	1
valid_sources[0x62]	905	1			T54	1		T56	1		T3	2
valid_sources[0x63]	844	1			T54	2		T1	10		T3	4
valid_sources[0x64]	958	1			T48	1		T54	1		T56	2
valid_sources[0x65]	1227	1			T54	3		T3	3		T8	4
valid_sources[0x66]	853	1			T55	1		T54	2		T25	1
valid_sources[0x67]	1386	1			T55	2		T54	2		T56	2
valid_sources[0x68]	826	1			T54	4		T1	6		T3	4
valid_sources[0x69]	876	1			T54	1		T1	26		T8	2
valid_sources[0x6a]	947	1			T72	1		T56	3		T3	4
valid_sources[0x6b]	977	1			T54	2		T1	5		T8	3
valid_sources[0x6c]	1044	1			T54	3		T1	11		T3	9
valid_sources[0x6d]	970	1			T1	9		T8	2		T66	2
valid_sources[0x6e]	1275	1			T55	2		T54	3		T1	47
valid_sources[0x6f]	803	1			T54	2		T1	1		T3	1
valid_sources[0x70]	1179	1			T45	1		T54	2		T3	3
valid_sources[0x71]	1119	1			T44	1		T55	1		T54	2
valid_sources[0x72]	1887	1			T1	2		T3	2		T31	2
valid_sources[0x73]	719	1			T45	1		T1	1		T8	3
valid_sources[0x74]	929	1			T54	1		T56	1		T1	10
valid_sources[0x75]	979	1			T48	1		T3	3		T29	1
valid_sources[0x76]	1009	1			T54	4		T3	1		T8	2
valid_sources[0x77]	1309	1			T54	1		T3	4		T8	4
valid_sources[0x78]	891	1			T54	1		T3	5		T8	3
valid_sources[0x79]	1321	1			T54	1		T3	3		T8	5
valid_sources[0x7a]	1631	1			T54	1		T8	1		T11	3
valid_sources[0x7b]	1169	1			T46	7		T54	1		T56	1
valid_sources[0x7c]	889	1			T47	1		T54	1		T3	4
valid_sources[0x7d]	1021	1			T54	3		T3	1		T29	1
valid_sources[0x7e]	920	1			T4	5		T1	30		T3	2
valid_sources[0x7f]	882	1			T1	11		T32	3		T8	4
valid_sources[0x80]	897	1			T32	6		T8	2		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66893

1

T4

3

T6

2

T42

1

values[0x0]

all_enables

biggest_size

32894

1

T6

10

T46

6

T48

3

values[0x1]

all_enables

biggest_size

23051

1

T5

2

T6

2

T71

1