Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T48,T32,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T48,T32,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T48,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T48,T32,T9
1	0	Covered	T6,T42,T43
1	1	Covered	T48,T32,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T48,T9,T10
0	1	Covered	T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T48,T9,T10
0	1	Covered	T48,T9,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T48,T9,T10
1	-	Covered	T48,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T48,T32,T9
DetectSt	168	Covered	T48,T9,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T48,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T48,T9,T10
DebounceSt->IdleSt	163	Covered	T48,T32,T67
DetectSt->IdleSt	186	Covered	T106
DetectSt->StableSt	191	Covered	T48,T9,T10
IdleSt->DebounceSt	148	Covered	T48,T32,T9
StableSt->IdleSt	206	Covered	T48,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T48,T32,T9
0	1	Covered	T48,T32,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T48,T9,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T48,T32,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T48,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T67,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T48,T32,T9
DetectSt	-	-	-	-	1	-	-	Covered	T106
DetectSt	-	-	-	-	0	1	-	Covered	T48,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T48,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	259	0	0
CntIncr_A	7872393	226432	0	0
CntNoWrap_A	7872393	7182402	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	737	0	0
DetectedPulseOut_A	7872393	117	0	0
DisabledIdleSt_A	7872393	6950181	0	0
DisabledNoDetection_A	7872393	6952599	0	0
EnterDebounceSt_A	7872393	142	0	0
EnterDetectSt_A	7872393	118	0	0
EnterStableSt_A	7872393	117	0	0
PulseIsPulse_A	7872393	117	0	0
StayInStableSt	7872393	620	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	7050	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	117	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	259	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	2	0	0
T10	0	4	0	0
T13	0	2	0	0
T19	0	3	0	0
T25	421	0	0	0
T32	0	1	0	0
T48	608	4	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	3	0	0
T68	0	2	0	0
T70	0	6	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	226432	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	27	0	0
T10	0	107	0	0
T13	0	79	0	0
T19	0	95	0	0
T25	421	0	0	0
T32	0	19	0	0
T48	608	111	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	121	0	0
T68	0	23	0	0
T70	0	79	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	159	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182402	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	203	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T86	27280	0	0	0
T106	17993	1	0	0
T110	527	0	0	0
T111	734	0	0	0
T112	403	0	0	0
T113	1128	0	0	0
T114	2709	0	0	0
T115	12391	0	0	0
T116	1040	0	0	0
T117	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	737	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	4	0	0
T10	0	4	0	0
T13	0	3	0	0
T19	0	3	0	0
T25	421	0	0	0
T48	608	5	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	3	0	0
T68	0	11	0	0
T70	0	26	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	7	0	0
T119	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	117	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T19	0	1	0	0
T25	421	0	0	0
T48	608	1	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	3	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	2	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6950181	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6952599	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	142	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T19	0	2	0	0
T25	421	0	0	0
T32	0	1	0	0
T48	608	3	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	3	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	118	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T19	0	1	0	0
T25	421	0	0	0
T48	608	1	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	3	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	2	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	117	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T19	0	1	0	0
T25	421	0	0	0
T48	608	1	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	3	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	2	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	117	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T19	0	1	0	0
T25	421	0	0	0
T48	608	1	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	3	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	2	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	620	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	3	0	0
T10	0	2	0	0
T13	0	2	0	0
T19	0	2	0	0
T25	421	0	0	0
T48	608	4	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	2	0	0
T68	0	10	0	0
T70	0	23	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	5	0	0
T119	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7050	0	0
T6	522	4	0	0
T42	427	2	0	0
T43	431	3	0	0
T44	569	0	0	0
T45	1016	4	0	0
T46	2176	17	0	0
T47	423	1	0	0
T48	608	3	0	0
T54	0	27	0	0
T55	498	6	0	0
T71	716	0	0	0
T72	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	117	0	0
T1	20302	0	0	0
T2	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	0	1	0	0
T19	0	1	0	0
T25	421	0	0	0
T48	608	1	0	0
T54	4766	0	0	0
T55	498	0	0	0
T56	522	0	0	0
T57	745	0	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	3	0	0
T71	716	0	0	0
T72	437	0	0	0
T95	0	2	0	0
T119	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T7,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T32,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T12
0	1	Covered	T7,T81,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T12
0	1	Unreachable
1	0	Covered	T7,T8,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T7,T8
DetectSt	168	Covered	T7,T8,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T12
DebounceSt->IdleSt	163	Covered	T32,T9,T60
DetectSt->IdleSt	186	Covered	T7,T81,T93
DetectSt->StableSt	191	Covered	T7,T8,T12
IdleSt->DebounceSt	148	Covered	T32,T7,T8
StableSt->IdleSt	206	Covered	T7,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T7,T8
0	1	Covered	T32,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T122,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T7,T81,T93
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T12
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	135	0	0
CntIncr_A	7872393	187818	0	0
CntNoWrap_A	7872393	7182526	0	0
DetectStDropOut_A	7872393	8	0	0
DetectedOut_A	7872393	7570	0	0
DetectedPulseOut_A	7872393	38	0	0
DisabledIdleSt_A	7872393	5808508	0	0
DisabledNoDetection_A	7872393	5810966	0	0
EnterDebounceSt_A	7872393	90	0	0
EnterDetectSt_A	7872393	46	0	0
EnterStableSt_A	7872393	38	0	0
PulseIsPulse_A	7872393	38	0	0
StayInStableSt	7872393	7532	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	7050	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_sticky_sva.StableStDropOut_A	7872393	1097828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	135	0	0
T7	1582	6	0	0
T8	28357	2	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T12	0	2	0	0
T19	0	2	0	0
T20	0	2	0	0
T24	0	2	0	0
T32	6847	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	2	0	0
T60	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	187818	0	0
T7	1582	249	0	0
T8	28357	96	0	0
T9	25340	32	0	0
T10	8317	0	0	0
T12	0	13	0	0
T19	0	25	0	0
T20	0	94	0	0
T24	0	75	0	0
T32	6847	64	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	47	0	0
T60	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182526	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	8	0	0
T7	1582	1	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T81	0	2	0	0
T93	0	2	0	0
T125	0	2	0	0
T126	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7570	0	0
T7	1582	258	0	0
T8	28357	688	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	28	0	0
T19	0	167	0	0
T20	0	226	0	0
T24	0	76	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	205	0	0
T40	0	230	0	0
T41	0	501	0	0
T121	0	33	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	38	0	0
T7	1582	2	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T121	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5808508	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5810966	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	90	0	0
T7	1582	3	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T32	6847	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	1	0	0
T60	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	46	0	0
T7	1582	3	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	38	0	0
T7	1582	2	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T121	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	38	0	0
T7	1582	2	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T121	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7532	0	0
T7	1582	256	0	0
T8	28357	687	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	27	0	0
T19	0	166	0	0
T20	0	225	0	0
T24	0	75	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	204	0	0
T40	0	228	0	0
T41	0	500	0	0
T121	0	32	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7050	0	0
T6	522	4	0	0
T42	427	2	0	0
T43	431	3	0	0
T44	569	0	0	0
T45	1016	4	0	0
T46	2176	17	0	0
T47	423	1	0	0
T48	608	3	0	0
T54	0	27	0	0
T55	498	6	0	0
T71	716	0	0	0
T72	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1097828	0	0
T7	1582	151	0	0
T8	28357	150	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	146	0	0
T19	0	175	0	0
T20	0	75	0	0
T24	0	113	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	65	0	0
T40	0	302	0	0
T41	0	120	0	0
T121	0	27223	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T42,T43
1	1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T7,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T32,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T12
0	1	Covered	T7,T8,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T12
0	1	Unreachable
1	0	Covered	T7,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T7,T8
DetectSt	168	Covered	T7,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T9
DebounceSt->IdleSt	163	Covered	T32,T7,T8
DetectSt->IdleSt	186	Covered	T7,T8,T92
DetectSt->StableSt	191	Covered	T7,T9,T12
IdleSt->DebounceSt	148	Covered	T32,T7,T8
StableSt->IdleSt	206	Covered	T7,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T7,T8
0	1	Covered	T32,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T8,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T7,T8,T92
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	138	0	0
CntIncr_A	7872393	207606	0	0
CntNoWrap_A	7872393	7182523	0	0
DetectStDropOut_A	7872393	17	0	0
DetectedOut_A	7872393	530160	0	0
DetectedPulseOut_A	7872393	40	0	0
DisabledIdleSt_A	7872393	5808508	0	0
DisabledNoDetection_A	7872393	5810966	0	0
EnterDebounceSt_A	7872393	82	0	0
EnterDetectSt_A	7872393	57	0	0
EnterStableSt_A	7872393	40	0	0
PulseIsPulse_A	7872393	40	0	0
StayInStableSt	7872393	530120	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_sticky_sva.StableStDropOut_A	7872393	440394	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	138	0	0
T7	1582	9	0	0
T8	28357	9	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T12	0	2	0	0
T19	0	4	0	0
T20	0	2	0	0
T24	0	2	0	0
T32	6847	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	2	0	0
T60	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	207606	0	0
T7	1582	425	0	0
T8	28357	330	0	0
T9	25340	89	0	0
T10	8317	0	0	0
T12	0	26	0	0
T19	0	120	0	0
T20	0	22	0	0
T24	0	62	0	0
T32	6847	64	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	13	0	0
T60	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182523	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	17	0	0
T7	1582	3	0	0
T8	28357	4	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T77	0	2	0	0
T92	0	1	0	0
T124	0	1	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	530160	0	0
T7	1582	85	0	0
T8	28357	0	0	0
T9	25340	114	0	0
T10	8317	0	0	0
T12	0	95	0	0
T20	0	94	0	0
T24	0	165	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	40	0	0
T40	0	342	0	0
T81	0	185	0	0
T121	0	1359	0	0
T122	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	40	0	0
T7	1582	1	0	0
T8	28357	0	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T12	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T81	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5808508	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5810966	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	82	0	0
T7	1582	5	0	0
T8	28357	5	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T24	0	1	0	0
T32	6847	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	1	0	0
T60	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	57	0	0
T7	1582	4	0	0
T8	28357	4	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T12	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T92	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	40	0	0
T7	1582	1	0	0
T8	28357	0	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T12	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T81	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	40	0	0
T7	1582	1	0	0
T8	28357	0	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T12	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T81	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	530120	0	0
T7	1582	84	0	0
T8	28357	0	0	0
T9	25340	113	0	0
T10	8317	0	0	0
T12	0	94	0	0
T20	0	93	0	0
T24	0	164	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	39	0	0
T40	0	340	0	0
T81	0	184	0	0
T121	0	1358	0	0
T122	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	440394	0	0
T7	1582	43	0	0
T8	28357	0	0	0
T9	25340	157	0	0
T10	8317	0	0	0
T12	0	67	0	0
T20	0	275	0	0
T24	0	45	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	261	0	0
T40	0	102	0	0
T81	0	455	0	0
T121	0	29	0	0
T122	0	96	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T7,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T32,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T19
0	1	Covered	T19,T20,T24
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T19
0	1	Unreachable
1	0	Covered	T7,T12,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T7,T8
DetectSt	168	Covered	T7,T12,T19
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T19

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T19
DebounceSt->IdleSt	163	Covered	T32,T8,T9
DetectSt->IdleSt	186	Covered	T19,T20,T24
DetectSt->StableSt	191	Covered	T7,T12,T19
IdleSt->DebounceSt	148	Covered	T32,T7,T8
StableSt->IdleSt	206	Covered	T7,T12,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T7,T8
0	1	Covered	T32,T7,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T19
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T9,T20
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T19,T20,T24
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T12,T19
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	145	0	0
CntIncr_A	7872393	435476	0	0
CntNoWrap_A	7872393	7182516	0	0
DetectStDropOut_A	7872393	15	0	0
DetectedOut_A	7872393	62535	0	0
DetectedPulseOut_A	7872393	35	0	0
DisabledIdleSt_A	7872393	5808508	0	0
DisabledNoDetection_A	7872393	5810966	0	0
EnterDebounceSt_A	7872393	96	0	0
EnterDetectSt_A	7872393	50	0	0
EnterStableSt_A	7872393	35	0	0
PulseIsPulse_A	7872393	35	0	0
StayInStableSt	7872393	62500	0	0
gen_high_event_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_sticky_sva.StableStDropOut_A	7872393	651782	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	145	0	0
T7	1582	4	0	0
T8	28357	5	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T12	0	2	0	0
T19	0	8	0	0
T20	0	5	0	0
T24	0	4	0	0
T32	6847	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	6	0	0
T60	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	435476	0	0
T7	1582	20	0	0
T8	28357	65	0	0
T9	25340	138	0	0
T10	8317	0	0	0
T12	0	22	0	0
T19	0	260	0	0
T20	0	42	0	0
T24	0	190	0	0
T32	6847	66	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	168	0	0
T60	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182516	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	15	0	0
T19	9761	3	0	0
T20	0	2	0	0
T24	0	1	0	0
T39	0	3	0	0
T64	4577	0	0	0
T69	17856	0	0	0
T121	0	1	0	0
T126	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	522	0	0	0
T135	9529	0	0	0
T136	422	0	0	0
T137	421	0	0	0
T138	667	0	0	0
T139	528	0	0	0
T140	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	62535	0	0
T7	1582	57	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	86	0	0
T19	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T40	0	417	0	0
T41	0	495	0	0
T92	0	66	0	0
T93	0	55706	0	0
T123	0	189	0	0
T124	0	383	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	35	0	0
T7	1582	2	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5808508	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5810966	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	96	0	0
T7	1582	2	0	0
T8	28357	5	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	4	0	0
T20	0	3	0	0
T24	0	2	0	0
T32	6847	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T39	0	3	0	0
T60	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	50	0	0
T7	1582	2	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T24	0	2	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T39	0	3	0	0
T40	0	2	0	0
T41	0	1	0	0
T92	0	1	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	35	0	0
T7	1582	2	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	35	0	0
T7	1582	2	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T24	0	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	62500	0	0
T7	1582	55	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	85	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T40	0	415	0	0
T41	0	494	0	0
T92	0	65	0	0
T93	0	55705	0	0
T123	0	188	0	0
T124	0	382	0	0
T125	0	721	0	0
T141	0	7	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	651782	0	0
T7	1582	627	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T12	0	90	0	0
T19	0	45	0	0
T24	0	59	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T40	0	80	0	0
T41	0	149	0	0
T92	0	33	0	0
T93	0	42	0	0
T123	0	47	0	0
T124	0	153	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T60,T61

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T60,T61

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T60,T61,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T8,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T32,T60,T61

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T60,T61,T62
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T60,T61,T62
0	1	Covered	T62,T142,T90
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T60,T61,T62
1	-	Covered	T62,T142,T90

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T60,T61
DetectSt	168	Covered	T60,T61,T62
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T60,T61,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T60,T61,T62
DebounceSt->IdleSt	163	Covered	T32,T143,T144
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T60,T61,T62
IdleSt->DebounceSt	148	Covered	T32,T60,T61
StableSt->IdleSt	206	Covered	T60,T62,T145

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T60,T61
0	1	Covered	T32,T60,T61
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T60,T61,T62
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T60,T61
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T60,T61,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T143,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T60,T61
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T60,T61,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T60,T62,T142
StableSt	-	-	-	-	-	-	0	Covered	T60,T61,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	67	0	0
CntIncr_A	7872393	2147	0	0
CntNoWrap_A	7872393	7182594	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	2785	0	0
DetectedPulseOut_A	7872393	31	0	0
DisabledIdleSt_A	7872393	7164092	0	0
DisabledNoDetection_A	7872393	7166498	0	0
EnterDebounceSt_A	7872393	35	0	0
EnterDetectSt_A	7872393	32	0	0
EnterStableSt_A	7872393	31	0	0
PulseIsPulse_A	7872393	31	0	0
StayInStableSt	7872393	2734	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	2	0	0
T90	0	6	0	0
T132	0	4	0	0
T142	0	4	0	0
T145	0	4	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2147	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T32	6847	26	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	22	0	0
T61	0	74	0	0
T62	0	93	0	0
T63	0	55	0	0
T90	0	213	0	0
T132	0	166	0	0
T142	0	74	0	0
T145	0	138	0	0
T146	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182594	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T84	13252	1	0	0
T85	19193	0	0	0
T103	16702	0	0	0
T147	503	0	0	0
T148	492	0	0	0
T149	688	0	0	0
T150	404	0	0	0
T151	43950	0	0	0
T152	445	0	0	0
T153	6018	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2785	0	0
T60	6842	2	0	0
T61	0	43	0	0
T62	0	181	0	0
T63	0	41	0	0
T80	24013	0	0	0
T90	0	169	0	0
T98	5121	0	0	0
T120	12648	0	0	0
T132	0	80	0	0
T142	0	117	0	0
T145	0	80	0	0
T146	0	41	0	0
T154	0	38	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	31	0	0
T60	6842	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T80	24013	0	0	0
T90	0	3	0	0
T98	5121	0	0	0
T120	12648	0	0	0
T132	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T154	0	1	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7164092	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7166498	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	35	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T90	0	3	0	0
T132	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	32	0	0
T60	6842	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T80	24013	0	0	0
T90	0	3	0	0
T98	5121	0	0	0
T120	12648	0	0	0
T132	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T154	0	1	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	31	0	0
T60	6842	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T80	24013	0	0	0
T90	0	3	0	0
T98	5121	0	0	0
T120	12648	0	0	0
T132	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T154	0	1	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	31	0	0
T60	6842	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T80	24013	0	0	0
T90	0	3	0	0
T98	5121	0	0	0
T120	12648	0	0	0
T132	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T146	0	1	0	0
T154	0	1	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2734	0	0
T60	6842	1	0	0
T61	0	41	0	0
T62	0	180	0	0
T63	0	39	0	0
T80	24013	0	0	0
T90	0	165	0	0
T98	5121	0	0	0
T120	12648	0	0	0
T132	0	77	0	0
T142	0	114	0	0
T145	0	76	0	0
T146	0	39	0	0
T154	0	36	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	10	0	0
T39	1177	0	0	0
T62	3439	1	0	0
T84	0	1	0	0
T90	0	2	0	0
T132	0	1	0	0
T142	0	1	0	0
T144	0	1	0	0
T149	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	404	0	0	0
T164	510	0	0	0
T165	404	0	0	0
T166	522	0	0	0
T167	19282	0	0	0
T168	21550	0	0	0
T169	575	0	0	0
T170	5166	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T9
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T13,T59,T171
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T13
1	-	Covered	T13,T59,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T9
DetectSt	168	Covered	T2,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T13
DebounceSt->IdleSt	163	Covered	T32,T61,T132
DetectSt->IdleSt	186	Covered	T87,T88
DetectSt->StableSt	191	Covered	T2,T9,T13
IdleSt->DebounceSt	148	Covered	T2,T32,T9
StableSt->IdleSt	206	Covered	T9,T13,T19

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T9
0	1	Covered	T2,T32,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T132,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T9
DetectSt	-	-	-	-	1	-	-	Covered	T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T59,T60
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	122	0	0
CntIncr_A	7872393	56213	0	0
CntNoWrap_A	7872393	7182539	0	0
DetectStDropOut_A	7872393	2	0	0
DetectedOut_A	7872393	67641	0	0
DetectedPulseOut_A	7872393	57	0	0
DisabledIdleSt_A	7872393	7050191	0	0
DisabledNoDetection_A	7872393	7052599	0	0
EnterDebounceSt_A	7872393	63	0	0
EnterDetectSt_A	7872393	59	0	0
EnterStableSt_A	7872393	57	0	0
PulseIsPulse_A	7872393	57	0	0
StayInStableSt	7872393	67558	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	2790	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	122	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	2	0	0
T13	0	4	0	0
T14	0	2	0	0
T19	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	1	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	56213	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	85	0	0
T13	0	158	0	0
T14	0	48	0	0
T19	0	40	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	25	0	0
T59	0	60	0	0
T60	0	22	0	0
T61	0	74	0	0
T171	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182539	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2	0	0
T87	21521	1	0	0
T88	24370	1	0	0
T173	504	0	0	0
T174	13565	0	0	0
T175	525	0	0	0
T176	431	0	0	0
T177	410	0	0	0
T178	40661	0	0	0
T179	852	0	0	0
T180	1033	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67641	0	0
T2	500	69	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	272	0	0
T13	0	248	0	0
T14	0	107	0	0
T19	0	114	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	141	0	0
T60	0	3	0	0
T62	0	85	0	0
T145	0	251	0	0
T171	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	57	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T19	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	2	0	0
T145	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7050191	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7052599	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T19	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	59	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T19	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	2	0	0
T145	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	57	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T19	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	2	0	0
T145	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	57	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T19	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T62	0	2	0	0
T145	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67558	0	0
T2	500	67	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	270	0	0
T13	0	245	0	0
T14	0	105	0	0
T19	0	112	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	138	0	0
T60	0	2	0	0
T62	0	82	0	0
T145	0	250	0	0
T171	0	159	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2790	0	0
T2	0	1	0	0
T6	522	5	0	0
T25	0	3	0	0
T42	427	2	0	0
T43	431	2	0	0
T44	569	0	0	0
T45	1016	0	0	0
T46	2176	8	0	0
T47	423	3	0	0
T48	608	0	0	0
T55	498	3	0	0
T56	0	5	0	0
T71	716	0	0	0
T72	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	30	0	0
T13	39966	1	0	0
T14	736	0	0	0
T15	8882	0	0	0
T16	30851	0	0	0
T59	0	1	0	0
T62	0	1	0	0
T65	5139	0	0	0
T67	1593	0	0	0
T73	502	0	0	0
T108	858	0	0	0
T109	422	0	0	0
T132	0	1	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T182	1757	0	0	0