Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T9,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T9,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T8,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T32,T9,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T18
0	1	Covered	T13,T18,T183
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T18
1	-	Covered	T13,T18,T183

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T9,T13
DetectSt	168	Covered	T9,T13,T18
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T18
DebounceSt->IdleSt	163	Covered	T32,T144
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T13,T18
IdleSt->DebounceSt	148	Covered	T32,T9,T13
StableSt->IdleSt	206	Covered	T9,T13,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T9,T13
0	1	Covered	T32,T9,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T18
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T9,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T144
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T9,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T18,T60
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	92	0	0
CntIncr_A	7872393	2837	0	0
CntNoWrap_A	7872393	7182569	0	0
DetectStDropOut_A	7872393	0	0	0
DetectedOut_A	7872393	3457	0	0
DetectedPulseOut_A	7872393	45	0	0
DisabledIdleSt_A	7872393	7159357	0	0
DisabledNoDetection_A	7872393	7161756	0	0
EnterDebounceSt_A	7872393	47	0	0
EnterDetectSt_A	7872393	45	0	0
EnterStableSt_A	7872393	45	0	0
PulseIsPulse_A	7872393	45	0	0
StayInStableSt	7872393	3385	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	92	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	4	0	0
T10	8317	0	0	0
T13	0	8	0	0
T18	0	2	0	0
T21	0	2	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	2	0	0
T145	0	2	0	0
T183	0	4	0	0
T184	0	2	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2837	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	146	0	0
T10	8317	0	0	0
T13	0	265	0	0
T18	0	84	0	0
T21	0	55	0	0
T32	6847	27	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	22	0	0
T145	0	92	0	0
T183	0	142	0	0
T184	0	45	0	0
T185	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182569	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3457	0	0
T9	25340	82	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	172	0	0
T18	0	19	0	0
T21	0	41	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	3	0	0
T66	4967	0	0	0
T107	414	0	0	0
T145	0	40	0	0
T183	0	80	0	0
T184	0	43	0	0
T185	0	218	0	0
T186	0	88	0	0
T187	826	0	0	0
T188	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T21	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T145	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7159357	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7161756	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	47	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T21	0	1	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	1	0	0
T145	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T21	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T145	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T21	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T145	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T21	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T145	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3385	0	0
T9	25340	78	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	167	0	0
T18	0	18	0	0
T21	0	39	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	2	0	0
T66	4967	0	0	0
T107	414	0	0	0
T145	0	38	0	0
T183	0	77	0	0
T184	0	41	0	0
T185	0	217	0	0
T186	0	85	0	0
T187	826	0	0	0
T188	427	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	17	0	0
T13	39966	3	0	0
T14	736	0	0	0
T15	8882	0	0	0
T16	30851	0	0	0
T18	0	1	0	0
T65	5139	0	0	0
T67	1593	0	0	0
T73	502	0	0	0
T90	0	2	0	0
T108	858	0	0	0
T109	422	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T161	0	1	0	0
T182	1757	0	0	0
T183	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T9,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T9,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T13,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T9,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T32,T9,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T18
0	1	Covered	T9,T13,T18
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T18
1	-	Covered	T9,T13,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T9,T13
DetectSt	168	Covered	T9,T13,T18
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T13,T18
DebounceSt->IdleSt	163	Covered	T32,T145,T190
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T13,T18
IdleSt->DebounceSt	148	Covered	T32,T9,T13
StableSt->IdleSt	206	Covered	T9,T13,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T9,T13
0	1	Covered	T32,T9,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T13,T18
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T9,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T13,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T145,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T9,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T18
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	129	0	0
CntIncr_A	7872393	3998	0	0
CntNoWrap_A	7872393	7182532	0	0
DetectStDropOut_A	7872393	0	0	0
DetectedOut_A	7872393	5919	0	0
DetectedPulseOut_A	7872393	63	0	0
DisabledIdleSt_A	7872393	7162958	0	0
DisabledNoDetection_A	7872393	7165368	0	0
EnterDebounceSt_A	7872393	66	0	0
EnterDetectSt_A	7872393	63	0	0
EnterStableSt_A	7872393	63	0	0
PulseIsPulse_A	7872393	63	0	0
StayInStableSt	7872393	5828	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	3205	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	129	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	6	0	0
T18	0	4	0	0
T19	0	2	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T62	0	2	0	0
T171	0	4	0	0
T185	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3998	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	85	0	0
T10	8317	0	0	0
T13	0	207	0	0
T18	0	168	0	0
T19	0	40	0	0
T32	6847	25	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	30	0	0
T60	0	22	0	0
T62	0	93	0	0
T171	0	116	0	0
T185	0	182	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182532	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5919	0	0
T9	25340	238	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	94	0	0
T18	0	404	0	0
T19	0	114	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	114	0	0
T60	0	4	0	0
T62	0	351	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	259	0	0
T185	0	174	0	0
T186	0	133	0	0
T187	826	0	0	0
T188	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7162958	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7165368	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	66	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T13	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T171	0	2	0	0
T185	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T185	0	2	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5828	0	0
T9	25340	237	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	91	0	0
T18	0	401	0	0
T19	0	112	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	112	0	0
T60	0	3	0	0
T62	0	350	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	256	0	0
T185	0	171	0	0
T186	0	131	0	0
T187	826	0	0	0
T188	427	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3205	0	0
T4	571	2	0	0
T5	891	4	0	0
T6	522	5	0	0
T42	427	1	0	0
T43	431	2	0	0
T44	569	4	0	0
T45	1016	0	0	0
T46	2176	11	0	0
T47	423	3	0	0
T48	608	0	0	0
T55	0	6	0	0
T71	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	34	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T62	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T142	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T42,T43
1	1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T8,T9
1	0	Covered	T6,T42,T43
1	1	Covered	T32,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T18
0	1	Covered	T8,T154,T192
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T13,T18
0	1	Covered	T9,T13,T18
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T18
1	-	Covered	T9,T13,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T8,T9
DetectSt	168	Covered	T8,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T13,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T13
DebounceSt->IdleSt	163	Covered	T32,T191,T90
DetectSt->IdleSt	186	Covered	T8,T154,T192
DetectSt->StableSt	191	Covered	T9,T13,T18
IdleSt->DebounceSt	148	Covered	T32,T8,T9
StableSt->IdleSt	206	Covered	T9,T13,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T8,T9
0	1	Covered	T32,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T191,T90,T146
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T154,T192
DetectSt	-	-	-	-	0	1	-	Covered	T9,T13,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T18
StableSt	-	-	-	-	-	-	0	Covered	T9,T13,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	153	0	0
CntIncr_A	7872393	4793	0	0
CntNoWrap_A	7872393	7182508	0	0
DetectStDropOut_A	7872393	3	0	0
DetectedOut_A	7872393	5100	0	0
DetectedPulseOut_A	7872393	69	0	0
DisabledIdleSt_A	7872393	7162053	0	0
DisabledNoDetection_A	7872393	7164451	0	0
EnterDebounceSt_A	7872393	81	0	0
EnterDetectSt_A	7872393	72	0	0
EnterStableSt_A	7872393	69	0	0
PulseIsPulse_A	7872393	69	0	0
StayInStableSt	7872393	5006	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	153	0	0
T7	1582	0	0	0
T8	28357	2	0	0
T9	25340	4	0	0
T10	8317	0	0	0
T13	0	8	0	0
T18	0	2	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0
T171	0	4	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	4793	0	0
T7	1582	0	0	0
T8	28357	92	0	0
T9	25340	170	0	0
T10	8317	0	0	0
T13	0	254	0	0
T18	0	84	0	0
T32	6847	26	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	30	0	0
T60	0	22	0	0
T61	0	74	0	0
T171	0	116	0	0
T184	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182508	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T66	4967	0	0	0
T154	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T192	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5100	0	0
T9	25340	23	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	143	0	0
T18	0	144	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	81	0	0
T60	0	2	0	0
T61	0	43	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	246	0	0
T184	0	42	0	0
T185	0	221	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	219	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	69	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7162053	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7164451	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	81	0	0
T7	1582	0	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T171	0	2	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	72	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T66	4967	0	0	0
T171	0	2	0	0
T184	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	69	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	69	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	4	0	0
T18	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5006	0	0
T9	25340	21	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	138	0	0
T18	0	143	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	80	0	0
T60	0	1	0	0
T61	0	41	0	0
T66	4967	0	0	0
T107	414	0	0	0
T171	0	243	0	0
T184	0	40	0	0
T185	0	219	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	217	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	43	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T125	0	1	0	0
T145	0	1	0	0
T171	0	1	0	0
T185	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	2	0	0
T194	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T9,T13,T171
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T9
1	-	Covered	T9,T13,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T8
DetectSt	168	Covered	T2,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T9
DebounceSt->IdleSt	163	Covered	T32,T194,T143
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T8,T9
IdleSt->DebounceSt	148	Covered	T2,T32,T8
StableSt->IdleSt	206	Covered	T8,T9,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T8
0	1	Covered	T2,T32,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T194,T143,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T60
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	113	0	0
CntIncr_A	7872393	3436	0	0
CntNoWrap_A	7872393	7182548	0	0
DetectStDropOut_A	7872393	0	0	0
DetectedOut_A	7872393	3950	0	0
DetectedPulseOut_A	7872393	54	0	0
DisabledIdleSt_A	7872393	7159959	0	0
DisabledNoDetection_A	7872393	7162355	0	0
EnterDebounceSt_A	7872393	59	0	0
EnterDetectSt_A	7872393	54	0	0
EnterStableSt_A	7872393	54	0	0
PulseIsPulse_A	7872393	54	0	0
StayInStableSt	7872393	3863	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	6809	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	113	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	2	0	0
T9	0	4	0	0
T13	0	6	0	0
T14	0	2	0	0
T18	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	2	0	0
T60	0	2	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3436	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	92	0	0
T9	0	170	0	0
T13	0	196	0	0
T14	0	48	0	0
T18	0	84	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	26	0	0
T59	0	30	0	0
T60	0	22	0	0
T171	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182548	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3950	0	0
T2	500	43	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	42	0	0
T9	0	84	0	0
T13	0	287	0	0
T14	0	59	0	0
T18	0	363	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	114	0	0
T60	0	3	0	0
T62	0	16	0	0
T171	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	54	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7159959	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7162355	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	59	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	54	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	54	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	54	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T18	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3863	0	0
T2	500	41	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	40	0	0
T9	0	81	0	0
T13	0	283	0	0
T14	0	57	0	0
T18	0	361	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	112	0	0
T60	0	2	0	0
T62	0	15	0	0
T171	0	56	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6809	0	0
T6	522	6	0	0
T42	427	2	0	0
T43	431	2	0	0
T44	569	0	0	0
T45	1016	4	0	0
T46	2176	19	0	0
T47	423	3	0	0
T48	608	0	0	0
T54	0	26	0	0
T55	498	9	0	0
T56	0	3	0	0
T71	716	0	0	0
T72	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	20	0	0
T9	25340	1	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	2	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T62	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T142	0	1	0	0
T154	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T186	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T191	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T42,T43
1	1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T2,T9,T13
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T9
1	-	Covered	T2,T9,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T8
DetectSt	168	Covered	T2,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T9
DebounceSt->IdleSt	163	Covered	T32,T183,T145
DetectSt->IdleSt	186	Covered	T90
DetectSt->StableSt	191	Covered	T2,T8,T9
IdleSt->DebounceSt	148	Covered	T2,T32,T8
StableSt->IdleSt	206	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T8
0	1	Covered	T2,T32,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T145,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T8
DetectSt	-	-	-	-	1	-	-	Covered	T90
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T13
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	134	0	0
CntIncr_A	7872393	57393	0	0
CntNoWrap_A	7872393	7182527	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	67235	0	0
DetectedPulseOut_A	7872393	63	0	0
DisabledIdleSt_A	7872393	7048611	0	0
DisabledNoDetection_A	7872393	7051017	0	0
EnterDebounceSt_A	7872393	71	0	0
EnterDetectSt_A	7872393	64	0	0
EnterStableSt_A	7872393	63	0	0
PulseIsPulse_A	7872393	63	0	0
StayInStableSt	7872393	67140	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	134	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	2	0	0
T9	0	6	0	0
T13	0	2	0	0
T19	0	2	0	0
T22	0	4	0	0
T23	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T60	0	2	0	0
T61	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	57393	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	92	0	0
T9	0	207	0	0
T13	0	58	0	0
T19	0	40	0	0
T22	0	148	0	0
T23	0	32	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	25	0	0
T60	0	22	0	0
T61	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182527	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T90	14942	1	0	0
T123	761	0	0	0
T146	867	0	0	0
T196	406	0	0	0
T197	502	0	0	0
T198	435	0	0	0
T199	420	0	0	0
T200	442	0	0	0
T201	494	0	0	0
T202	1070	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67235	0	0
T2	500	4	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	136	0	0
T9	0	424	0	0
T13	0	130	0	0
T19	0	115	0	0
T22	0	42	0	0
T23	0	41	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	3	0	0
T61	0	74	0	0
T164	0	73	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T164	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7048611	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7051017	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	71	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T60	0	1	0	0
T61	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	64	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T164	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T164	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	63	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T19	0	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T164	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67140	0	0
T2	500	3	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	134	0	0
T9	0	420	0	0
T13	0	129	0	0
T19	0	113	0	0
T22	0	40	0	0
T23	0	39	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	2	0	0
T61	0	72	0	0
T164	0	71	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	30	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	2	0	0
T13	0	1	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T84	0	1	0	0
T145	0	2	0	0
T181	0	1	0	0
T193	0	1	0	0
T195	0	1	0	0
T203	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T14
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T13,T22,T171
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T13
1	-	Covered	T13,T22,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T9
DetectSt	168	Covered	T2,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T13
DebounceSt->IdleSt	163	Covered	T32
DetectSt->IdleSt	186	Covered	T14
DetectSt->StableSt	191	Covered	T2,T9,T13
IdleSt->DebounceSt	148	Covered	T2,T32,T9
StableSt->IdleSt	206	Covered	T9,T13,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T9
0	1	Covered	T2,T32,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T13
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T9
DetectSt	-	-	-	-	1	-	-	Covered	T14
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T22,T60
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	89	0	0
CntIncr_A	7872393	2856	0	0
CntNoWrap_A	7872393	7182572	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	3511	0	0
DetectedPulseOut_A	7872393	43	0	0
DisabledIdleSt_A	7872393	7045546	0	0
DisabledNoDetection_A	7872393	7047944	0	0
EnterDebounceSt_A	7872393	45	0	0
EnterDetectSt_A	7872393	44	0	0
EnterStableSt_A	7872393	43	0	0
PulseIsPulse_A	7872393	43	0	0
StayInStableSt	7872393	3446	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	6344	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	89	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T21	0	2	0	0
T22	0	4	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T60	0	2	0	0
T171	0	4	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2856	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	85	0	0
T13	0	69	0	0
T14	0	48	0	0
T21	0	55	0	0
T22	0	148	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	27	0	0
T60	0	22	0	0
T171	0	116	0	0
T184	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182572	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T14	736	1	0	0
T15	8882	0	0	0
T16	30851	0	0	0
T65	5139	0	0	0
T67	1593	0	0	0
T73	502	0	0	0
T108	858	0	0	0
T109	422	0	0	0
T182	1757	0	0	0
T204	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3511	0	0
T2	500	43	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	42	0	0
T13	0	22	0	0
T21	0	40	0	0
T22	0	77	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	3	0	0
T62	0	181	0	0
T145	0	40	0	0
T171	0	59	0	0
T184	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	43	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T62	0	1	0	0
T145	0	1	0	0
T171	0	2	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7045546	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7047944	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T60	0	1	0	0
T171	0	2	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	44	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T62	0	1	0	0
T171	0	2	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	43	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T62	0	1	0	0
T145	0	1	0	0
T171	0	2	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	43	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T21	0	1	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T62	0	1	0	0
T145	0	1	0	0
T171	0	2	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3446	0	0
T2	500	41	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	40	0	0
T13	0	21	0	0
T21	0	38	0	0
T22	0	74	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	2	0	0
T62	0	180	0	0
T145	0	38	0	0
T171	0	57	0	0
T184	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6344	0	0
T1	0	25	0	0
T6	522	5	0	0
T42	427	5	0	0
T43	431	4	0	0
T44	569	0	0	0
T45	1016	0	0	0
T46	2176	14	0	0
T47	423	1	0	0
T48	608	0	0	0
T54	0	27	0	0
T55	498	6	0	0
T56	0	4	0	0
T71	716	0	0	0
T72	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	20	0	0
T13	39966	1	0	0
T14	736	0	0	0
T15	8882	0	0	0
T16	30851	0	0	0
T22	0	1	0	0
T62	0	1	0	0
T65	5139	0	0	0
T67	1593	0	0	0
T73	502	0	0	0
T90	0	2	0	0
T108	858	0	0	0
T109	422	0	0	0
T143	0	1	0	0
T171	0	2	0	0
T182	1757	0	0	0
T195	0	1	0	0
T203	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0