Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T42,T43
1	1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T18
0	1	Covered	T8,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T18
0	1	Covered	T2,T13,T18
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T18
1	-	Covered	T2,T13,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T8
DetectSt	168	Covered	T2,T8,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T13,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T13
DebounceSt->IdleSt	163	Covered	T32,T14,T146
DetectSt->IdleSt	186	Covered	T8,T91
DetectSt->StableSt	191	Covered	T2,T13,T18
IdleSt->DebounceSt	148	Covered	T2,T32,T8
StableSt->IdleSt	206	Covered	T2,T13,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T8
0	1	Covered	T2,T32,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T146,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T18
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	136	0	0
CntIncr_A	7872393	57033	0	0
CntNoWrap_A	7872393	7182525	0	0
DetectStDropOut_A	7872393	2	0	0
DetectedOut_A	7872393	67740	0	0
DetectedPulseOut_A	7872393	64	0	0
DisabledIdleSt_A	7872393	7048952	0	0
DisabledNoDetection_A	7872393	7051360	0	0
EnterDebounceSt_A	7872393	70	0	0
EnterDetectSt_A	7872393	66	0	0
EnterStableSt_A	7872393	64	0	0
PulseIsPulse_A	7872393	64	0	0
StayInStableSt	7872393	67646	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	136	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	2	0	0
T13	0	8	0	0
T14	0	1	0	0
T18	0	4	0	0
T22	0	4	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T60	0	2	0	0
T61	0	2	0	0
T183	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	57033	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	92	0	0
T13	0	338	0	0
T14	0	48	0	0
T18	0	168	0	0
T22	0	148	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	27	0	0
T60	0	22	0	0
T61	0	74	0	0
T183	0	142	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182525	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T66	4967	0	0	0
T91	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67740	0	0
T2	500	4	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T13	0	256	0	0
T18	0	279	0	0
T22	0	196	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	3	0	0
T61	0	73	0	0
T62	0	341	0	0
T63	0	78	0	0
T83	0	122	0	0
T183	0	167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	64	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T13	0	4	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T83	0	2	0	0
T183	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7048952	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7051360	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	70	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T13	0	4	0	0
T14	0	1	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T183	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	66	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T13	0	4	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T183	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	64	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T13	0	4	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T83	0	2	0	0
T183	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	64	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T13	0	4	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T83	0	2	0	0
T183	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	67646	0	0
T2	500	3	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T13	0	251	0	0
T18	0	276	0	0
T22	0	193	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	2	0	0
T61	0	71	0	0
T62	0	338	0	0
T63	0	75	0	0
T83	0	119	0	0
T183	0	164	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	33	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T13	0	3	0	0
T18	0	1	0	0
T22	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T83	0	1	0	0
T183	0	1	0	0
T185	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T8,T9
1	0	Covered	T6,T42,T43
1	1	Covered	T32,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T13
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T13
0	1	Covered	T9,T13,T18
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T13
1	-	Covered	T9,T13,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T8,T9
DetectSt	168	Covered	T8,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T13
DebounceSt->IdleSt	163	Covered	T32,T186,T144
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T9,T13
IdleSt->DebounceSt	148	Covered	T32,T8,T9
StableSt->IdleSt	206	Covered	T8,T9,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T8,T9
0	1	Covered	T32,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T186,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T8,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T13,T18
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	93	0	0
CntIncr_A	7872393	2881	0	0
CntNoWrap_A	7872393	7182568	0	0
DetectStDropOut_A	7872393	0	0	0
DetectedOut_A	7872393	3498	0	0
DetectedPulseOut_A	7872393	45	0	0
DisabledIdleSt_A	7872393	7047523	0	0
DisabledNoDetection_A	7872393	7049926	0	0
EnterDebounceSt_A	7872393	48	0	0
EnterDetectSt_A	7872393	45	0	0
EnterStableSt_A	7872393	45	0	0
PulseIsPulse_A	7872393	45	0	0
StayInStableSt	7872393	3430	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	6431	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	93	0	0
T7	1582	0	0	0
T8	28357	2	0	0
T9	25340	4	0	0
T10	8317	0	0	0
T13	0	2	0	0
T14	0	2	0	0
T18	0	2	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	2	0	0
T63	0	2	0	0
T185	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2881	0	0
T7	1582	0	0	0
T8	28357	92	0	0
T9	25340	146	0	0
T10	8317	0	0	0
T13	0	100	0	0
T14	0	48	0	0
T18	0	84	0	0
T32	6847	26	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	22	0	0
T63	0	55	0	0
T185	0	91	0	0
T193	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182568	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3498	0	0
T8	28357	43	0	0
T9	25340	193	0	0
T10	8317	0	0	0
T13	0	199	0	0
T14	0	59	0	0
T18	0	143	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	4	0	0
T63	0	39	0	0
T66	4967	0	0	0
T145	0	247	0	0
T185	0	40	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	4967	0	0	0
T145	0	1	0	0
T185	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7047523	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7049926	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	48	0	0
T7	1582	0	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T185	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	4967	0	0	0
T145	0	1	0	0
T185	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	4967	0	0	0
T145	0	1	0	0
T185	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T8	28357	1	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	1	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T66	4967	0	0	0
T145	0	1	0	0
T185	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3430	0	0
T8	28357	41	0	0
T9	25340	191	0	0
T10	8317	0	0	0
T13	0	198	0	0
T14	0	57	0	0
T18	0	142	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T60	0	3	0	0
T63	0	38	0	0
T66	4967	0	0	0
T145	0	245	0	0
T185	0	39	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6431	0	0
T1	0	20	0	0
T6	522	6	0	0
T42	427	1	0	0
T43	431	3	0	0
T44	569	0	0	0
T45	1016	0	0	0
T46	2176	14	0	0
T47	423	4	0	0
T48	608	0	0	0
T54	0	21	0	0
T55	498	7	0	0
T56	0	6	0	0
T71	716	0	0	0
T72	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	21	0	0
T9	25340	2	0	0
T10	8317	0	0	0
T11	28461	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T63	0	1	0	0
T66	4967	0	0	0
T107	414	0	0	0
T132	0	1	0	0
T154	0	1	0	0
T181	0	1	0	0
T185	0	1	0	0
T187	826	0	0	0
T188	427	0	0	0
T193	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T42,T43
1	1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T2,T9,T13
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T13
1	-	Covered	T2,T9,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T9
DetectSt	168	Covered	T2,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T13
DebounceSt->IdleSt	163	Covered	T32,T9,T209
DetectSt->IdleSt	186	Covered	T208
DetectSt->StableSt	191	Covered	T2,T9,T13
IdleSt->DebounceSt	148	Covered	T2,T32,T9
StableSt->IdleSt	206	Covered	T2,T9,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T9
0	1	Covered	T2,T32,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T9
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T209,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T9
DetectSt	-	-	-	-	1	-	-	Covered	T208
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T13
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	158	0	0
CntIncr_A	7872393	4772	0	0
CntNoWrap_A	7872393	7182503	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	7446	0	0
DetectedPulseOut_A	7872393	75	0	0
DisabledIdleSt_A	7872393	7158664	0	0
DisabledNoDetection_A	7872393	7161062	0	0
EnterDebounceSt_A	7872393	82	0	0
EnterDetectSt_A	7872393	76	0	0
EnterStableSt_A	7872393	75	0	0
PulseIsPulse_A	7872393	75	0	0
StayInStableSt	7872393	7342	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	158	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	3	0	0
T13	0	4	0	0
T14	0	2	0	0
T18	0	4	0	0
T22	0	4	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	4	0	0
T60	0	2	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	4772	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	122	0	0
T13	0	127	0	0
T14	0	48	0	0
T18	0	168	0	0
T22	0	148	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	25	0	0
T59	0	60	0	0
T60	0	22	0	0
T171	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182503	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T104	24133	0	0	0
T162	1217	0	0	0
T208	503	1	0	0
T210	1012	0	0	0
T211	12693	0	0	0
T212	402	0	0	0
T213	6921	0	0	0
T214	410	0	0	0
T215	560	0	0	0
T216	8936	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7446	0	0
T2	500	4	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	102	0	0
T13	0	217	0	0
T14	0	200	0	0
T18	0	59	0	0
T22	0	257	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	35	0	0
T60	0	3	0	0
T171	0	265	0	0
T184	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	75	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T171	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7158664	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7161062	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	82	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	2	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	76	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T171	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	75	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T171	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	75	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T18	0	2	0	0
T22	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T171	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7342	0	0
T2	500	3	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	101	0	0
T13	0	214	0	0
T14	0	198	0	0
T18	0	57	0	0
T22	0	254	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	33	0	0
T60	0	2	0	0
T171	0	264	0	0
T184	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	45	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T18	0	2	0	0
T22	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T145	0	1	0	0
T171	0	1	0	0
T185	0	1	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T59,T62,T193
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T13
1	-	Covered	T59,T62,T193

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T9
DetectSt	168	Covered	T2,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T13
DebounceSt->IdleSt	163	Covered	T32,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T13
IdleSt->DebounceSt	148	Covered	T2,T32,T9
StableSt->IdleSt	206	Covered	T9,T13,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T9
0	1	Covered	T2,T32,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T85
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T59,T60,T62
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	84	0	0
CntIncr_A	7872393	2844	0	0
CntNoWrap_A	7872393	7182577	0	0
DetectStDropOut_A	7872393	0	0	0
DetectedOut_A	7872393	3199	0	0
DetectedPulseOut_A	7872393	41	0	0
DisabledIdleSt_A	7872393	7045801	0	0
DisabledNoDetection_A	7872393	7048206	0	0
EnterDebounceSt_A	7872393	43	0	0
EnterDetectSt_A	7872393	41	0	0
EnterStableSt_A	7872393	41	0	0
PulseIsPulse_A	7872393	41	0	0
StayInStableSt	7872393	3136	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	6274	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	84	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	2	0	0
T13	0	2	0	0
T23	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T83	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2844	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	85	0	0
T13	0	69	0	0
T23	0	32	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	26	0	0
T59	0	60	0	0
T60	0	22	0	0
T61	0	74	0	0
T62	0	93	0	0
T83	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182577	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3199	0	0
T2	500	44	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	144	0	0
T13	0	248	0	0
T23	0	41	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	156	0	0
T60	0	3	0	0
T61	0	43	0	0
T62	0	41	0	0
T83	0	81	0	0
T193	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	41	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T83	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7045801	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7048206	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	43	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T83	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	41	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T83	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	41	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T83	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	41	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T83	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3136	0	0
T2	500	42	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	142	0	0
T13	0	246	0	0
T23	0	39	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T59	0	153	0	0
T60	0	2	0	0
T61	0	41	0	0
T62	0	40	0	0
T83	0	79	0	0
T193	0	46	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6274	0	0
T1	0	29	0	0
T6	522	6	0	0
T42	427	3	0	0
T43	431	1	0	0
T44	569	0	0	0
T45	1016	0	0	0
T46	2176	10	0	0
T47	423	4	0	0
T48	608	0	0	0
T54	0	26	0	0
T55	498	11	0	0
T56	0	6	0	0
T71	716	0	0	0
T72	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	18	0	0
T59	31947	1	0	0
T60	6842	0	0	0
T62	0	1	0	0
T80	24013	0	0	0
T120	12648	0	0	0
T142	0	1	0	0
T155	27224	0	0	0
T156	13434	0	0	0
T157	502	0	0	0
T158	438	0	0	0
T159	8389	0	0	0
T160	402	0	0	0
T181	0	2	0	0
T185	0	1	0	0
T193	0	1	0	0
T195	0	2	0	0
T203	0	1	0	0
T207	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T42,T43
1	1	Covered	T6,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T32,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T32,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T32,T8
1	0	Covered	T6,T42,T43
1	1	Covered	T2,T32,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T190
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T2,T8,T9
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T13
1	-	Covered	T2,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T32,T8
DetectSt	168	Covered	T2,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T9
DebounceSt->IdleSt	163	Covered	T32,T9,T61
DetectSt->IdleSt	186	Covered	T190
DetectSt->StableSt	191	Covered	T2,T8,T9
IdleSt->DebounceSt	148	Covered	T2,T32,T8
StableSt->IdleSt	206	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T32,T8
0	1	Covered	T2,T32,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T32,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T61,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T32,T8
DetectSt	-	-	-	-	1	-	-	Covered	T190
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	129	0	0
CntIncr_A	7872393	4226	0	0
CntNoWrap_A	7872393	7182532	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	5340	0	0
DetectedPulseOut_A	7872393	59	0	0
DisabledIdleSt_A	7872393	7163004	0	0
DisabledNoDetection_A	7872393	7165409	0	0
EnterDebounceSt_A	7872393	69	0	0
EnterDetectSt_A	7872393	60	0	0
EnterStableSt_A	7872393	59	0	0
PulseIsPulse_A	7872393	59	0	0
StayInStableSt	7872393	5260	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	129	0	0
T2	500	2	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	2	0	0
T9	0	7	0	0
T13	0	2	0	0
T14	0	2	0	0
T18	0	4	0	0
T19	0	2	0	0
T21	0	2	0	0
T23	0	2	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	4226	0	0
T2	500	21	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	92	0	0
T9	0	268	0	0
T13	0	100	0	0
T14	0	48	0	0
T18	0	168	0	0
T19	0	40	0	0
T21	0	55	0	0
T23	0	32	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182532	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T101	11743	0	0	0
T190	553	1	0	0
T217	2129	0	0	0
T218	839	0	0	0
T219	17864	0	0	0
T220	55143	0	0	0
T221	714	0	0	0
T222	402	0	0	0
T223	408	0	0	0
T224	16677	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5340	0	0
T2	500	4	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	62	0	0
T13	0	36	0	0
T14	0	92	0	0
T18	0	153	0	0
T19	0	115	0	0
T21	0	22	0	0
T23	0	41	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	59	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7163004	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7165409	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	69	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	60	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	59	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	59	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	5260	0	0
T2	500	3	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T9	0	59	0	0
T13	0	35	0	0
T14	0	91	0	0
T18	0	151	0	0
T19	0	113	0	0
T21	0	21	0	0
T23	0	39	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T60	0	1	0	0
T62	0	65	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	37	0	0
T2	500	1	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	1	0	0
T9	0	3	0	0
T13	0	1	0	0
T14	0	1	0	0
T18	0	2	0	0
T21	0	1	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T62	0	2	0	0
T169	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T42,T43
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T42,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T8,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T32,T8,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T18,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T8,T18
1	0	Covered	T6,T42,T43
1	1	Covered	T32,T8,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T18,T59
0	1	Covered	T225
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T18,T59
0	1	Covered	T18,T59,T186
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T18,T59
1	-	Covered	T18,T59,T186

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T8,T18
DetectSt	168	Covered	T8,T18,T59
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T18,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T18,T59
DebounceSt->IdleSt	163	Covered	T32
DetectSt->IdleSt	186	Covered	T225
DetectSt->StableSt	191	Covered	T8,T18,T59
IdleSt->DebounceSt	148	Covered	T32,T8,T18
StableSt->IdleSt	206	Covered	T8,T18,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T8,T18
0	1	Covered	T32,T8,T18
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T18,T59
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T8,T18
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T18,T59
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T8,T18
DetectSt	-	-	-	-	1	-	-	Covered	T225
DetectSt	-	-	-	-	0	1	-	Covered	T8,T18,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T59,T60
StableSt	-	-	-	-	-	-	0	Covered	T8,T18,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	87	0	0
CntIncr_A	7872393	2216	0	0
CntNoWrap_A	7872393	7182574	0	0
DetectStDropOut_A	7872393	1	0	0
DetectedOut_A	7872393	3097	0	0
DetectedPulseOut_A	7872393	42	0	0
DisabledIdleSt_A	7872393	7166064	0	0
DisabledNoDetection_A	7872393	7168478	0	0
EnterDebounceSt_A	7872393	44	0	0
EnterDetectSt_A	7872393	43	0	0
EnterStableSt_A	7872393	42	0	0
PulseIsPulse_A	7872393	42	0	0
StayInStableSt	7872393	3027	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7872393	7050	0	0
gen_low_level_sva.LowLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	87	0	0
T7	1582	0	0	0
T8	28357	2	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	4	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	4	0	0
T60	0	2	0	0
T83	0	2	0	0
T164	0	2	0	0
T169	0	2	0	0
T183	0	2	0	0
T186	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2216	0	0
T7	1582	0	0	0
T8	28357	92	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	168	0	0
T32	6847	25	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	60	0	0
T60	0	22	0	0
T83	0	24	0	0
T164	0	27	0	0
T169	0	48	0	0
T183	0	71	0	0
T186	0	106	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7182574	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1	0	0
T225	637	1	0	0
T226	414	0	0	0
T227	64008	0	0	0
T228	620	0	0	0
T229	9416	0	0	0
T230	492	0	0	0
T231	4412	0	0	0
T232	407	0	0	0
T233	451	0	0	0
T234	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3097	0	0
T8	28357	42	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	185	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	158	0	0
T60	0	3	0	0
T66	4967	0	0	0
T83	0	46	0	0
T164	0	45	0	0
T169	0	41	0	0
T181	0	154	0	0
T183	0	41	0	0
T186	0	186	0	0
T187	826	0	0	0
T188	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	42	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	2	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T66	4967	0	0	0
T83	0	1	0	0
T164	0	1	0	0
T169	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7166064	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7168478	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	44	0	0
T7	1582	0	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	2	0	0
T32	6847	1	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T83	0	1	0	0
T164	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0
T186	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	43	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	2	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T66	4967	0	0	0
T83	0	1	0	0
T164	0	1	0	0
T169	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	42	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	2	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T66	4967	0	0	0
T83	0	1	0	0
T164	0	1	0	0
T169	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	42	0	0
T8	28357	1	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	2	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	2	0	0
T60	0	1	0	0
T66	4967	0	0	0
T83	0	1	0	0
T164	0	1	0	0
T169	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T186	0	2	0	0
T187	826	0	0	0
T188	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	3027	0	0
T8	28357	40	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T18	0	182	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	13408	0	0	0
T59	0	155	0	0
T60	0	2	0	0
T66	4967	0	0	0
T83	0	44	0	0
T164	0	43	0	0
T169	0	39	0	0
T181	0	152	0	0
T183	0	39	0	0
T186	0	183	0	0
T187	826	0	0	0
T188	427	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7050	0	0
T6	522	4	0	0
T42	427	2	0	0
T43	431	3	0	0
T44	569	0	0	0
T45	1016	4	0	0
T46	2176	17	0	0
T47	423	1	0	0
T48	608	3	0	0
T54	0	27	0	0
T55	498	6	0	0
T71	716	0	0	0
T72	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	13	0	0
T18	3247	1	0	0
T19	9761	0	0	0
T59	0	1	0	0
T64	4577	0	0	0
T69	17856	0	0	0
T84	0	1	0	0
T134	522	0	0	0
T135	9529	0	0	0
T136	422	0	0	0
T137	421	0	0	0
T138	667	0	0	0
T139	528	0	0	0
T142	0	1	0	0
T186	0	1	0	0
T189	0	1	0	0
T194	0	1	0	0
T206	0	1	0	0
T218	0	1	0	0
T235	0	1	0	0