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Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 100.00 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT54,T1,T3
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT54,T1,T3
10CoveredT1,T3,T32
11CoveredT54,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT54,T1,T3
01CoveredT54,T3,T32
10CoveredT3,T32,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T32,T64
01CoveredT1,T32,T64
10CoveredT32,T60,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT1,T32,T64
1-CoveredT1,T32,T64

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T54,T1,T3
DetectSt 168 Covered T54,T1,T3
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T1,T32,T64


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T54,T1,T3
DebounceSt->IdleSt 163 Covered T32,T64,T60
DetectSt->IdleSt 186 Covered T54,T3,T32
DetectSt->StableSt 191 Covered T1,T32,T64
IdleSt->DebounceSt 148 Covered T54,T1,T3
StableSt->IdleSt 206 Covered T1,T32,T64



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T54,T1,T3
0 1 Covered T54,T1,T3
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T54,T1,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T54,T1,T3
IdleSt 0 - - - - - - Covered T54,T1,T3
DebounceSt - 1 - - - - - Covered T32,T60
DebounceSt - 0 1 1 - - - Covered T54,T1,T3
DebounceSt - 0 1 0 - - - Covered T32,T64,T60
DebounceSt - 0 0 - - - - Covered T54,T1,T3
DetectSt - - - - 1 - - Covered T54,T3,T32
DetectSt - - - - 0 1 - Covered T1,T32,T64
DetectSt - - - - 0 0 - Covered T54,T1,T3
StableSt - - - - - - 1 Covered T1,T32,T64
StableSt - - - - - - 0 Covered T1,T32,T64
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7872393 2825 0 0
CntIncr_A 7872393 95526 0 0
CntNoWrap_A 7872393 7179836 0 0
DetectStDropOut_A 7872393 511 0 0
DetectedOut_A 7872393 70367 0 0
DetectedPulseOut_A 7872393 667 0 0
DisabledIdleSt_A 7872393 6750061 0 0
DisabledNoDetection_A 7872393 6752289 0 0
EnterDebounceSt_A 7872393 1442 0 0
EnterDetectSt_A 7872393 1384 0 0
EnterStableSt_A 7872393 667 0 0
PulseIsPulse_A 7872393 667 0 0
StayInStableSt 7872393 69558 0 0
gen_high_event_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_high_level_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_not_sticky_sva.StableStDropOut_A 7872393 521 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 2825 0 0
T1 20302 18 0 0
T2 500 0 0 0
T3 12676 24 0 0
T15 0 58 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 17 0 0
T38 0 8 0 0
T54 4766 54 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 28 0 0
T65 0 60 0 0
T66 0 12 0 0
T69 0 24 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 95526 0 0
T1 20302 495 0 0
T2 500 0 0 0
T3 12676 658 0 0
T15 0 1697 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 431 0 0
T38 0 225 0 0
T54 4766 1161 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 1150 0 0
T65 0 1494 0 0
T66 0 280 0 0
T69 0 692 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7179836 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 511 0 0
T1 20302 0 0 0
T2 500 0 0 0
T3 12676 9 0 0
T15 0 16 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 1 0 0
T38 0 2 0 0
T54 4766 27 0 0
T56 522 0 0 0
T57 745 0 0 0
T60 0 1 0 0
T65 0 30 0 0
T66 0 6 0 0
T98 0 5 0 0
T99 0 26 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 70367 0 0
T1 20302 2541 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 351 0 0
T60 0 291 0 0
T64 0 69 0 0
T80 0 2258 0 0
T118 0 806 0 0
T120 0 18 0 0
T236 0 1146 0 0
T237 0 482 0 0
T238 0 351 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 667 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 5 0 0
T60 0 5 0 0
T64 0 10 0 0
T80 0 10 0 0
T118 0 11 0 0
T120 0 4 0 0
T236 0 12 0 0
T237 0 15 0 0
T238 0 6 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6750061 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6752289 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 1442 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 12 0 0
T15 0 29 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 10 0 0
T38 0 4 0 0
T54 4766 27 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 18 0 0
T65 0 30 0 0
T66 0 6 0 0
T69 0 12 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 1384 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 12 0 0
T15 0 29 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 7 0 0
T38 0 4 0 0
T54 4766 27 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 10 0 0
T65 0 30 0 0
T66 0 6 0 0
T69 0 12 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 667 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 5 0 0
T60 0 5 0 0
T64 0 10 0 0
T80 0 10 0 0
T118 0 11 0 0
T120 0 4 0 0
T236 0 12 0 0
T237 0 15 0 0
T238 0 6 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 667 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 5 0 0
T60 0 5 0 0
T64 0 10 0 0
T80 0 10 0 0
T118 0 11 0 0
T120 0 4 0 0
T236 0 12 0 0
T237 0 15 0 0
T238 0 6 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 69558 0 0
T1 20302 2526 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 346 0 0
T60 0 286 0 0
T64 0 59 0 0
T80 0 2242 0 0
T118 0 793 0 0
T120 0 14 0 0
T236 0 1132 0 0
T237 0 467 0 0
T238 0 344 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 521 0 0
T1 20302 3 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 4 0 0
T60 0 4 0 0
T64 0 10 0 0
T80 0 4 0 0
T118 0 9 0 0
T120 0 4 0 0
T236 0 10 0 0
T237 0 15 0 0
T238 0 5 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions2121100.00
Logical2121100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT54,T1,T26
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT54,T1,T26
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T32,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T5,T6 VC_COV_UNR
1CoveredT1,T32,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T32,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT1,T26,T32
10CoveredT46,T54,T1
11CoveredT1,T32,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT1,T32,T8
01CoveredT11,T94,T96
10CoveredT32,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT1,T32,T8
01CoveredT1,T8,T9
10CoveredT32,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT1,T32,T8
1-CoveredT1,T8,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T1,T32,T8
DetectSt 168 Covered T1,T32,T8
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T1,T32,T8


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T1,T32,T8
DebounceSt->IdleSt 163 Covered T32,T8,T11
DetectSt->IdleSt 186 Covered T32,T11,T94
DetectSt->StableSt 191 Covered T1,T32,T8
IdleSt->DebounceSt 148 Covered T1,T32,T8
StableSt->IdleSt 206 Covered T1,T32,T8



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 11 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T1,T32,T8
0 1 Covered T1,T32,T8
0 0 Excluded T4,T5,T6 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T32,T8
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T1,T32,T8
IdleSt 0 - - - - - - Covered T4,T5,T6
DebounceSt - 1 - - - - - Covered T32,T60
DebounceSt - 0 1 1 - - - Covered T1,T32,T8
DebounceSt - 0 1 0 - - - Covered T8,T11,T13
DebounceSt - 0 0 - - - - Covered T1,T32,T8
DetectSt - - - - 1 - - Covered T32,T11,T94
DetectSt - - - - 0 1 - Covered T1,T32,T8
DetectSt - - - - 0 0 - Covered T1,T32,T8
StableSt - - - - - - 1 Covered T1,T32,T8
StableSt - - - - - - 0 Covered T1,T32,T8
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7872393 939 0 0
CntIncr_A 7872393 46370 0 0
CntNoWrap_A 7872393 7181722 0 0
DetectStDropOut_A 7872393 58 0 0
DetectedOut_A 7872393 16607 0 0
DetectedPulseOut_A 7872393 368 0 0
DisabledIdleSt_A 7872393 6815299 0 0
DisabledNoDetection_A 7872393 6817051 0 0
EnterDebounceSt_A 7872393 509 0 0
EnterDetectSt_A 7872393 431 0 0
EnterStableSt_A 7872393 368 0 0
PulseIsPulse_A 7872393 368 0 0
StayInStableSt 7872393 16193 0 0
gen_high_level_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_not_sticky_sva.StableStDropOut_A 7872393 319 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 939 0 0
T1 20302 12 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 13 0 0
T9 0 6 0 0
T11 0 21 0 0
T13 0 3 0 0
T16 0 18 0 0
T17 0 3 0 0
T19 0 2 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 8 0 0
T94 0 16 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 46370 0 0
T1 20302 504 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 1231 0 0
T9 0 237 0 0
T11 0 761 0 0
T13 0 136 0 0
T16 0 946 0 0
T17 0 45 0 0
T19 0 40 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 166 0 0
T94 0 1192 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7181722 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 58 0 0
T11 28461 9 0 0
T12 1104 0 0 0
T13 39966 0 0 0
T14 736 0 0 0
T15 8882 0 0 0
T65 5139 0 0 0
T67 1593 0 0 0
T94 0 6 0 0
T96 0 10 0 0
T97 0 1 0 0
T100 0 9 0 0
T101 0 1 0 0
T102 0 6 0 0
T103 0 8 0 0
T104 0 2 0 0
T105 0 6 0 0
T107 414 0 0 0
T108 858 0 0 0
T109 422 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 16607 0 0
T1 20302 388 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 38 0 0
T9 0 159 0 0
T13 0 36 0 0
T16 0 307 0 0
T17 0 4 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 110 0 0
T58 0 57 0 0
T95 0 28 0 0
T118 0 152 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 368 0 0
T1 20302 6 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 6 0 0
T9 0 3 0 0
T13 0 1 0 0
T16 0 8 0 0
T17 0 1 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 1 0 0
T58 0 9 0 0
T95 0 2 0 0
T118 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6815299 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6817051 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 509 0 0
T1 20302 6 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 7 0 0
T9 0 3 0 0
T11 0 12 0 0
T13 0 2 0 0
T16 0 10 0 0
T17 0 2 0 0
T19 0 2 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 5 0 0
T94 0 10 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 431 0 0
T1 20302 6 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 6 0 0
T9 0 3 0 0
T11 0 9 0 0
T13 0 1 0 0
T16 0 8 0 0
T17 0 1 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 3 0 0
T58 0 9 0 0
T94 0 6 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 368 0 0
T1 20302 6 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 6 0 0
T9 0 3 0 0
T13 0 1 0 0
T16 0 8 0 0
T17 0 1 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 1 0 0
T58 0 9 0 0
T95 0 2 0 0
T118 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 368 0 0
T1 20302 6 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 6 0 0
T9 0 3 0 0
T13 0 1 0 0
T16 0 8 0 0
T17 0 1 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 1 0 0
T58 0 9 0 0
T95 0 2 0 0
T118 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 16193 0 0
T1 20302 382 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 32 0 0
T9 0 155 0 0
T13 0 35 0 0
T16 0 299 0 0
T17 0 3 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 0 109 0 0
T58 0 48 0 0
T95 0 26 0 0
T118 0 148 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 319 0 0
T1 20302 6 0 0
T2 500 0 0 0
T3 12676 0 0 0
T8 0 6 0 0
T9 0 2 0 0
T13 0 1 0 0
T16 0 8 0 0
T17 0 1 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T58 0 9 0 0
T59 0 5 0 0
T80 0 6 0 0
T95 0 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT54,T1,T3
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT54,T1,T3
10CoveredT1,T3,T32
11CoveredT54,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT54,T1,T3
01CoveredT54,T32,T38
10CoveredT1,T32,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T32,T15
01CoveredT3,T32,T15
10CoveredT60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T32,T15
1-CoveredT3,T32,T15

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T54,T1,T3
DetectSt 168 Covered T54,T1,T3
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T3,T32,T15


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T54,T1,T3
DebounceSt->IdleSt 163 Covered T32,T64,T60
DetectSt->IdleSt 186 Covered T54,T1,T32
DetectSt->StableSt 191 Covered T3,T32,T15
IdleSt->DebounceSt 148 Covered T54,T1,T3
StableSt->IdleSt 206 Covered T3,T32,T15



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T54,T1,T3
0 1 Covered T54,T1,T3
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T54,T1,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T54,T1,T3
IdleSt 0 - - - - - - Covered T54,T1,T3
DebounceSt - 1 - - - - - Covered T32,T60
DebounceSt - 0 1 1 - - - Covered T54,T1,T3
DebounceSt - 0 1 0 - - - Covered T32,T64,T60
DebounceSt - 0 0 - - - - Covered T54,T1,T3
DetectSt - - - - 1 - - Covered T54,T1,T32
DetectSt - - - - 0 1 - Covered T3,T32,T15
DetectSt - - - - 0 0 - Covered T54,T1,T3
StableSt - - - - - - 1 Covered T3,T32,T15
StableSt - - - - - - 0 Covered T3,T32,T15
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7872393 2985 0 0
CntIncr_A 7872393 100103 0 0
CntNoWrap_A 7872393 7179676 0 0
DetectStDropOut_A 7872393 538 0 0
DetectedOut_A 7872393 75536 0 0
DetectedPulseOut_A 7872393 756 0 0
DisabledIdleSt_A 7872393 6746092 0 0
DisabledNoDetection_A 7872393 6748353 0 0
EnterDebounceSt_A 7872393 1516 0 0
EnterDetectSt_A 7872393 1471 0 0
EnterStableSt_A 7872393 756 0 0
PulseIsPulse_A 7872393 756 0 0
StayInStableSt 7872393 74670 0 0
gen_high_event_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_high_level_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_not_sticky_sva.StableStDropOut_A 7872393 645 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 2985 0 0
T1 20302 18 0 0
T2 500 0 0 0
T3 12676 20 0 0
T15 0 44 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 16 0 0
T38 0 18 0 0
T54 4766 26 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 16 0 0
T65 0 6 0 0
T66 0 32 0 0
T69 0 24 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 100103 0 0
T1 20302 554 0 0
T2 500 0 0 0
T3 12676 370 0 0
T15 0 880 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 423 0 0
T38 0 509 0 0
T54 4766 553 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 675 0 0
T65 0 148 0 0
T66 0 746 0 0
T69 0 692 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7179676 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 538 0 0
T1 20302 0 0 0
T2 500 0 0 0
T3 12676 0 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 1 0 0
T38 0 2 0 0
T54 4766 13 0 0
T56 522 0 0 0
T57 745 0 0 0
T60 0 1 0 0
T65 0 3 0 0
T66 0 16 0 0
T80 0 10 0 0
T98 0 5 0 0
T99 0 20 0 0
T239 0 12 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 75536 0 0
T3 12676 1404 0 0
T7 1582 0 0 0
T15 0 1723 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 361 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 315 0 0
T64 0 37 0 0
T118 0 585 0 0
T120 0 311 0 0
T236 0 1609 0 0
T237 0 617 0 0
T240 0 1915 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 756 0 0
T3 12676 10 0 0
T7 1582 0 0 0
T15 0 22 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 5 0 0
T64 0 5 0 0
T118 0 8 0 0
T120 0 12 0 0
T236 0 22 0 0
T237 0 15 0 0
T240 0 25 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6746092 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6748353 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 1516 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 10 0 0
T15 0 22 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 9 0 0
T38 0 9 0 0
T54 4766 13 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 11 0 0
T65 0 3 0 0
T66 0 16 0 0
T69 0 12 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 1471 0 0
T1 20302 9 0 0
T2 500 0 0 0
T3 12676 10 0 0
T15 0 22 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 7 0 0
T38 0 9 0 0
T54 4766 13 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 5 0 0
T65 0 3 0 0
T66 0 16 0 0
T69 0 12 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 756 0 0
T3 12676 10 0 0
T7 1582 0 0 0
T15 0 22 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 5 0 0
T64 0 5 0 0
T118 0 8 0 0
T120 0 12 0 0
T236 0 22 0 0
T237 0 15 0 0
T240 0 25 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 756 0 0
T3 12676 10 0 0
T7 1582 0 0 0
T15 0 22 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 5 0 0
T64 0 5 0 0
T118 0 8 0 0
T120 0 12 0 0
T236 0 22 0 0
T237 0 15 0 0
T240 0 25 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 74670 0 0
T3 12676 1391 0 0
T7 1582 0 0 0
T15 0 1700 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 356 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 310 0 0
T64 0 32 0 0
T118 0 574 0 0
T120 0 297 0 0
T236 0 1585 0 0
T237 0 602 0 0
T240 0 1890 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 645 0 0
T3 12676 7 0 0
T7 1582 0 0 0
T15 0 21 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 4 0 0
T64 0 5 0 0
T118 0 5 0 0
T120 0 10 0 0
T236 0 20 0 0
T237 0 15 0 0
T240 0 25 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions2121100.00
Logical2121100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT54,T1,T26
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT54,T1,T26
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT26,T3,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T5,T6 VC_COV_UNR
1CoveredT26,T3,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT26,T3,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT26,T3,T32
10CoveredT46,T54,T1
11CoveredT26,T3,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT26,T3,T32
01CoveredT9,T11,T241
10CoveredT32,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT26,T3,T32
01CoveredT26,T3,T13
10CoveredT32,T60,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT26,T3,T32
1-CoveredT26,T3,T13

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T26,T3,T32
DetectSt 168 Covered T26,T3,T32
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T26,T3,T32


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T26,T3,T32
DebounceSt->IdleSt 163 Covered T26,T32,T11
DetectSt->IdleSt 186 Covered T32,T9,T11
DetectSt->StableSt 191 Covered T26,T3,T32
IdleSt->DebounceSt 148 Covered T26,T3,T32
StableSt->IdleSt 206 Covered T26,T3,T32



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 11 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T26,T3,T32
0 1 Covered T26,T3,T32
0 0 Excluded T4,T5,T6 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T26,T3,T32
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T26,T3,T32
IdleSt 0 - - - - - - Covered T4,T5,T6
DebounceSt - 1 - - - - - Covered T32,T60
DebounceSt - 0 1 1 - - - Covered T26,T3,T32
DebounceSt - 0 1 0 - - - Covered T26,T11,T16
DebounceSt - 0 0 - - - - Covered T26,T3,T32
DetectSt - - - - 1 - - Covered T32,T9,T11
DetectSt - - - - 0 1 - Covered T26,T3,T32
DetectSt - - - - 0 0 - Covered T26,T3,T32
StableSt - - - - - - 1 Covered T26,T3,T32
StableSt - - - - - - 0 Covered T26,T3,T32
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7872393 864 0 0
CntIncr_A 7872393 52007 0 0
CntNoWrap_A 7872393 7181797 0 0
DetectStDropOut_A 7872393 36 0 0
DetectedOut_A 7872393 15639 0 0
DetectedPulseOut_A 7872393 367 0 0
DisabledIdleSt_A 7872393 6793639 0 0
DisabledNoDetection_A 7872393 6795445 0 0
EnterDebounceSt_A 7872393 457 0 0
EnterDetectSt_A 7872393 408 0 0
EnterStableSt_A 7872393 367 0 0
PulseIsPulse_A 7872393 367 0 0
StayInStableSt 7872393 15244 0 0
gen_high_level_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_not_sticky_sva.StableStDropOut_A 7872393 334 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 864 0 0
T3 12676 6 0 0
T7 1582 0 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 13 0 0
T13 0 6 0 0
T15 0 2 0 0
T16 0 26 0 0
T26 17675 9 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 8 0 0
T33 487 0 0 0
T94 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 52007 0 0
T3 12676 201 0 0
T7 1582 0 0 0
T9 0 129 0 0
T10 0 165 0 0
T11 0 479 0 0
T13 0 261 0 0
T15 0 38 0 0
T16 0 1686 0 0
T26 17675 325 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 181 0 0
T33 487 0 0 0
T94 0 130 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7181797 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 36 0 0
T9 25340 1 0 0
T10 8317 0 0 0
T11 28461 6 0 0
T36 524 0 0 0
T37 1015 0 0 0
T38 13408 0 0 0
T66 4967 0 0 0
T91 0 2 0 0
T107 414 0 0 0
T125 0 2 0 0
T187 826 0 0 0
T188 427 0 0 0
T241 0 5 0 0
T242 0 2 0 0
T243 0 4 0 0
T244 0 3 0 0
T245 0 1 0 0
T246 0 2 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 15639 0 0
T3 12676 62 0 0
T7 1582 0 0 0
T10 0 32 0 0
T13 0 74 0 0
T15 0 75 0 0
T16 0 142 0 0
T26 17675 192 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 110 0 0
T33 487 0 0 0
T58 0 428 0 0
T94 0 4 0 0
T135 0 4 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 367 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T10 0 1 0 0
T13 0 3 0 0
T15 0 1 0 0
T16 0 12 0 0
T26 17675 4 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 1 0 0
T33 487 0 0 0
T58 0 6 0 0
T94 0 1 0 0
T135 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6793639 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6795445 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 457 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 7 0 0
T13 0 3 0 0
T15 0 1 0 0
T16 0 14 0 0
T26 17675 5 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T94 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 408 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 6 0 0
T13 0 3 0 0
T15 0 1 0 0
T16 0 12 0 0
T26 17675 4 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 3 0 0
T33 487 0 0 0
T94 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 367 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T10 0 1 0 0
T13 0 3 0 0
T15 0 1 0 0
T16 0 12 0 0
T26 17675 4 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 1 0 0
T33 487 0 0 0
T58 0 6 0 0
T94 0 1 0 0
T135 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 367 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T10 0 1 0 0
T13 0 3 0 0
T15 0 1 0 0
T16 0 12 0 0
T26 17675 4 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 1 0 0
T33 487 0 0 0
T58 0 6 0 0
T94 0 1 0 0
T135 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 15244 0 0
T3 12676 59 0 0
T7 1582 0 0 0
T10 0 30 0 0
T13 0 71 0 0
T15 0 74 0 0
T16 0 130 0 0
T26 17675 188 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 109 0 0
T33 487 0 0 0
T58 0 422 0 0
T94 0 3 0 0
T135 0 3 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 334 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T13 0 3 0 0
T15 0 1 0 0
T16 0 12 0 0
T26 17675 4 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 0 0 0
T33 487 0 0 0
T58 0 6 0 0
T94 0 1 0 0
T96 0 7 0 0
T97 0 2 0 0
T135 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT54,T1,T3
1CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT54,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT54,T1,T3
10CoveredT1,T3,T32
11CoveredT54,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT54,T1,T3
01CoveredT54,T1,T32
10CoveredT1,T32,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T32,T64
01CoveredT3,T32,T65
10CoveredT60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T32,T64
1-CoveredT3,T32,T65

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T54,T1,T3
DetectSt 168 Covered T54,T1,T3
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T3,T32,T65


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T54,T1,T3
DebounceSt->IdleSt 163 Covered T32,T64,T60
DetectSt->IdleSt 186 Covered T54,T1,T32
DetectSt->StableSt 191 Covered T3,T32,T65
IdleSt->DebounceSt 148 Covered T54,T1,T3
StableSt->IdleSt 206 Covered T3,T32,T65



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T54,T1,T3
0 1 Covered T54,T1,T3
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T54,T1,T3
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T54,T1,T3
IdleSt 0 - - - - - - Covered T54,T1,T3
DebounceSt - 1 - - - - - Covered T32,T60
DebounceSt - 0 1 1 - - - Covered T54,T1,T3
DebounceSt - 0 1 0 - - - Covered T32,T64,T60
DebounceSt - 0 0 - - - - Covered T54,T1,T3
DetectSt - - - - 1 - - Covered T54,T1,T32
DetectSt - - - - 0 1 - Covered T3,T32,T65
DetectSt - - - - 0 0 - Covered T54,T1,T3
StableSt - - - - - - 1 Covered T3,T32,T65
StableSt - - - - - - 0 Covered T3,T32,T64
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7872393 2961 0 0
CntIncr_A 7872393 96962 0 0
CntNoWrap_A 7872393 7179700 0 0
DetectStDropOut_A 7872393 537 0 0
DetectedOut_A 7872393 69977 0 0
DetectedPulseOut_A 7872393 747 0 0
DisabledIdleSt_A 7872393 6750829 0 0
DisabledNoDetection_A 7872393 6753074 0 0
EnterDebounceSt_A 7872393 1505 0 0
EnterDetectSt_A 7872393 1457 0 0
EnterStableSt_A 7872393 747 0 0
PulseIsPulse_A 7872393 747 0 0
StayInStableSt 7872393 69104 0 0
gen_high_event_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_high_level_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_not_sticky_sva.StableStDropOut_A 7872393 620 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 2961 0 0
T1 20302 24 0 0
T2 500 0 0 0
T3 12676 6 0 0
T15 0 42 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 16 0 0
T38 0 68 0 0
T54 4766 52 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 21 0 0
T65 0 14 0 0
T66 0 22 0 0
T69 0 56 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 96962 0 0
T1 20302 734 0 0
T2 500 0 0 0
T3 12676 87 0 0
T15 0 1222 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 397 0 0
T38 0 1932 0 0
T54 4766 1121 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 999 0 0
T65 0 343 0 0
T66 0 515 0 0
T69 0 1568 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7179700 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 537 0 0
T1 20302 7 0 0
T2 500 0 0 0
T3 12676 0 0 0
T15 0 14 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 1 0 0
T38 0 12 0 0
T54 4766 26 0 0
T56 522 0 0 0
T57 745 0 0 0
T60 0 1 0 0
T65 0 6 0 0
T66 0 11 0 0
T98 0 20 0 0
T99 0 13 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 69977 0 0
T3 12676 276 0 0
T7 1582 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 329 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 351 0 0
T64 0 9 0 0
T65 0 1 0 0
T69 0 2286 0 0
T80 0 1027 0 0
T118 0 1632 0 0
T236 0 2493 0 0
T237 0 2189 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 747 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 5 0 0
T64 0 5 0 0
T65 0 1 0 0
T69 0 28 0 0
T80 0 8 0 0
T118 0 26 0 0
T236 0 27 0 0
T237 0 31 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6750829 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6753074 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 1505 0 0
T1 20302 12 0 0
T2 500 0 0 0
T3 12676 3 0 0
T15 0 21 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 9 0 0
T38 0 34 0 0
T54 4766 26 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 17 0 0
T65 0 7 0 0
T66 0 11 0 0
T69 0 28 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 1457 0 0
T1 20302 12 0 0
T2 500 0 0 0
T3 12676 3 0 0
T15 0 21 0 0
T25 421 0 0 0
T26 17675 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T32 0 7 0 0
T38 0 34 0 0
T54 4766 26 0 0
T56 522 0 0 0
T57 745 0 0 0
T64 0 5 0 0
T65 0 7 0 0
T66 0 11 0 0
T69 0 28 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 747 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 5 0 0
T64 0 5 0 0
T65 0 1 0 0
T69 0 28 0 0
T80 0 8 0 0
T118 0 26 0 0
T236 0 27 0 0
T237 0 31 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 747 0 0
T3 12676 3 0 0
T7 1582 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 5 0 0
T64 0 5 0 0
T65 0 1 0 0
T69 0 28 0 0
T80 0 8 0 0
T118 0 26 0 0
T236 0 27 0 0
T237 0 31 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 69104 0 0
T3 12676 272 0 0
T7 1582 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 324 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 346 0 0
T64 0 4 0 0
T69 0 2253 0 0
T80 0 1015 0 0
T118 0 1601 0 0
T236 0 2458 0 0
T237 0 2156 0 0
T239 0 1503 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 620 0 0
T3 12676 2 0 0
T7 1582 0 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T34 1035 0 0 0
T60 0 4 0 0
T64 0 5 0 0
T65 0 1 0 0
T69 0 23 0 0
T80 0 4 0 0
T118 0 21 0 0
T236 0 19 0 0
T237 0 29 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions2121100.00
Logical2121100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT54,T1,T26
1CoveredT4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT54,T1,T26
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT26,T3,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT4,T5,T6 VC_COV_UNR
1CoveredT26,T3,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT26,T3,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT26,T3,T32
10CoveredT46,T54,T1
11CoveredT26,T3,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT26,T3,T32
01CoveredT26,T16,T135
10CoveredT32,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T32,T8
01CoveredT3,T8,T9
10CoveredT32,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T32,T8
1-CoveredT3,T8,T9

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T26,T3,T32
DetectSt 168 Covered T26,T3,T32
IdleSt 163 Covered T4,T5,T6
StableSt 191 Covered T3,T32,T8


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T26,T3,T32
DebounceSt->IdleSt 163 Covered T26,T32,T11
DetectSt->IdleSt 186 Covered T26,T32,T10
DetectSt->StableSt 191 Covered T3,T32,T8
IdleSt->DebounceSt 148 Covered T26,T3,T32
StableSt->IdleSt 206 Covered T3,T32,T8



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 11 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T26,T3,T32
0 1 Covered T26,T3,T32
0 0 Excluded T4,T5,T6 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T26,T3,T32
0 Covered T4,T5,T6


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T26,T3,T32
IdleSt 0 - - - - - - Covered T4,T5,T6
DebounceSt - 1 - - - - - Covered T32,T60
DebounceSt - 0 1 1 - - - Covered T26,T3,T32
DebounceSt - 0 1 0 - - - Covered T26,T11,T94
DebounceSt - 0 0 - - - - Covered T26,T3,T32
DetectSt - - - - 1 - - Covered T26,T32,T16
DetectSt - - - - 0 1 - Covered T3,T32,T8
DetectSt - - - - 0 0 - Covered T26,T3,T32
StableSt - - - - - - 1 Covered T3,T32,T8
StableSt - - - - - - 0 Covered T3,T32,T8
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7872393 761 0 0
CntIncr_A 7872393 41745 0 0
CntNoWrap_A 7872393 7181900 0 0
DetectStDropOut_A 7872393 43 0 0
DetectedOut_A 7872393 14762 0 0
DetectedPulseOut_A 7872393 311 0 0
DisabledIdleSt_A 7872393 6795071 0 0
DisabledNoDetection_A 7872393 6796853 0 0
EnterDebounceSt_A 7872393 404 0 0
EnterDetectSt_A 7872393 360 0 0
EnterStableSt_A 7872393 311 0 0
PulseIsPulse_A 7872393 311 0 0
StayInStableSt 7872393 14418 0 0
gen_high_level_sva.HighLevelEvent_A 7872393 7185121 0 0
gen_not_sticky_sva.StableStDropOut_A 7872393 275 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 761 0 0
T3 12676 2 0 0
T7 1582 0 0 0
T8 0 8 0 0
T9 0 8 0 0
T10 0 3 0 0
T11 0 19 0 0
T13 0 2 0 0
T16 0 2 0 0
T26 17675 7 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 8 0 0
T33 487 0 0 0
T94 0 12 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 41745 0 0
T3 12676 53 0 0
T7 1582 0 0 0
T8 0 648 0 0
T9 0 401 0 0
T10 0 393 0 0
T11 0 651 0 0
T13 0 83 0 0
T16 0 142 0 0
T26 17675 401 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 149 0 0
T33 487 0 0 0
T94 0 802 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7181900 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 43 0 0
T3 12676 0 0 0
T7 1582 0 0 0
T16 0 1 0 0
T26 17675 3 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 0 0 0
T33 487 0 0 0
T100 0 1 0 0
T102 0 6 0 0
T125 0 2 0 0
T135 0 2 0 0
T206 0 1 0 0
T241 0 11 0 0
T247 0 5 0 0
T248 0 5 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 14762 0 0
T3 12676 35 0 0
T7 1582 0 0 0
T8 0 137 0 0
T9 0 126 0 0
T10 0 21 0 0
T11 0 65 0 0
T13 0 8 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 109 0 0
T33 487 0 0 0
T34 1035 0 0 0
T58 0 224 0 0
T69 0 279 0 0
T94 0 63 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 311 0 0
T3 12676 1 0 0
T7 1582 0 0 0
T8 0 4 0 0
T9 0 4 0 0
T10 0 1 0 0
T11 0 9 0 0
T13 0 1 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 1 0 0
T33 487 0 0 0
T34 1035 0 0 0
T58 0 6 0 0
T69 0 5 0 0
T94 0 5 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6795071 0 0
T4 571 170 0 0
T5 891 490 0 0
T6 522 121 0 0
T42 427 26 0 0
T43 431 30 0 0
T44 569 168 0 0
T45 1016 615 0 0
T46 2176 172 0 0
T47 423 22 0 0
T48 608 207 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 6796853 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 404 0 0
T3 12676 1 0 0
T7 1582 0 0 0
T8 0 4 0 0
T9 0 4 0 0
T10 0 2 0 0
T11 0 10 0 0
T13 0 1 0 0
T16 0 1 0 0
T26 17675 4 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 5 0 0
T33 487 0 0 0
T94 0 7 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 360 0 0
T3 12676 1 0 0
T7 1582 0 0 0
T8 0 4 0 0
T9 0 4 0 0
T10 0 2 0 0
T11 0 9 0 0
T13 0 1 0 0
T16 0 1 0 0
T26 17675 3 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 3 0 0
T33 487 0 0 0
T94 0 5 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 311 0 0
T3 12676 1 0 0
T7 1582 0 0 0
T8 0 4 0 0
T9 0 4 0 0
T10 0 1 0 0
T11 0 9 0 0
T13 0 1 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 1 0 0
T33 487 0 0 0
T34 1035 0 0 0
T58 0 6 0 0
T69 0 5 0 0
T94 0 5 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 311 0 0
T3 12676 1 0 0
T7 1582 0 0 0
T8 0 4 0 0
T9 0 4 0 0
T10 0 1 0 0
T11 0 9 0 0
T13 0 1 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 1 0 0
T33 487 0 0 0
T34 1035 0 0 0
T58 0 6 0 0
T69 0 5 0 0
T94 0 5 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 14418 0 0
T3 12676 34 0 0
T7 1582 0 0 0
T8 0 133 0 0
T9 0 121 0 0
T10 0 20 0 0
T11 0 56 0 0
T13 0 7 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 108 0 0
T33 487 0 0 0
T34 1035 0 0 0
T58 0 218 0 0
T69 0 271 0 0
T94 0 58 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 7185121 0 0
T4 571 171 0 0
T5 891 491 0 0
T6 522 122 0 0
T42 427 27 0 0
T43 431 31 0 0
T44 569 169 0 0
T45 1016 616 0 0
T46 2176 176 0 0
T47 423 23 0 0
T48 608 208 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7872393 275 0 0
T3 12676 1 0 0
T7 1582 0 0 0
T8 0 4 0 0
T9 0 3 0 0
T10 0 1 0 0
T11 0 9 0 0
T13 0 1 0 0
T27 499 0 0 0
T28 1295 0 0 0
T29 522 0 0 0
T30 532 0 0 0
T31 409 0 0 0
T32 6847 0 0 0
T33 487 0 0 0
T34 1035 0 0 0
T58 0 6 0 0
T69 0 2 0 0
T94 0 5 0 0
T96 0 3 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%