Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T54,T1,T3
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T1,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T1,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T1,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T54,T1,T3
1	0	Covered	T1,T3,T32
1	1	Covered	T54,T1,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T54,T1,T3
0	1	Covered	T54,T1,T3
1	0	Covered	T1,T3,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T38,T15
0	1	Covered	T32,T38,T15
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T38,T15
1	-	Covered	T32,T38,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T54,T1,T3
DetectSt	168	Covered	T54,T1,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T32,T38,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T54,T1,T3
DebounceSt->IdleSt	163	Covered	T32,T64,T60
DetectSt->IdleSt	186	Covered	T54,T1,T3
DetectSt->StableSt	191	Covered	T32,T38,T15
IdleSt->DebounceSt	148	Covered	T54,T1,T3
StableSt->IdleSt	206	Covered	T32,T38,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T54,T1,T3
0	1	Covered	T54,T1,T3
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T54,T1,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T54,T1,T3
IdleSt	0	-	-	-	-	-	-	Covered	T54,T1,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T32,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T54,T1,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T64,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T54,T1,T3
DetectSt	-	-	-	-	1	-	-	Covered	T54,T1,T3
DetectSt	-	-	-	-	0	1	-	Covered	T32,T38,T15
DetectSt	-	-	-	-	0	0	-	Covered	T54,T1,T3
StableSt	-	-	-	-	-	-	1	Covered	T32,T38,T15
StableSt	-	-	-	-	-	-	0	Covered	T32,T38,T15
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	2857	0	0
CntIncr_A	7872393	93921	0	0
CntNoWrap_A	7872393	7179804	0	0
DetectStDropOut_A	7872393	474	0	0
DetectedOut_A	7872393	76684	0	0
DetectedPulseOut_A	7872393	773	0	0
DisabledIdleSt_A	7872393	6751360	0	0
DisabledNoDetection_A	7872393	6753601	0	0
EnterDebounceSt_A	7872393	1458	0	0
EnterDetectSt_A	7872393	1400	0	0
EnterStableSt_A	7872393	773	0	0
PulseIsPulse_A	7872393	773	0	0
StayInStableSt	7872393	75783	0	0
gen_high_event_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	645	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	2857	0	0
T1	20302	24	0	0
T2	500	0	0	0
T3	12676	18	0	0
T15	0	44	0	0
T25	421	0	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T32	0	16	0	0
T38	0	44	0	0
T54	4766	12	0	0
T56	522	0	0	0
T57	745	0	0	0
T64	0	17	0	0
T65	0	20	0	0
T66	0	22	0	0
T69	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	93921	0	0
T1	20302	729	0	0
T2	500	0	0	0
T3	12676	497	0	0
T15	0	946	0	0
T25	421	0	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T32	0	452	0	0
T38	0	1166	0	0
T54	4766	254	0	0
T56	522	0	0	0
T57	745	0	0	0
T64	0	781	0	0
T65	0	494	0	0
T66	0	517	0	0
T69	0	684	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7179804	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	474	0	0
T1	20302	8	0	0
T2	500	0	0	0
T3	12676	6	0	0
T25	421	0	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T32	0	1	0	0
T54	4766	6	0	0
T56	522	0	0	0
T57	745	0	0	0
T60	0	1	0	0
T65	0	10	0	0
T66	0	11	0	0
T98	0	10	0	0
T99	0	12	0	0
T239	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	76684	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T15	0	1657	0	0
T32	6847	345	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	0	1959	0	0
T60	0	286	0	0
T64	0	63	0	0
T69	0	1788	0	0
T80	0	559	0	0
T118	0	2140	0	0
T120	0	2012	0	0
T236	0	640	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	773	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T15	0	22	0	0
T32	6847	5	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	0	22	0	0
T60	0	5	0	0
T64	0	3	0	0
T69	0	12	0	0
T80	0	3	0	0
T118	0	30	0	0
T120	0	27	0	0
T236	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6751360	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6753601	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1458	0	0
T1	20302	12	0	0
T2	500	0	0	0
T3	12676	9	0	0
T15	0	22	0	0
T25	421	0	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T32	0	9	0	0
T38	0	22	0	0
T54	4766	6	0	0
T56	522	0	0	0
T57	745	0	0	0
T64	0	15	0	0
T65	0	10	0	0
T66	0	11	0	0
T69	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	1400	0	0
T1	20302	12	0	0
T2	500	0	0	0
T3	12676	9	0	0
T15	0	22	0	0
T25	421	0	0	0
T26	17675	0	0	0
T27	499	0	0	0
T28	1295	0	0	0
T32	0	7	0	0
T38	0	22	0	0
T54	4766	6	0	0
T56	522	0	0	0
T57	745	0	0	0
T64	0	3	0	0
T65	0	10	0	0
T66	0	11	0	0
T69	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	773	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T15	0	22	0	0
T32	6847	5	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	0	22	0	0
T60	0	5	0	0
T64	0	3	0	0
T69	0	12	0	0
T80	0	3	0	0
T118	0	30	0	0
T120	0	27	0	0
T236	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	773	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T15	0	22	0	0
T32	6847	5	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	0	22	0	0
T60	0	5	0	0
T64	0	3	0	0
T69	0	12	0	0
T80	0	3	0	0
T118	0	30	0	0
T120	0	27	0	0
T236	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	75783	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T15	0	1634	0	0
T32	6847	340	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	0	1934	0	0
T60	0	281	0	0
T64	0	60	0	0
T69	0	1774	0	0
T80	0	554	0	0
T118	0	2106	0	0
T120	0	1983	0	0
T236	0	628	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	645	0	0
T7	1582	0	0	0
T8	28357	0	0	0
T9	25340	0	0	0
T10	8317	0	0	0
T15	0	21	0	0
T32	6847	5	0	0
T33	487	0	0	0
T34	1035	0	0	0
T35	493	0	0	0
T36	524	0	0	0
T37	1015	0	0	0
T38	0	19	0	0
T60	0	5	0	0
T64	0	3	0	0
T69	0	10	0	0
T80	0	1	0	0
T118	0	26	0	0
T120	0	25	0	0
T236	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T54,T1,T26
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T54,T1,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T32,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T32,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T32,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T32,T8
1	0	Covered	T46,T54,T1
1	1	Covered	T26,T32,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T32,T8
0	1	Covered	T16,T135,T97
1	0	Covered	T32,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T32,T8
0	1	Covered	T26,T8,T9
1	0	Covered	T32

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T26,T32,T8
1	-	Covered	T26,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T32,T8
DetectSt	168	Covered	T26,T32,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T26,T32,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T32,T8
DebounceSt->IdleSt	163	Covered	T26,T32,T11
DetectSt->IdleSt	186	Covered	T32,T9,T16
DetectSt->StableSt	191	Covered	T26,T32,T8
IdleSt->DebounceSt	148	Covered	T26,T32,T8
StableSt->IdleSt	206	Covered	T26,T32,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T32,T8
0	1	Covered	T26,T32,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T32,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T32,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T32,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T32,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T11,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T32,T8
DetectSt	-	-	-	-	1	-	-	Covered	T32,T16,T135
DetectSt	-	-	-	-	0	1	-	Covered	T26,T32,T8
DetectSt	-	-	-	-	0	0	-	Covered	T26,T32,T8
StableSt	-	-	-	-	-	-	1	Covered	T26,T32,T8
StableSt	-	-	-	-	-	-	0	Covered	T26,T32,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7872393	878	0	0
CntIncr_A	7872393	48462	0	0
CntNoWrap_A	7872393	7181783	0	0
DetectStDropOut_A	7872393	46	0	0
DetectedOut_A	7872393	18188	0	0
DetectedPulseOut_A	7872393	366	0	0
DisabledIdleSt_A	7872393	6779138	0	0
DisabledNoDetection_A	7872393	6780907	0	0
EnterDebounceSt_A	7872393	463	0	0
EnterDetectSt_A	7872393	417	0	0
EnterStableSt_A	7872393	366	0	0
PulseIsPulse_A	7872393	366	0	0
StayInStableSt	7872393	17799	0	0
gen_high_level_sva.HighLevelEvent_A	7872393	7185121	0	0
gen_not_sticky_sva.StableStDropOut_A	7872393	340	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	878	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	6	0	0
T9	0	5	0	0
T11	0	13	0	0
T13	0	2	0	0
T15	0	2	0	0
T16	0	6	0	0
T26	17675	5	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	8	0	0
T33	487	0	0	0
T38	0	6	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	48462	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	519	0	0
T9	0	387	0	0
T11	0	405	0	0
T13	0	134	0	0
T15	0	72	0	0
T16	0	429	0	0
T26	17675	227	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	166	0	0
T33	487	0	0	0
T38	0	279	0	0
T94	0	129	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7181783	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	46	0	0
T16	30851	3	0	0
T17	4850	0	0	0
T18	3247	0	0	0
T19	9761	0	0	0
T68	694	0	0	0
T94	15702	0	0	0
T97	0	7	0	0
T103	0	1	0	0
T134	522	0	0	0
T135	0	5	0	0
T204	523	0	0	0
T211	0	1	0	0
T246	0	1	0	0
T249	0	1	0	0
T250	0	2	0	0
T251	0	6	0	0
T252	0	7	0	0
T253	402	0	0	0
T254	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	18188	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	69	0	0
T9	0	9	0	0
T11	0	74	0	0
T13	0	17	0	0
T15	0	41	0	0
T26	17675	57	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	109	0	0
T33	487	0	0	0
T38	0	133	0	0
T69	0	458	0	0
T94	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	366	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	3	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	17675	2	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T33	487	0	0	0
T38	0	3	0	0
T69	0	8	0	0
T94	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6779138	0	0
T4	571	170	0	0
T5	891	490	0	0
T6	522	121	0	0
T42	427	26	0	0
T43	431	30	0	0
T44	569	168	0	0
T45	1016	615	0	0
T46	2176	172	0	0
T47	423	22	0	0
T48	608	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	6780907	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	463	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	3	0	0
T9	0	3	0	0
T11	0	7	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	3	0	0
T26	17675	3	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	5	0	0
T33	487	0	0	0
T38	0	3	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	417	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	3	0	0
T9	0	3	0	0
T11	0	6	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	3	0	0
T26	17675	2	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	3	0	0
T33	487	0	0	0
T38	0	3	0	0
T94	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	366	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	3	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	17675	2	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T33	487	0	0	0
T38	0	3	0	0
T69	0	8	0	0
T94	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	366	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	3	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	17675	2	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	1	0	0
T33	487	0	0	0
T38	0	3	0	0
T69	0	8	0	0
T94	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	17799	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	66	0	0
T9	0	7	0	0
T11	0	68	0	0
T13	0	16	0	0
T15	0	40	0	0
T26	17675	55	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	108	0	0
T33	487	0	0	0
T38	0	127	0	0
T69	0	450	0	0
T94	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	7185121	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7872393	340	0	0
T3	12676	0	0	0
T7	1582	0	0	0
T8	0	3	0	0
T9	0	2	0	0
T11	0	6	0	0
T13	0	1	0	0
T15	0	1	0	0
T26	17675	2	0	0
T27	499	0	0	0
T28	1295	0	0	0
T29	522	0	0	0
T30	532	0	0	0
T31	409	0	0	0
T32	6847	0	0	0
T33	487	0	0	0
T58	0	4	0	0
T69	0	8	0	0
T94	0	1	0	0
T96	0	1	0	0