Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1253150054	10985	0	0
auto_block_debounce_ctl_rd_A	1253150054	2171	0	0
auto_block_out_ctl_rd_A	1253150054	3137	0	0
com_det_ctl_0_rd_A	1253150054	3762	0	0
com_det_ctl_1_rd_A	1253150054	3684	0	0
com_det_ctl_2_rd_A	1253150054	3743	0	0
com_det_ctl_3_rd_A	1253150054	3657	0	0
com_out_ctl_0_rd_A	1253150054	4461	0	0
com_out_ctl_1_rd_A	1253150054	4648	0	0
com_out_ctl_2_rd_A	1253150054	4357	0	0
com_out_ctl_3_rd_A	1253150054	4407	0	0
com_pre_det_ctl_0_rd_A	1253150054	1595	0	0
com_pre_det_ctl_1_rd_A	1253150054	1506	0	0
com_pre_det_ctl_2_rd_A	1253150054	1526	0	0
com_pre_det_ctl_3_rd_A	1253150054	1572	0	0
com_pre_sel_ctl_0_rd_A	1253150054	4621	0	0
com_pre_sel_ctl_1_rd_A	1253150054	4951	0	0
com_pre_sel_ctl_2_rd_A	1253150054	4827	0	0
com_pre_sel_ctl_3_rd_A	1253150054	4635	0	0
com_sel_ctl_0_rd_A	1253150054	4878	0	0
com_sel_ctl_1_rd_A	1253150054	4878	0	0
com_sel_ctl_2_rd_A	1253150054	4901	0	0
com_sel_ctl_3_rd_A	1253150054	4529	0	0
ec_rst_ctl_rd_A	1253150054	2379	0	0
intr_enable_rd_A	1253150054	2052	0	0
key_intr_ctl_rd_A	1253150054	5129	0	0
key_intr_debounce_ctl_rd_A	1253150054	1562	0	0
key_invert_ctl_rd_A	1253150054	6252	0	0
pin_allowed_ctl_rd_A	1253150054	7818	0	0
pin_out_ctl_rd_A	1253150054	5433	0	0
pin_out_value_rd_A	1253150054	5321	0	0
regwen_rd_A	1253150054	1621	0	0
ulp_ac_debounce_ctl_rd_A	1253150054	1627	0	0
ulp_ctl_rd_A	1253150054	1610	0	0
ulp_lid_debounce_ctl_rd_A	1253150054	1753	0	0
ulp_pwrb_debounce_ctl_rd_A	1253150054	1696	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	10985	0	0
T8	342864	18	0	0
T9	590258	23	0	0
T10	411727	12	0	0
T13	0	2	0	0
T17	0	2	0	0
T19	0	17	0	0
T21	0	11	0	0
T35	121032	0	0	0
T36	125736	0	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T59	0	11	0	0
T66	149015	0	0	0
T159	0	5	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T281	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2171	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T10	0	34	0	0
T13	0	1	0	0
T19	0	31	0	0
T25	209071	0	0	0
T48	292193	12	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0
T282	0	10	0	0
T283	0	9	0	0
T284	0	8	0	0
T285	0	2	0	0
T286	0	13	0	0
T287	0	19	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	3137	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T10	0	44	0	0
T13	0	13	0	0
T19	0	25	0	0
T25	209071	0	0	0
T48	292193	5	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0
T282	0	1	0	0
T283	0	11	0	0
T284	0	5	0	0
T285	0	17	0	0
T286	0	10	0	0
T288	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	3762	0	0
T3	608422	54	0	0
T7	246334	0	0	0
T10	0	37	0	0
T11	0	62	0	0
T13	0	11	0	0
T19	0	12	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	46	0	0
T135	0	55	0	0
T156	0	78	0	0
T236	0	32	0	0
T289	0	46	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	3684	0	0
T3	608422	45	0	0
T7	246334	0	0	0
T10	0	37	0	0
T11	0	78	0	0
T13	0	19	0	0
T19	0	12	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	62	0	0
T135	0	54	0	0
T156	0	62	0	0
T236	0	40	0	0
T289	0	15	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	3743	0	0
T3	608422	39	0	0
T7	246334	0	0	0
T10	0	35	0	0
T11	0	71	0	0
T13	0	33	0	0
T19	0	12	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	59	0	0
T135	0	61	0	0
T156	0	43	0	0
T236	0	36	0	0
T289	0	32	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	3657	0	0
T3	608422	57	0	0
T7	246334	0	0	0
T10	0	26	0	0
T11	0	53	0	0
T13	0	9	0	0
T19	0	18	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	63	0	0
T135	0	70	0	0
T156	0	59	0	0
T236	0	47	0	0
T289	0	21	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4461	0	0
T3	608422	66	0	0
T7	246334	0	0	0
T10	0	35	0	0
T11	0	51	0	0
T13	0	26	0	0
T19	0	5	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	48	0	0
T135	0	87	0	0
T156	0	70	0	0
T236	0	27	0	0
T289	0	36	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4648	0	0
T3	608422	51	0	0
T7	246334	0	0	0
T10	0	35	0	0
T11	0	72	0	0
T13	0	26	0	0
T19	0	20	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	42	0	0
T135	0	52	0	0
T156	0	83	0	0
T236	0	34	0	0
T289	0	42	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4357	0	0
T3	608422	73	0	0
T7	246334	0	0	0
T10	0	24	0	0
T11	0	72	0	0
T13	0	36	0	0
T19	0	8	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	39	0	0
T135	0	66	0	0
T156	0	74	0	0
T236	0	38	0	0
T289	0	45	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4407	0	0
T3	608422	55	0	0
T7	246334	0	0	0
T10	0	39	0	0
T11	0	66	0	0
T13	0	14	0	0
T19	0	15	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	35	0	0
T135	0	67	0	0
T156	0	83	0	0
T236	0	38	0	0
T289	0	56	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1595	0	0
T10	411727	21	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	5	0	0
T19	0	21	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	8	0	0
T107	49673	0	0	0
T132	0	12	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T192	0	19	0	0
T202	0	5	0	0
T290	0	6	0	0
T291	0	16	0	0
T292	0	7	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1506	0	0
T10	411727	22	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	6	0	0
T19	0	18	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	1	0	0
T107	49673	0	0	0
T132	0	2	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T192	0	35	0	0
T202	0	5	0	0
T287	0	6	0	0
T290	0	21	0	0
T291	0	12	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1526	0	0
T10	411727	11	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	21	0	0
T19	0	12	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	19	0	0
T107	49673	0	0	0
T132	0	7	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T192	0	9	0	0
T287	0	11	0	0
T290	0	23	0	0
T291	0	8	0	0
T292	0	29	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1572	0	0
T10	411727	24	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	14	0	0
T19	0	10	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	6	0	0
T107	49673	0	0	0
T132	0	5	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T192	0	26	0	0
T202	0	18	0	0
T287	0	17	0	0
T290	0	18	0	0
T291	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4621	0	0
T3	608422	60	0	0
T7	246334	0	0	0
T10	0	16	0	0
T11	0	76	0	0
T13	0	19	0	0
T19	0	21	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	31	0	0
T135	0	70	0	0
T156	0	68	0	0
T236	0	23	0	0
T289	0	56	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4951	0	0
T3	608422	60	0	0
T7	246334	0	0	0
T10	0	28	0	0
T11	0	61	0	0
T13	0	27	0	0
T19	0	18	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	59	0	0
T135	0	54	0	0
T156	0	66	0	0
T236	0	56	0	0
T289	0	46	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4827	0	0
T3	608422	52	0	0
T7	246334	0	0	0
T10	0	27	0	0
T11	0	67	0	0
T13	0	28	0	0
T19	0	6	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	47	0	0
T135	0	66	0	0
T156	0	58	0	0
T236	0	48	0	0
T289	0	46	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4635	0	0
T3	608422	63	0	0
T7	246334	0	0	0
T10	0	31	0	0
T11	0	71	0	0
T13	0	21	0	0
T19	0	16	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	40	0	0
T135	0	71	0	0
T156	0	48	0	0
T236	0	45	0	0
T289	0	51	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4878	0	0
T3	608422	53	0	0
T7	246334	0	0	0
T10	0	9	0	0
T11	0	69	0	0
T13	0	6	0	0
T19	0	11	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	48	0	0
T135	0	75	0	0
T156	0	76	0	0
T236	0	45	0	0
T289	0	25	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4878	0	0
T3	608422	64	0	0
T7	246334	0	0	0
T10	0	20	0	0
T11	0	46	0	0
T13	0	35	0	0
T19	0	13	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	61	0	0
T135	0	67	0	0
T156	0	65	0	0
T236	0	39	0	0
T289	0	62	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4901	0	0
T3	608422	36	0	0
T7	246334	0	0	0
T10	0	26	0	0
T11	0	97	0	0
T13	0	30	0	0
T19	0	22	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	39	0	0
T135	0	55	0	0
T156	0	79	0	0
T236	0	30	0	0
T289	0	56	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	4529	0	0
T3	608422	71	0	0
T7	246334	0	0	0
T10	0	23	0	0
T11	0	57	0	0
T13	0	36	0	0
T19	0	16	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	0	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T38	0	23	0	0
T135	0	75	0	0
T156	0	60	0	0
T236	0	42	0	0
T289	0	50	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2379	0	0
T3	0	9	0	0
T4	28575	2	0	0
T5	445888	0	0	0
T6	221684	0	0	0
T10	0	38	0	0
T11	0	45	0	0
T13	0	32	0	0
T19	0	22	0	0
T33	0	3	0	0
T38	0	13	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	0	0	0
T45	78487	0	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T65	0	1	0	0
T135	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2052	0	0
T10	411727	14	0	0
T11	126651	15	0	0
T12	17373	0	0	0
T13	487461	34	0	0
T19	0	7	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	20	0	0
T107	49673	0	0	0
T132	0	20	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T202	0	9	0	0
T287	0	34	0	0
T290	0	16	0	0
T293	0	12	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	5129	0	0
T10	411727	28	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	32	0	0
T19	0	27	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T83	0	7	0	0
T90	0	22	0	0
T107	49673	0	0	0
T132	0	13	0	0
T146	0	7	0	0
T185	0	4	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T202	0	14	0	0
T287	0	10	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1562	0	0
T10	411727	21	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	21	0	0
T19	0	5	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	12	0	0
T107	49673	0	0	0
T132	0	23	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T192	0	30	0	0
T202	0	6	0	0
T290	0	8	0	0
T291	0	24	0	0
T292	0	18	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6252	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T3	608422	0	0	0
T10	0	91	0	0
T11	0	78	0	0
T13	0	57	0	0
T19	0	36	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	0	53	0	0
T54	238297	0	0	0
T55	59819	70	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T72	118199	0	0	0
T287	0	37	0	0
T294	0	77	0	0
T295	0	44	0	0
T296	0	67	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7818	0	0
T10	411727	19	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	80	0	0
T19	0	86	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T107	49673	0	0	0
T157	0	83	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T287	0	63	0	0
T297	0	60	0	0
T298	0	97	0	0
T299	0	73	0	0
T300	0	74	0	0
T301	0	51	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	5433	0	0
T10	411727	27	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	97	0	0
T19	0	78	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T107	49673	0	0	0
T157	0	87	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T287	0	56	0	0
T297	0	43	0	0
T298	0	78	0	0
T299	0	58	0	0
T300	0	46	0	0
T301	0	47	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	5321	0	0
T10	411727	27	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	107	0	0
T19	0	102	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T107	49673	0	0	0
T157	0	55	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T287	0	67	0	0
T297	0	85	0	0
T298	0	91	0	0
T299	0	98	0	0
T300	0	60	0	0
T301	0	47	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1621	0	0
T10	411727	9	0	0
T11	126651	0	0	0
T12	17373	0	0	0
T13	487461	0	0	0
T19	0	22	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	24	0	0
T107	49673	0	0	0
T132	0	15	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T192	0	19	0	0
T202	0	12	0	0
T287	0	15	0	0
T290	0	14	0	0
T291	0	20	0	0
T292	0	20	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1627	0	0
T10	411727	25	0	0
T11	126651	0	0	0
T12	17373	11	0	0
T13	487461	15	0	0
T19	0	24	0	0
T24	0	10	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T39	0	2	0	0
T66	149015	0	0	0
T107	49673	0	0	0
T121	0	3	0	0
T122	0	6	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T287	0	10	0	0
T293	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1610	0	0
T10	411727	16	0	0
T11	126651	0	0	0
T12	17373	16	0	0
T13	487461	2	0	0
T19	0	18	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T66	149015	0	0	0
T90	0	10	0	0
T107	49673	0	0	0
T122	0	6	0	0
T132	0	13	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T202	0	22	0	0
T287	0	13	0	0
T293	0	5	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1753	0	0
T10	411727	22	0	0
T11	126651	0	0	0
T12	17373	9	0	0
T13	487461	13	0	0
T19	0	29	0	0
T24	0	5	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T39	0	7	0	0
T66	149015	0	0	0
T107	49673	0	0	0
T121	0	6	0	0
T122	0	3	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T287	0	9	0	0
T293	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1696	0	0
T10	411727	14	0	0
T11	126651	0	0	0
T12	17373	5	0	0
T13	487461	7	0	0
T19	0	14	0	0
T24	0	16	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T39	0	7	0	0
T66	149015	0	0	0
T90	0	9	0	0
T107	49673	0	0	0
T121	0	7	0	0
T122	0	9	0	0
T187	396725	0	0	0
T188	51316	0	0	0
T287	0	7	0	0