| T389 |
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3930639936 |
|
|
Mar 07 02:02:30 PM PST 24 |
Mar 07 02:04:15 PM PST 24 |
76250140428 ps |
| T631 |
/workspace/coverage/default/44.sysrst_ctrl_smoke.678911578 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:12 PM PST 24 |
2108861196 ps |
| T192 |
/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1538258932 |
|
|
Mar 07 02:01:09 PM PST 24 |
Mar 07 02:02:33 PM PST 24 |
64605454588 ps |
| T632 |
/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2255189907 |
|
|
Mar 07 01:59:43 PM PST 24 |
Mar 07 01:59:51 PM PST 24 |
2613283873 ps |
| T633 |
/workspace/coverage/default/28.sysrst_ctrl_alert_test.933936957 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:10 PM PST 24 |
2041986222 ps |
| T634 |
/workspace/coverage/default/34.sysrst_ctrl_stress_all.3779589508 |
|
|
Mar 07 02:02:30 PM PST 24 |
Mar 07 02:02:37 PM PST 24 |
15374072478 ps |
| T292 |
/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2063517378 |
|
|
Mar 07 02:01:09 PM PST 24 |
Mar 07 02:02:25 PM PST 24 |
64285664532 ps |
| T172 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3644295968 |
|
|
Mar 07 02:00:09 PM PST 24 |
Mar 07 02:01:28 PM PST 24 |
48143660704 ps |
| T635 |
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1318128272 |
|
|
Mar 07 02:02:04 PM PST 24 |
Mar 07 02:02:18 PM PST 24 |
4726371440 ps |
| T636 |
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1623467971 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:18 PM PST 24 |
4279838674 ps |
| T637 |
/workspace/coverage/default/17.sysrst_ctrl_edge_detect.1665948118 |
|
|
Mar 07 01:59:57 PM PST 24 |
Mar 07 02:00:05 PM PST 24 |
3155312063 ps |
| T638 |
/workspace/coverage/default/32.sysrst_ctrl_alert_test.57666195 |
|
|
Mar 07 02:01:04 PM PST 24 |
Mar 07 02:01:05 PM PST 24 |
2108883543 ps |
| T639 |
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.319466258 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:14 PM PST 24 |
4398977163 ps |
| T640 |
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3058045199 |
|
|
Mar 07 02:02:10 PM PST 24 |
Mar 07 02:02:12 PM PST 24 |
2581885317 ps |
| T127 |
/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3313730864 |
|
|
Mar 07 01:59:40 PM PST 24 |
Mar 07 02:00:43 PM PST 24 |
55421537706 ps |
| T641 |
/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.4268061581 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:01:08 PM PST 24 |
3082983609 ps |
| T386 |
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3261877615 |
|
|
Mar 07 02:02:17 PM PST 24 |
Mar 07 02:03:59 PM PST 24 |
167958462692 ps |
| T642 |
/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.1039109466 |
|
|
Mar 07 02:01:21 PM PST 24 |
Mar 07 02:01:26 PM PST 24 |
2457385432 ps |
| T364 |
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.288499701 |
|
|
Mar 07 02:02:34 PM PST 24 |
Mar 07 02:07:01 PM PST 24 |
220121521567 ps |
| T643 |
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3699758177 |
|
|
Mar 07 02:02:25 PM PST 24 |
Mar 07 02:03:36 PM PST 24 |
109754110523 ps |
| T644 |
/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.894115226 |
|
|
Mar 07 02:01:17 PM PST 24 |
Mar 07 02:01:19 PM PST 24 |
2071064038 ps |
| T645 |
/workspace/coverage/default/1.sysrst_ctrl_smoke.2264255223 |
|
|
Mar 07 01:58:44 PM PST 24 |
Mar 07 01:58:48 PM PST 24 |
2120655584 ps |
| T646 |
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3022133636 |
|
|
Mar 07 02:01:57 PM PST 24 |
Mar 07 02:02:05 PM PST 24 |
2739846574 ps |
| T647 |
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3629741174 |
|
|
Mar 07 01:59:19 PM PST 24 |
Mar 07 01:59:21 PM PST 24 |
2536414975 ps |
| T648 |
/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1521352577 |
|
|
Mar 07 02:01:06 PM PST 24 |
Mar 07 02:01:09 PM PST 24 |
2060920158 ps |
| T344 |
/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1676062804 |
|
|
Mar 07 02:01:09 PM PST 24 |
Mar 07 02:02:56 PM PST 24 |
175148954125 ps |
| T649 |
/workspace/coverage/default/48.sysrst_ctrl_smoke.2829648701 |
|
|
Mar 07 02:02:08 PM PST 24 |
Mar 07 02:02:15 PM PST 24 |
2112790845 ps |
| T650 |
/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2834988681 |
|
|
Mar 07 02:01:16 PM PST 24 |
Mar 07 02:01:36 PM PST 24 |
244464796687 ps |
| T651 |
/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1898510337 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:01:20 PM PST 24 |
2629200656 ps |
| T652 |
/workspace/coverage/default/25.sysrst_ctrl_alert_test.1286434868 |
|
|
Mar 07 02:01:07 PM PST 24 |
Mar 07 02:01:13 PM PST 24 |
2013372229 ps |
| T653 |
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1878911256 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:40 PM PST 24 |
12141571865 ps |
| T654 |
/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3026525733 |
|
|
Mar 07 01:58:46 PM PST 24 |
Mar 07 01:59:45 PM PST 24 |
45010835092 ps |
| T655 |
/workspace/coverage/default/23.sysrst_ctrl_alert_test.1402748667 |
|
|
Mar 07 02:00:27 PM PST 24 |
Mar 07 02:00:30 PM PST 24 |
2024640586 ps |
| T656 |
/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2415379652 |
|
|
Mar 07 02:00:25 PM PST 24 |
Mar 07 02:00:32 PM PST 24 |
2458553683 ps |
| T258 |
/workspace/coverage/default/2.sysrst_ctrl_sec_cm.896478402 |
|
|
Mar 07 01:58:48 PM PST 24 |
Mar 07 01:59:51 PM PST 24 |
22011587681 ps |
| T657 |
/workspace/coverage/default/14.sysrst_ctrl_smoke.1416451604 |
|
|
Mar 07 01:59:41 PM PST 24 |
Mar 07 01:59:48 PM PST 24 |
2108162975 ps |
| T355 |
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4207494934 |
|
|
Mar 07 02:02:34 PM PST 24 |
Mar 07 02:03:55 PM PST 24 |
115993664139 ps |
| T658 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1605432678 |
|
|
Mar 07 01:58:50 PM PST 24 |
Mar 07 01:58:53 PM PST 24 |
2531219499 ps |
| T659 |
/workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1130329832 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:01:11 PM PST 24 |
2033640084 ps |
| T660 |
/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3009834089 |
|
|
Mar 07 02:01:42 PM PST 24 |
Mar 07 02:08:31 PM PST 24 |
309389108586 ps |
| T661 |
/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1358418777 |
|
|
Mar 07 02:00:02 PM PST 24 |
Mar 07 02:01:09 PM PST 24 |
2070240278246 ps |
| T393 |
/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2090704714 |
|
|
Mar 07 02:00:26 PM PST 24 |
Mar 07 02:00:37 PM PST 24 |
35916854356 ps |
| T662 |
/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.356670409 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:02:05 PM PST 24 |
24334988160 ps |
| T663 |
/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1171120708 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:16 PM PST 24 |
2611964073 ps |
| T664 |
/workspace/coverage/default/9.sysrst_ctrl_smoke.1900699967 |
|
|
Mar 07 01:59:28 PM PST 24 |
Mar 07 01:59:35 PM PST 24 |
2108314901 ps |
| T126 |
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.4236806758 |
|
|
Mar 07 02:01:56 PM PST 24 |
Mar 07 02:02:04 PM PST 24 |
4719959930 ps |
| T665 |
/workspace/coverage/default/49.sysrst_ctrl_alert_test.354241113 |
|
|
Mar 07 02:02:13 PM PST 24 |
Mar 07 02:02:18 PM PST 24 |
2015836879 ps |
| T666 |
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2713997941 |
|
|
Mar 07 01:59:29 PM PST 24 |
Mar 07 01:59:36 PM PST 24 |
2612043173 ps |
| T259 |
/workspace/coverage/default/0.sysrst_ctrl_sec_cm.2231648181 |
|
|
Mar 07 01:58:46 PM PST 24 |
Mar 07 01:59:45 PM PST 24 |
42015489144 ps |
| T667 |
/workspace/coverage/default/28.sysrst_ctrl_combo_detect.2693154606 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:05:02 PM PST 24 |
90874203479 ps |
| T78 |
/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.4234007618 |
|
|
Mar 07 01:59:46 PM PST 24 |
Mar 07 01:59:54 PM PST 24 |
8480214264 ps |
| T370 |
/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2412371713 |
|
|
Mar 07 01:59:42 PM PST 24 |
Mar 07 02:02:32 PM PST 24 |
66558391534 ps |
| T208 |
/workspace/coverage/default/35.sysrst_ctrl_edge_detect.4093872487 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:15 PM PST 24 |
2517883397 ps |
| T210 |
/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1207708917 |
|
|
Mar 07 02:00:25 PM PST 24 |
Mar 07 02:00:29 PM PST 24 |
5062157484 ps |
| T211 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect.1561332757 |
|
|
Mar 07 02:01:06 PM PST 24 |
Mar 07 02:01:22 PM PST 24 |
63468520587 ps |
| T162 |
/workspace/coverage/default/19.sysrst_ctrl_edge_detect.1289376758 |
|
|
Mar 07 02:00:12 PM PST 24 |
Mar 07 02:00:15 PM PST 24 |
6085660070 ps |
| T212 |
/workspace/coverage/default/36.sysrst_ctrl_alert_test.1685593349 |
|
|
Mar 07 02:01:19 PM PST 24 |
Mar 07 02:01:25 PM PST 24 |
2013671184 ps |
| T213 |
/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2430648707 |
|
|
Mar 07 01:59:44 PM PST 24 |
Mar 07 02:01:18 PM PST 24 |
34607727869 ps |
| T104 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all.2636088947 |
|
|
Mar 07 02:01:07 PM PST 24 |
Mar 07 02:05:53 PM PST 24 |
120666552782 ps |
| T214 |
/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.586268374 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:01:19 PM PST 24 |
2051744909 ps |
| T215 |
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3232273158 |
|
|
Mar 07 01:59:30 PM PST 24 |
Mar 07 01:59:33 PM PST 24 |
2800835854 ps |
| T216 |
/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1528584421 |
|
|
Mar 07 01:59:33 PM PST 24 |
Mar 07 02:01:30 PM PST 24 |
44680970651 ps |
| T668 |
/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1353705423 |
|
|
Mar 07 01:59:57 PM PST 24 |
Mar 07 02:02:17 PM PST 24 |
64140405003 ps |
| T669 |
/workspace/coverage/default/34.sysrst_ctrl_edge_detect.747032856 |
|
|
Mar 07 02:01:07 PM PST 24 |
Mar 07 02:01:11 PM PST 24 |
3559532038 ps |
| T365 |
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3715172762 |
|
|
Mar 07 02:02:18 PM PST 24 |
Mar 07 02:03:12 PM PST 24 |
73507206989 ps |
| T670 |
/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.942457865 |
|
|
Mar 07 02:01:06 PM PST 24 |
Mar 07 02:01:08 PM PST 24 |
2280809362 ps |
| T671 |
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2899322860 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:09 PM PST 24 |
2527262384 ps |
| T672 |
/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3718286315 |
|
|
Mar 07 01:59:32 PM PST 24 |
Mar 07 01:59:35 PM PST 24 |
2474842110 ps |
| T673 |
/workspace/coverage/default/41.sysrst_ctrl_smoke.2888980245 |
|
|
Mar 07 02:01:55 PM PST 24 |
Mar 07 02:01:57 PM PST 24 |
2136908173 ps |
| T674 |
/workspace/coverage/default/23.sysrst_ctrl_edge_detect.3473870349 |
|
|
Mar 07 02:00:24 PM PST 24 |
Mar 07 02:00:28 PM PST 24 |
4277296322 ps |
| T675 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all.364694161 |
|
|
Mar 07 02:00:10 PM PST 24 |
Mar 07 02:00:18 PM PST 24 |
11318369799 ps |
| T676 |
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4253966427 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:09 PM PST 24 |
2118363729 ps |
| T677 |
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2219191881 |
|
|
Mar 07 02:01:59 PM PST 24 |
Mar 07 02:02:35 PM PST 24 |
14685519813 ps |
| T678 |
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1676282661 |
|
|
Mar 07 02:02:12 PM PST 24 |
Mar 07 02:02:17 PM PST 24 |
2618760803 ps |
| T374 |
/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3546417636 |
|
|
Mar 07 01:59:54 PM PST 24 |
Mar 07 02:00:20 PM PST 24 |
64450519856 ps |
| T87 |
/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.650121901 |
|
|
Mar 07 01:58:51 PM PST 24 |
Mar 07 01:59:55 PM PST 24 |
107606174026 ps |
| T173 |
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2389027492 |
|
|
Mar 07 01:59:08 PM PST 24 |
Mar 07 01:59:12 PM PST 24 |
2521769173 ps |
| T174 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect.3113805388 |
|
|
Mar 07 02:01:57 PM PST 24 |
Mar 07 02:03:25 PM PST 24 |
67827999531 ps |
| T175 |
/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3421804824 |
|
|
Mar 07 02:00:10 PM PST 24 |
Mar 07 02:00:12 PM PST 24 |
2628991179 ps |
| T176 |
/workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3278753186 |
|
|
Mar 07 01:58:46 PM PST 24 |
Mar 07 01:58:51 PM PST 24 |
2153910488 ps |
| T177 |
/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1187453782 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:01:20 PM PST 24 |
2051352971 ps |
| T88 |
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.4182108346 |
|
|
Mar 07 02:02:04 PM PST 24 |
Mar 07 02:04:58 PM PST 24 |
121851525361 ps |
| T178 |
/workspace/coverage/default/34.sysrst_ctrl_combo_detect.4117424125 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:10:37 PM PST 24 |
203305225126 ps |
| T179 |
/workspace/coverage/default/12.sysrst_ctrl_edge_detect.420287726 |
|
|
Mar 07 01:59:44 PM PST 24 |
Mar 07 01:59:53 PM PST 24 |
4261273099 ps |
| T180 |
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4283193870 |
|
|
Mar 07 02:02:07 PM PST 24 |
Mar 07 02:02:22 PM PST 24 |
5171527524 ps |
| T679 |
/workspace/coverage/default/32.sysrst_ctrl_edge_detect.3759572195 |
|
|
Mar 07 02:01:12 PM PST 24 |
Mar 07 02:01:19 PM PST 24 |
3337434460 ps |
| T680 |
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2388494527 |
|
|
Mar 07 02:02:09 PM PST 24 |
Mar 07 02:02:14 PM PST 24 |
2465124020 ps |
| T246 |
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.984938801 |
|
|
Mar 07 02:02:15 PM PST 24 |
Mar 07 02:03:11 PM PST 24 |
155480159280 ps |
| T681 |
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2088069575 |
|
|
Mar 07 01:58:56 PM PST 24 |
Mar 07 01:59:57 PM PST 24 |
1535615859913 ps |
| T682 |
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1505365359 |
|
|
Mar 07 02:01:57 PM PST 24 |
Mar 07 02:02:01 PM PST 24 |
2514658325 ps |
| T683 |
/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1591771553 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:15 PM PST 24 |
7927671522 ps |
| T684 |
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3338818676 |
|
|
Mar 07 01:59:31 PM PST 24 |
Mar 07 01:59:39 PM PST 24 |
4799259094 ps |
| T685 |
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3103435618 |
|
|
Mar 07 02:01:33 PM PST 24 |
Mar 07 02:01:37 PM PST 24 |
2516288662 ps |
| T252 |
/workspace/coverage/default/33.sysrst_ctrl_combo_detect.1431959179 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:05:56 PM PST 24 |
105992789208 ps |
| T686 |
/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.558288745 |
|
|
Mar 07 02:01:20 PM PST 24 |
Mar 07 02:01:23 PM PST 24 |
3126486450 ps |
| T687 |
/workspace/coverage/default/20.sysrst_ctrl_alert_test.3434362988 |
|
|
Mar 07 02:00:08 PM PST 24 |
Mar 07 02:00:14 PM PST 24 |
2014993388 ps |
| T302 |
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4063247521 |
|
|
Mar 07 02:02:04 PM PST 24 |
Mar 07 02:03:37 PM PST 24 |
34570039520 ps |
| T688 |
/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.236054642 |
|
|
Mar 07 01:59:45 PM PST 24 |
Mar 07 01:59:51 PM PST 24 |
3493569196 ps |
| T689 |
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.69627942 |
|
|
Mar 07 01:59:28 PM PST 24 |
Mar 07 02:02:27 PM PST 24 |
69676670801 ps |
| T690 |
/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1758002327 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:01:07 PM PST 24 |
2523931433 ps |
| T691 |
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.213320973 |
|
|
Mar 07 02:02:19 PM PST 24 |
Mar 07 02:02:29 PM PST 24 |
3311279270 ps |
| T375 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2034293717 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:02:23 PM PST 24 |
147402729542 ps |
| T692 |
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4240133586 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:14 PM PST 24 |
2608285304 ps |
| T693 |
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.829744395 |
|
|
Mar 07 02:02:03 PM PST 24 |
Mar 07 02:02:08 PM PST 24 |
4709714263 ps |
| T694 |
/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3947402660 |
|
|
Mar 07 01:59:33 PM PST 24 |
Mar 07 02:04:40 PM PST 24 |
109743270521 ps |
| T310 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1742701677 |
|
|
Mar 07 02:00:25 PM PST 24 |
Mar 07 02:01:23 PM PST 24 |
102432101095 ps |
| T362 |
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1352901248 |
|
|
Mar 07 02:02:18 PM PST 24 |
Mar 07 02:05:45 PM PST 24 |
84099507812 ps |
| T695 |
/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1336309945 |
|
|
Mar 07 01:59:57 PM PST 24 |
Mar 07 02:00:00 PM PST 24 |
2628795356 ps |
| T696 |
/workspace/coverage/default/25.sysrst_ctrl_edge_detect.56016640 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:10 PM PST 24 |
4298733832 ps |
| T697 |
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1746850486 |
|
|
Mar 07 01:59:20 PM PST 24 |
Mar 07 01:59:21 PM PST 24 |
3683331812 ps |
| T272 |
/workspace/coverage/default/3.sysrst_ctrl_sec_cm.3198826234 |
|
|
Mar 07 01:58:56 PM PST 24 |
Mar 07 02:00:20 PM PST 24 |
42014649986 ps |
| T698 |
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1150349527 |
|
|
Mar 07 02:02:14 PM PST 24 |
Mar 07 02:02:21 PM PST 24 |
4918692328 ps |
| T699 |
/workspace/coverage/default/35.sysrst_ctrl_stress_all.330283830 |
|
|
Mar 07 02:01:10 PM PST 24 |
Mar 07 02:01:37 PM PST 24 |
10391825726 ps |
| T700 |
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2320238646 |
|
|
Mar 07 02:02:07 PM PST 24 |
Mar 07 02:02:25 PM PST 24 |
33251684885 ps |
| T701 |
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1671557153 |
|
|
Mar 07 02:02:23 PM PST 24 |
Mar 07 02:02:29 PM PST 24 |
23904448016 ps |
| T360 |
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.34943163 |
|
|
Mar 07 02:02:15 PM PST 24 |
Mar 07 02:04:54 PM PST 24 |
62218111246 ps |
| T377 |
/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.184365653 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:01:23 PM PST 24 |
32998799882 ps |
| T702 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect.3898754796 |
|
|
Mar 07 01:58:38 PM PST 24 |
Mar 07 02:01:55 PM PST 24 |
148330266203 ps |
| T703 |
/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1116372747 |
|
|
Mar 07 02:01:06 PM PST 24 |
Mar 07 02:01:13 PM PST 24 |
2610918347 ps |
| T704 |
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4038963842 |
|
|
Mar 07 01:59:11 PM PST 24 |
Mar 07 01:59:20 PM PST 24 |
900290447886 ps |
| T705 |
/workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.70068343 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:01:09 PM PST 24 |
2453423549 ps |
| T706 |
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.220573343 |
|
|
Mar 07 02:02:13 PM PST 24 |
Mar 07 02:02:17 PM PST 24 |
4057536125 ps |
| T707 |
/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3818487194 |
|
|
Mar 07 01:58:48 PM PST 24 |
Mar 07 01:58:55 PM PST 24 |
2149360215 ps |
| T708 |
/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.39109237 |
|
|
Mar 07 01:59:28 PM PST 24 |
Mar 07 01:59:36 PM PST 24 |
2510244225 ps |
| T709 |
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1012079323 |
|
|
Mar 07 02:02:05 PM PST 24 |
Mar 07 02:02:07 PM PST 24 |
2634157291 ps |
| T710 |
/workspace/coverage/default/0.sysrst_ctrl_alert_test.1059472608 |
|
|
Mar 07 01:58:49 PM PST 24 |
Mar 07 01:58:55 PM PST 24 |
2012536555 ps |
| T711 |
/workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.4263234229 |
|
|
Mar 07 02:01:10 PM PST 24 |
Mar 07 02:01:15 PM PST 24 |
2916375735 ps |
| T712 |
/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2162335352 |
|
|
Mar 07 02:01:07 PM PST 24 |
Mar 07 02:01:13 PM PST 24 |
3347498641 ps |
| T713 |
/workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.935664934 |
|
|
Mar 07 01:58:52 PM PST 24 |
Mar 07 01:58:55 PM PST 24 |
2629782878 ps |
| T714 |
/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2668939776 |
|
|
Mar 07 02:00:11 PM PST 24 |
Mar 07 02:00:18 PM PST 24 |
2514465813 ps |
| T715 |
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2613839551 |
|
|
Mar 07 01:59:20 PM PST 24 |
Mar 07 01:59:21 PM PST 24 |
2506941769 ps |
| T716 |
/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3189617145 |
|
|
Mar 07 02:00:27 PM PST 24 |
Mar 07 02:00:29 PM PST 24 |
2505216932 ps |
| T717 |
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2123399122 |
|
|
Mar 07 02:02:07 PM PST 24 |
Mar 07 02:02:12 PM PST 24 |
2039371413 ps |
| T718 |
/workspace/coverage/default/26.sysrst_ctrl_smoke.3296599629 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:10 PM PST 24 |
2124942636 ps |
| T719 |
/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2812928749 |
|
|
Mar 07 02:00:01 PM PST 24 |
Mar 07 02:00:04 PM PST 24 |
2628907137 ps |
| T720 |
/workspace/coverage/default/26.sysrst_ctrl_edge_detect.721632699 |
|
|
Mar 07 02:01:10 PM PST 24 |
Mar 07 02:01:13 PM PST 24 |
3777436884 ps |
| T372 |
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.844037909 |
|
|
Mar 07 02:02:23 PM PST 24 |
Mar 07 02:03:16 PM PST 24 |
84898306394 ps |
| T347 |
/workspace/coverage/default/16.sysrst_ctrl_combo_detect.1946752877 |
|
|
Mar 07 01:59:59 PM PST 24 |
Mar 07 02:02:41 PM PST 24 |
65842027018 ps |
| T721 |
/workspace/coverage/default/22.sysrst_ctrl_stress_all.1326863237 |
|
|
Mar 07 02:00:25 PM PST 24 |
Mar 07 02:00:56 PM PST 24 |
11739573423 ps |
| T722 |
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3100199698 |
|
|
Mar 07 01:59:29 PM PST 24 |
Mar 07 01:59:32 PM PST 24 |
3725588114 ps |
| T723 |
/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1760492835 |
|
|
Mar 07 02:00:26 PM PST 24 |
Mar 07 02:00:32 PM PST 24 |
12198350304 ps |
| T724 |
/workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1036331641 |
|
|
Mar 07 02:01:07 PM PST 24 |
Mar 07 02:01:14 PM PST 24 |
2609772016 ps |
| T725 |
/workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.633382878 |
|
|
Mar 07 01:58:55 PM PST 24 |
Mar 07 01:59:00 PM PST 24 |
7806515220 ps |
| T726 |
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1329239377 |
|
|
Mar 07 01:59:11 PM PST 24 |
Mar 07 01:59:13 PM PST 24 |
2069842463 ps |
| T727 |
/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1109422715 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:19 PM PST 24 |
3492605348 ps |
| T728 |
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2838398751 |
|
|
Mar 07 02:02:18 PM PST 24 |
Mar 07 02:02:21 PM PST 24 |
2532406983 ps |
| T105 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect.282469329 |
|
|
Mar 07 01:58:57 PM PST 24 |
Mar 07 02:00:44 PM PST 24 |
159983901687 ps |
| T729 |
/workspace/coverage/default/36.sysrst_ctrl_edge_detect.3627324524 |
|
|
Mar 07 02:01:21 PM PST 24 |
Mar 07 02:01:23 PM PST 24 |
2986115642 ps |
| T730 |
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1125027638 |
|
|
Mar 07 02:02:07 PM PST 24 |
Mar 07 02:02:14 PM PST 24 |
2515091559 ps |
| T225 |
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.133191758 |
|
|
Mar 07 01:58:57 PM PST 24 |
Mar 07 01:59:06 PM PST 24 |
3191159955 ps |
| T226 |
/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3490598291 |
|
|
Mar 07 02:00:25 PM PST 24 |
Mar 07 02:00:27 PM PST 24 |
2069354068 ps |
| T227 |
/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2681040270 |
|
|
Mar 07 01:59:43 PM PST 24 |
Mar 07 02:02:37 PM PST 24 |
320044400598 ps |
| T228 |
/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2669919569 |
|
|
Mar 07 01:58:45 PM PST 24 |
Mar 07 01:58:55 PM PST 24 |
3102818600 ps |
| T229 |
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1354376214 |
|
|
Mar 07 02:02:22 PM PST 24 |
Mar 07 02:04:31 PM PST 24 |
47080407689 ps |
| T230 |
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1099153170 |
|
|
Mar 07 02:01:58 PM PST 24 |
Mar 07 02:02:03 PM PST 24 |
2464906226 ps |
| T231 |
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.1010649196 |
|
|
Mar 07 01:58:58 PM PST 24 |
Mar 07 01:59:14 PM PST 24 |
22058871940 ps |
| T232 |
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2966969676 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:09 PM PST 24 |
2035951985 ps |
| T233 |
/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.874660347 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:12 PM PST 24 |
2256345516 ps |
| T234 |
/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.2715440773 |
|
|
Mar 07 02:01:09 PM PST 24 |
Mar 07 02:01:12 PM PST 24 |
2616162530 ps |
| T731 |
/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1724519823 |
|
|
Mar 07 01:59:44 PM PST 24 |
Mar 07 01:59:48 PM PST 24 |
2122706007 ps |
| T732 |
/workspace/coverage/default/42.sysrst_ctrl_smoke.871323887 |
|
|
Mar 07 02:01:57 PM PST 24 |
Mar 07 02:02:04 PM PST 24 |
2112487902 ps |
| T733 |
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1949425156 |
|
|
Mar 07 02:02:03 PM PST 24 |
Mar 07 02:02:07 PM PST 24 |
3528226551 ps |
| T734 |
/workspace/coverage/default/10.sysrst_ctrl_stress_all.3733948404 |
|
|
Mar 07 01:59:29 PM PST 24 |
Mar 07 02:00:59 PM PST 24 |
135573736875 ps |
| T106 |
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2170854230 |
|
|
Mar 07 01:59:17 PM PST 24 |
Mar 07 02:00:18 PM PST 24 |
89965220781 ps |
| T110 |
/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3413424965 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:11 PM PST 24 |
2635649062 ps |
| T111 |
/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3584611143 |
|
|
Mar 07 02:01:07 PM PST 24 |
Mar 07 02:01:09 PM PST 24 |
3673792463 ps |
| T86 |
/workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1845272967 |
|
|
Mar 07 02:00:27 PM PST 24 |
Mar 07 02:02:01 PM PST 24 |
136403353101 ps |
| T112 |
/workspace/coverage/default/35.sysrst_ctrl_alert_test.4034856778 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:12 PM PST 24 |
2014878690 ps |
| T113 |
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.81025520 |
|
|
Mar 07 02:01:57 PM PST 24 |
Mar 07 02:02:02 PM PST 24 |
5640610838 ps |
| T114 |
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1571670297 |
|
|
Mar 07 01:59:18 PM PST 24 |
Mar 07 01:59:22 PM PST 24 |
13548485788 ps |
| T115 |
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3358403630 |
|
|
Mar 07 02:02:22 PM PST 24 |
Mar 07 02:03:05 PM PST 24 |
61957539036 ps |
| T116 |
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1194514161 |
|
|
Mar 07 01:59:18 PM PST 24 |
Mar 07 01:59:25 PM PST 24 |
5205471449 ps |
| T117 |
/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.265840779 |
|
|
Mar 07 02:01:13 PM PST 24 |
Mar 07 02:01:20 PM PST 24 |
2514449802 ps |
| T735 |
/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.312835100 |
|
|
Mar 07 01:58:48 PM PST 24 |
Mar 07 01:58:50 PM PST 24 |
2572322123 ps |
| T736 |
/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.783513655 |
|
|
Mar 07 02:00:24 PM PST 24 |
Mar 07 02:00:32 PM PST 24 |
2612546871 ps |
| T737 |
/workspace/coverage/default/29.sysrst_ctrl_smoke.1198730524 |
|
|
Mar 07 02:01:12 PM PST 24 |
Mar 07 02:01:18 PM PST 24 |
2112934945 ps |
| T738 |
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4234794936 |
|
|
Mar 07 02:02:09 PM PST 24 |
Mar 07 02:02:13 PM PST 24 |
2617778381 ps |
| T739 |
/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.74175673 |
|
|
Mar 07 02:01:21 PM PST 24 |
Mar 07 02:01:24 PM PST 24 |
3571000384 ps |
| T740 |
/workspace/coverage/default/12.sysrst_ctrl_alert_test.3898979907 |
|
|
Mar 07 01:59:44 PM PST 24 |
Mar 07 01:59:51 PM PST 24 |
2014617048 ps |
| T741 |
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1078411039 |
|
|
Mar 07 02:02:25 PM PST 24 |
Mar 07 02:02:45 PM PST 24 |
26861353568 ps |
| T742 |
/workspace/coverage/default/35.sysrst_ctrl_smoke.3007575987 |
|
|
Mar 07 02:01:10 PM PST 24 |
Mar 07 02:01:12 PM PST 24 |
2131349627 ps |
| T743 |
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3128904988 |
|
|
Mar 07 02:01:56 PM PST 24 |
Mar 07 02:01:58 PM PST 24 |
2237429143 ps |
| T744 |
/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2992148203 |
|
|
Mar 07 02:01:17 PM PST 24 |
Mar 07 02:01:24 PM PST 24 |
2512897322 ps |
| T745 |
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2955581325 |
|
|
Mar 07 01:59:18 PM PST 24 |
Mar 07 01:59:21 PM PST 24 |
2075042676 ps |
| T746 |
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.903070589 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:03:11 PM PST 24 |
57222956071 ps |
| T79 |
/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2298126820 |
|
|
Mar 07 02:01:09 PM PST 24 |
Mar 07 02:12:58 PM PST 24 |
3546986312288 ps |
| T747 |
/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1646011534 |
|
|
Mar 07 01:59:43 PM PST 24 |
Mar 07 01:59:46 PM PST 24 |
7383182699 ps |
| T748 |
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1120495915 |
|
|
Mar 07 02:01:55 PM PST 24 |
Mar 07 02:02:02 PM PST 24 |
2511927465 ps |
| T749 |
/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2441132160 |
|
|
Mar 07 01:59:29 PM PST 24 |
Mar 07 01:59:32 PM PST 24 |
3777990979 ps |
| T750 |
/workspace/coverage/default/18.sysrst_ctrl_edge_detect.1963642394 |
|
|
Mar 07 02:00:05 PM PST 24 |
Mar 07 02:00:07 PM PST 24 |
3313080238 ps |
| T751 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.817155574 |
|
|
Mar 07 01:59:28 PM PST 24 |
Mar 07 02:07:09 PM PST 24 |
178656202766 ps |
| T338 |
/workspace/coverage/default/12.sysrst_ctrl_stress_all.2301398025 |
|
|
Mar 07 01:59:43 PM PST 24 |
Mar 07 02:01:04 PM PST 24 |
131869282784 ps |
| T752 |
/workspace/coverage/default/31.sysrst_ctrl_smoke.3278180635 |
|
|
Mar 07 02:01:05 PM PST 24 |
Mar 07 02:01:08 PM PST 24 |
2132327896 ps |
| T128 |
/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.379319704 |
|
|
Mar 07 02:00:24 PM PST 24 |
Mar 07 02:00:28 PM PST 24 |
6270427575 ps |
| T753 |
/workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1457604097 |
|
|
Mar 07 01:58:57 PM PST 24 |
Mar 07 01:59:00 PM PST 24 |
2532913413 ps |
| T754 |
/workspace/coverage/default/27.sysrst_ctrl_combo_detect.461170086 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:33 PM PST 24 |
86842609407 ps |
| T303 |
/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3820188893 |
|
|
Mar 07 02:01:12 PM PST 24 |
Mar 07 02:02:19 PM PST 24 |
24260012174 ps |
| T390 |
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2348686862 |
|
|
Mar 07 02:02:35 PM PST 24 |
Mar 07 02:03:07 PM PST 24 |
49078067831 ps |
| T342 |
/workspace/coverage/default/18.sysrst_ctrl_combo_detect.2284400260 |
|
|
Mar 07 01:59:58 PM PST 24 |
Mar 07 02:02:32 PM PST 24 |
53802295318 ps |
| T755 |
/workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2317614922 |
|
|
Mar 07 01:59:30 PM PST 24 |
Mar 07 01:59:34 PM PST 24 |
2461549891 ps |
| T756 |
/workspace/coverage/default/6.sysrst_ctrl_alert_test.790213784 |
|
|
Mar 07 01:59:17 PM PST 24 |
Mar 07 01:59:24 PM PST 24 |
2012449698 ps |
| T757 |
/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2597939711 |
|
|
Mar 07 01:59:28 PM PST 24 |
Mar 07 01:59:30 PM PST 24 |
2529724660 ps |
| T758 |
/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.310675589 |
|
|
Mar 07 01:59:47 PM PST 24 |
Mar 07 01:59:50 PM PST 24 |
12570130579 ps |
| T759 |
/workspace/coverage/default/29.sysrst_ctrl_stress_all.166014618 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:01:45 PM PST 24 |
22637081741 ps |
| T129 |
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4123297211 |
|
|
Mar 07 01:59:16 PM PST 24 |
Mar 07 01:59:21 PM PST 24 |
118940939369 ps |
| T361 |
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.861804370 |
|
|
Mar 07 02:02:25 PM PST 24 |
Mar 07 02:02:53 PM PST 24 |
82241609030 ps |
| T760 |
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1376047129 |
|
|
Mar 07 02:02:26 PM PST 24 |
Mar 07 02:05:26 PM PST 24 |
90772790302 ps |
| T761 |
/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.726949786 |
|
|
Mar 07 01:59:57 PM PST 24 |
Mar 07 02:12:40 PM PST 24 |
310680570789 ps |
| T762 |
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3875398368 |
|
|
Mar 07 02:02:28 PM PST 24 |
Mar 07 02:02:48 PM PST 24 |
27599036030 ps |
| T763 |
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1805306882 |
|
|
Mar 07 02:01:59 PM PST 24 |
Mar 07 02:04:27 PM PST 24 |
61416841202 ps |
| T764 |
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2090879744 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:31 PM PST 24 |
36128411657 ps |
| T765 |
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2317522224 |
|
|
Mar 07 01:59:16 PM PST 24 |
Mar 07 01:59:19 PM PST 24 |
3635920681 ps |
| T766 |
/workspace/coverage/default/3.sysrst_ctrl_edge_detect.1457241183 |
|
|
Mar 07 01:59:00 PM PST 24 |
Mar 07 01:59:08 PM PST 24 |
4809725789 ps |
| T767 |
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.319147246 |
|
|
Mar 07 02:02:07 PM PST 24 |
Mar 07 02:05:02 PM PST 24 |
141654136743 ps |
| T768 |
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2753541331 |
|
|
Mar 07 02:02:06 PM PST 24 |
Mar 07 02:02:14 PM PST 24 |
2610234968 ps |
| T769 |
/workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1435803510 |
|
|
Mar 07 02:00:10 PM PST 24 |
Mar 07 02:00:21 PM PST 24 |
3351256564 ps |
| T770 |
/workspace/coverage/default/15.sysrst_ctrl_stress_all.2246062314 |
|
|
Mar 07 01:59:54 PM PST 24 |
Mar 07 02:00:05 PM PST 24 |
7586481512 ps |
| T771 |
/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2716606746 |
|
|
Mar 07 01:59:57 PM PST 24 |
Mar 07 02:00:04 PM PST 24 |
2211140031 ps |
| T772 |
/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3387435523 |
|
|
Mar 07 02:01:08 PM PST 24 |
Mar 07 02:01:14 PM PST 24 |
2252113134 ps |
| T773 |
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.960726082 |
|
|
Mar 07 02:01:56 PM PST 24 |
Mar 07 02:01:59 PM PST 24 |
2785814720 ps |
| T774 |
/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2526840467 |
|
|
Mar 07 02:01:22 PM PST 24 |
Mar 07 02:01:25 PM PST 24 |
2104863049 ps |
| T775 |
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1443172428 |
|
|
Mar 07 01:59:20 PM PST 24 |
Mar 07 01:59:24 PM PST 24 |
3724867162 ps |
| T776 |
/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3300323054 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:01:21 PM PST 24 |
2534485808 ps |
| T777 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.63868894 |
|
|
Mar 07 01:58:49 PM PST 24 |
Mar 07 01:58:53 PM PST 24 |
2395486460 ps |
| T778 |
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1087151535 |
|
|
Mar 07 02:02:16 PM PST 24 |
Mar 07 02:02:59 PM PST 24 |
31225606379 ps |
| T779 |
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.881505084 |
|
|
Mar 07 02:02:35 PM PST 24 |
Mar 07 02:03:34 PM PST 24 |
23332978493 ps |
| T780 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2792063816 |
|
|
Mar 07 01:58:59 PM PST 24 |
Mar 07 02:04:12 PM PST 24 |
125927955185 ps |
| T781 |
/workspace/coverage/default/16.sysrst_ctrl_stress_all.3469126618 |
|
|
Mar 07 01:59:56 PM PST 24 |
Mar 07 02:00:48 PM PST 24 |
305294068296 ps |
| T346 |
/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1250097252 |
|
|
Mar 07 02:01:33 PM PST 24 |
Mar 07 02:12:47 PM PST 24 |
252991944875 ps |
| T782 |
/workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3662566183 |
|
|
Mar 07 02:01:09 PM PST 24 |
Mar 07 02:01:12 PM PST 24 |
3681542753 ps |
| T783 |
/workspace/coverage/default/11.sysrst_ctrl_edge_detect.2252938758 |
|
|
Mar 07 01:59:32 PM PST 24 |
Mar 07 01:59:39 PM PST 24 |
3480951828 ps |
| T784 |
/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4048904410 |
|
|
Mar 07 02:00:00 PM PST 24 |
Mar 07 02:00:05 PM PST 24 |
3297188072 ps |
| T785 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4249266263 |
|
|
Mar 07 01:58:37 PM PST 24 |
Mar 07 01:58:41 PM PST 24 |
2320710305 ps |
| T133 |
/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1318567053 |
|
|
Mar 07 01:58:37 PM PST 24 |
Mar 07 01:58:43 PM PST 24 |
5423843817 ps |
| T786 |
/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2949590606 |
|
|
Mar 07 02:00:25 PM PST 24 |
Mar 07 02:00:27 PM PST 24 |
2239762307 ps |
| T787 |
/workspace/coverage/default/31.sysrst_ctrl_edge_detect.1981921481 |
|
|
Mar 07 02:01:12 PM PST 24 |
Mar 07 02:01:16 PM PST 24 |
3053099510 ps |
| T130 |
/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1233938731 |
|
|
Mar 07 01:59:56 PM PST 24 |
Mar 07 02:00:05 PM PST 24 |
6281096285 ps |
| T788 |
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4200564147 |
|
|
Mar 07 01:59:05 PM PST 24 |
Mar 07 02:01:14 PM PST 24 |
47573721663 ps |
| T789 |
/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1712904791 |
|
|
Mar 07 02:01:20 PM PST 24 |
Mar 07 02:01:24 PM PST 24 |
2614836343 ps |
| T790 |
/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.782093911 |
|
|
Mar 07 02:00:24 PM PST 24 |
Mar 07 02:00:32 PM PST 24 |
2510401978 ps |
| T144 |
/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3003324670 |
|
|
Mar 07 02:01:18 PM PST 24 |
Mar 07 02:02:44 PM PST 24 |
134048747217 ps |
| T371 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2475438147 |
|
|
Mar 07 01:58:37 PM PST 24 |
Mar 07 01:59:02 PM PST 24 |
166701039727 ps |
| T791 |
/workspace/coverage/default/39.sysrst_ctrl_smoke.3387062961 |
|
|
Mar 07 02:02:56 PM PST 24 |
Mar 07 02:03:00 PM PST 24 |
2118586234 ps |
| T792 |
/workspace/coverage/default/14.sysrst_ctrl_alert_test.331734755 |
|
|
Mar 07 01:59:44 PM PST 24 |
Mar 07 01:59:51 PM PST 24 |
2012225055 ps |
| T793 |
/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3311530339 |
|
|
Mar 07 01:59:32 PM PST 24 |
Mar 07 01:59:39 PM PST 24 |
2513811784 ps |
| T255 |
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.755277201 |
|
|
Mar 07 01:10:13 PM PST 24 |
Mar 07 01:10:20 PM PST 24 |
2041689302 ps |
| T49 |
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1832384258 |
|
|
Mar 07 01:10:28 PM PST 24 |
Mar 07 01:10:31 PM PST 24 |
2077014206 ps |
| T50 |
/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.4283972849 |
|
|
Mar 07 01:10:15 PM PST 24 |
Mar 07 01:10:18 PM PST 24 |
2047200980 ps |
| T794 |
/workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3792636976 |
|
|
Mar 07 01:10:18 PM PST 24 |
Mar 07 01:10:20 PM PST 24 |
2037744671 ps |
| T795 |
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2495660447 |
|
|
Mar 07 01:10:12 PM PST 24 |
Mar 07 01:10:14 PM PST 24 |
2062836830 ps |