SYSRST_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.520s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	8.100s	2.444ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.670s	2.387ms	4	5	80.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.050s	2.532ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	11.420s	4.011ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.260s	2.056ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.882m	63.216ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	11.770s	3.171ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.880s	2.110ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.260s	2.056ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.770s	3.171ms	5	5	100.00
V1		TOTAL			164	165	99.39
V2	combo_detect	sysrst_ctrl_combo_detect	9.482m	203.305ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	11.226m	252.992ms	91	100	91.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.706m	310.681ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	25.150m	575.333ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.830s	2.515ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.730s	2.191ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	25.020m	564.952ms	49	50	98.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.930s	2.614ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	11.813m	3.547s	46	50	92.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.543m	34.214ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	5.920m	219.698ms	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	6.180s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.120s	2.009ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.090s	2.120ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.090s	2.120ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	11.420s	4.011ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.260s	2.056ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.770s	3.171ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	37.770s	9.065ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	11.420s	4.011ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.260s	2.056ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.770s	3.171ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	37.770s	9.065ms	20	20	100.00
V2		TOTAL			676	692	97.69
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.403m	42.015ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.937m	42.441ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.937m	42.441ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	3.234m	98.168ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			910	932	97.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.84	99.34	96.33	100.00	96.79	98.71	99.53	94.16

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 7 failures:

Test sysrst_ctrl_ultra_low_pwr has 4 failures.

6.sysrst_ctrl_ultra_low_pwr.80504644393690383419526764812373147905213980996260659086190980773220013678555
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5007853019 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 5300353019 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5300353019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sysrst_ctrl_ultra_low_pwr.90240969119145299797978893650373392779069020904910140070060877995001081572545
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2594651070 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4227151070 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4227151070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sysrst_ctrl_stress_all has 2 failures.

8.sysrst_ctrl_stress_all.72092978473452146647347933194553388456573539191612102229753067226483355998430
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4269795553 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4537295553 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 11502295553 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 11502408432 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 11533408680 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_in_out_inverted_vseq

9.sysrst_ctrl_stress_all.111006788719902451914096573164543743458118678697151933569336665106044944317819
Line 563, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 61724625941 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 160442125941 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 160442125941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

36.sysrst_ctrl_stress_all_with_rand_reset.90488067792557904301960473860421725607561183921679330171350279099368619187021
Line 639, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 52859162415 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 52891662415 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 55416662415 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 55416729701 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 55430009701 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 3 failures.

54.sysrst_ctrl_combo_detect_with_pre_cond.108948535600363128198202686354372972305601336169946026056148324275117061580162
Line 617, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 61815903896 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 61815903896 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 61815903896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

62.sysrst_ctrl_combo_detect_with_pre_cond.108011477394867187649374861523226270753855995623173881774142355472506041255417
Line 618, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 72561227606 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 72561227606 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 72561227606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 2 failures:

Test sysrst_ctrl_combo_detect_ec_rst has 1 failures.

0.sysrst_ctrl_combo_detect_ec_rst.66973270169732067001619370092759208868439911487584528962838587061591351103298
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest/run.log

  UVM_ERROR @ 2175625042 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 2387408312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

31.sysrst_ctrl_stress_all_with_rand_reset.41825806829751687448890210503289919983332609813788478462150658067981847229655
Line 726, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 121894809566 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 122139853193 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Finished run 9/10 w/o reset
  UVM_INFO @ 122139853193 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 9/10

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 2 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 4.sysrst_ctrl_ec_pwr_on_rst.44607508815953741355274133408428419391735680270951455807998424320074706946321
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 3327702624 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 3327702624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 30.sysrst_ctrl_stress_all_with_rand_reset.65110864231772054480237351725524796179303658279868790974912729383834427605410
    Line 581, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12772365278 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 12772365278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

5.sysrst_ctrl_combo_detect_with_pre_cond.108145550869799895290783236634820109631590595839727354225813711289118186313353
Line 600, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 86314972121 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 96607299028 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 96607369735 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x10
  UVM_INFO @ 97085369257 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
  UVM_INFO @ 97099972121 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= b

21.sysrst_ctrl_combo_detect_with_pre_cond.102407872067714724956847310601687784972207368138842459294627764548130499658514
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 49152706829 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 49152706829 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 49152706829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:75) [sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

23.sysrst_ctrl_stress_all_with_rand_reset.50943795338021549397268794612097830569456139019337797184160841693396178354013
Line 637, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 684638756191 ps: (sysrst_ctrl_combo_detect_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 684638756191 ps: (sysrst_ctrl_combo_detect_vseq.sv:234) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.ec_rst_l_out == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 684638756191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

36.sysrst_ctrl_combo_detect_with_pre_cond.3402790894005881538599731911730144027085965945059288804494864623066835148685
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13336983528 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4
  UVM_ERROR @ 13336983528 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 13336983528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

39.sysrst_ctrl_combo_detect_with_pre_cond.43930099172013195776046425942931053481767811795420151670464277093664848191143
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13939589098 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-4
  UVM_ERROR @ 13939589098 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 13939589098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

40.sysrst_ctrl_stress_all_with_rand_reset.69435186977418506277575121559812756564772316455657429924037421421605409036149
Line 672, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 62837226208 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 62845616960 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 62875616960 ps: (cip_base_vseq.sv:764) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 10/10

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

41.sysrst_ctrl_combo_detect_with_pre_cond.43518608378954231739248730222210549206678733308337421681035006121645041218068
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13346841310 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-4
  UVM_ERROR @ 13346841310 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
  UVM_INFO @ 13346841310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

84.sysrst_ctrl_combo_detect_with_pre_cond.89219710543933137907770491640541245708887329811697980626583727577355110073444
Line 584, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 40309461493 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
  UVM_INFO @ 50551443943 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27
  UVM_INFO @ 50551516862 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2e
  UVM_INFO @ 52469461493 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
  UVM_INFO @ 52469703242 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2