SYSRST_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.520s 2.111ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.100s 2.444ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.670s 2.387ms 4 5 80.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.050s 2.532ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.420s 4.011ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.260s 2.056ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.882m 63.216ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 11.770s 3.171ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.880s 2.110ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.260s 2.056ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.770s 3.171ms 5 5 100.00
V1 TOTAL 164 165 99.39
V2 combo_detect sysrst_ctrl_combo_detect 9.482m 203.305ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 11.226m 252.992ms 91 100 91.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 12.706m 310.681ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 25.150m 575.333ms 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.830s 2.515ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.730s 2.191ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 25.020m 564.952ms 49 50 98.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.930s 2.614ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 11.813m 3.547s 46 50 92.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.543m 34.214ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 5.920m 219.698ms 48 50 96.00
V2 alert_test sysrst_ctrl_alert_test 6.180s 2.012ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.120s 2.009ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 8.090s 2.120ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 8.090s 2.120ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.420s 4.011ms 5 5 100.00
sysrst_ctrl_csr_rw 6.260s 2.056ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.770s 3.171ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 37.770s 9.065ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.420s 4.011ms 5 5 100.00
sysrst_ctrl_csr_rw 6.260s 2.056ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.770s 3.171ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 37.770s 9.065ms 20 20 100.00
V2 TOTAL 676 692 97.69
V2S tl_intg_err sysrst_ctrl_sec_cm 1.403m 42.015ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.937m 42.441ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.937m 42.441ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 3.234m 98.168ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 910 932 97.64

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 15 15 11 73.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.84 99.34 96.33 100.00 96.79 98.71 99.53 94.16

Failure Buckets

Past Results