SYSRST_CTRL Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.530s	2.112ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.840s	2.463ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.090s	2.419ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.340s	2.528ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	16.410s	6.043ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.730s	2.042ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	5.352m	74.934ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	12.180s	3.166ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	7.770s	2.076ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.730s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.180s	3.166ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.395m	187.242ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.701m	205.391ms	93	100	93.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.968m	287.930ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	9.307m	208.818ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.840s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.700s	2.210ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	2.046m	764.617ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.840s	2.613ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.231m	417.215ms	46	50	92.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.671m	40.623ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	8.378m	184.826ms	46	50	92.00
V2	alert_test	sysrst_ctrl_alert_test	6.200s	2.011ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.480s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.780s	2.056ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.780s	2.056ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	16.410s	6.043ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.730s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.180s	3.166ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	27.920s	5.560ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	16.410s	6.043ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.730s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.180s	3.166ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	27.920s	5.560ms	20	20	100.00
V2		TOTAL			677	692	97.83
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.872m	42.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	2.068m	42.385ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	2.068m	42.385ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	4.465m	697.245ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			907	932	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	99.31	96.07	100.00	96.15	98.68	99.16	93.64

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 11 failures:

Test sysrst_ctrl_stress_all has 4 failures.

4.sysrst_ctrl_stress_all.108704857552713889363344538072949791328272620496369115339760745409409972443760
Line 585, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 11300893385 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 12853393385 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 12853393385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.sysrst_ctrl_stress_all.87837877263257088732792523520964098627865409035218067104770438093334001671273
Line 619, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 155181072134 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 155363572134 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 158328572134 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 158328688658 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 158383928658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 3 failures.

12.sysrst_ctrl_stress_all_with_rand_reset.29824197321769717183821355866756439714930838748031453683236228777515578927274
Line 634, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32310877708 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 32413377708 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 32923377708 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 32923518973 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 32938233244 ps: (cip_base_vseq.sv:733) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

17.sysrst_ctrl_stress_all_with_rand_reset.56813617990363204745145163409075315210112689730236820012111282025179974413969
Line 567, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8826775168 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 9014275168 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 9014275168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test sysrst_ctrl_ultra_low_pwr has 4 failures.

22.sysrst_ctrl_ultra_low_pwr.68444700019813369725341831455381016655476215551484321030046461053747719592879
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 9201925604 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 9419425604 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 10779425604 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 10779546321 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 10799173889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

24.sysrst_ctrl_ultra_low_pwr.64544790045048448650371898190582404097435643296654031963930758782130593149773
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2393583871 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 151236083871 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 599681083871 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 599681465876 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 599713905876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 3 failures.

1.sysrst_ctrl_stress_all_with_rand_reset.29009863622459742906647599351972499578398545547274281679356847097692153716810
Line 614, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18237436590 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18260368909 ps: (cip_base_vseq.sv:752) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 4/10
  UVM_INFO @ 18261314031 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 18261491120 ps: (cip_base_vseq.sv:705) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/10

4.sysrst_ctrl_stress_all_with_rand_reset.33721064530235952058704698586802641800604420391227929629720772925793959004302
Line 601, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17016597421 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 17032002457 ps: (cip_base_vseq.sv:752) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 4/5
  UVM_INFO @ 17033911233 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 17035344184 ps: (cip_base_vseq.sv:705) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/5

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 3 failures.

15.sysrst_ctrl_combo_detect_with_pre_cond.82707051714855464081907541503634757856704713727744763546136493877533510861550
Line 573, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 16366623657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 16366623657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16366623657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.sysrst_ctrl_combo_detect_with_pre_cond.82538470670834286341753763563003061316045556810123709023323894006869753641736
Line 603, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 89660839258 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 89660839258 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 89660839258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
  - 9.sysrst_ctrl_stress_all_with_rand_reset.11895706537551289819254458773004827561158720872097162959222328922612145244109
    Line 591, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 22569387514 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 22569387514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

16.sysrst_ctrl_stress_all_with_rand_reset.105305319815593386556270298020579668963961192359514261994114140845139374213467
Line 572, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7932027743 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 8138127743 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ec_pwr_on_rst_vseq
  UVM_INFO @ 9462791659 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 9502791659 ps: (cip_base_vseq.sv:752) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

27.sysrst_ctrl_stress_all_with_rand_reset.109036213132075392387505762960527020728943253501023180194704790227806938500798
Line 659, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 224949549261 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 224949549261 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 224949549261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

30.sysrst_ctrl_combo_detect_with_pre_cond.108846352200571116179031141184981389463637094204881797161416709369289662978422
Line 575, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13306682459 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_ERROR @ 13306682459 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 13306682459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

35.sysrst_ctrl_combo_detect_with_pre_cond.36958149849551659675054909352141493918374527626870420060675826960715119109293
Line 573, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15643501826 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 15663501826 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 15683501826 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 25975349184 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e
  UVM_INFO @ 25975432520 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

40.sysrst_ctrl_combo_detect_with_pre_cond.69709355195483050976144734834814668912649764081744849423756312776923196324064
Line 568, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13332116016 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
  UVM_ERROR @ 13332116016 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 13332116016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

46.sysrst_ctrl_combo_detect_with_pre_cond.28014369023341045916971751433576372008902485250525512628063467712718743470591
Line 567, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14313762886 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
  UVM_ERROR @ 14313762886 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
  UVM_INFO @ 14313762886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

46.sysrst_ctrl_stress_all_with_rand_reset.47143822275728106279355781271034605857677732352958496210691506716396678991048
Line 759, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1214868757832 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1214970247876 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 30e1
  UVM_INFO @ 1274443404574 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Reset is issued for run 10/10
  UVM_INFO @ 1274458404574 ps: (cip_base_vseq.sv:752) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]