| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| sysrst_ctrl_combo_detect_det_cg_0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_detect_det_cg_1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_detect_det_cg_2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_detect_det_cg_3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 30 | 1 | T232 | 1 | T339 | 7 | T102 | 1 | ||||
| mid_range | 340 | 1 | T7 | 7 | T8 | 9 | T10 | 5 | ||||
| min_range | 462 | 1 | T24 | 1 | T3 | 9 | T30 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 24 | 1 | T8 | 9 | T203 | 15 | - | - | ||||
| mid_range | 285 | 1 | T10 | 5 | T53 | 9 | T12 | 17 | ||||
| min_range | 523 | 1 | T24 | 1 | T3 | 9 | T7 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 17 | 1 | T12 | 17 | - | - | - | - | ||||
| mid_range | 276 | 1 | T10 | 5 | T53 | 7 | T17 | 9 | ||||
| min_range | 539 | 1 | T24 | 1 | T3 | 9 | T7 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 20 | 1 | T238 | 1 | T148 | 10 | T248 | 6 | ||||
| mid_range | 291 | 1 | T8 | 9 | T10 | 5 | T53 | 7 | ||||
| min_range | 521 | 1 | T24 | 1 | T3 | 9 | T7 | 7 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |