Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	98.85	96.35	100.00	96.15	98.26	99.44	94.55

Total tests in report: 912

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
59.08	59.08	75.95	75.95	66.11	66.11	92.26	92.26	15.38	15.38	78.32	78.32	68.54	68.54	17.00	17.00	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3420641373
76.75	17.67	90.07	14.12	83.04	16.93	96.01	3.76	34.62	19.23	90.18	11.87	82.21	13.67	61.10	44.10	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.98188229
85.47	8.72	94.62	4.55	87.19	4.15	96.01	0.00	67.31	32.69	93.94	3.76	93.63	11.42	65.56	4.46	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3093755990
87.98	2.51	96.28	1.67	89.43	2.24	96.47	0.46	71.15	3.85	95.54	1.60	95.69	2.06	71.26	5.70	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.450097610
89.67	1.70	97.10	0.82	91.53	2.10	96.47	0.00	78.85	7.69	96.45	0.90	96.07	0.37	71.26	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1791307878
90.95	1.28	97.17	0.07	92.82	1.29	97.15	0.68	78.85	0.00	96.55	0.10	96.16	0.09	77.95	6.69	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3861394450
91.93	0.98	97.46	0.30	93.13	0.31	97.61	0.46	80.13	1.28	96.73	0.17	96.82	0.66	81.62	3.67	/workspace/coverage/default/28.sysrst_ctrl_stress_all.3224024771
92.59	0.67	97.55	0.09	93.47	0.33	98.06	0.46	82.05	1.92	96.83	0.10	97.28	0.47	82.90	1.29	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2097430092
93.01	0.42	97.62	0.07	93.51	0.05	98.06	0.00	84.62	2.56	96.97	0.14	97.38	0.09	82.90	0.00	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.4239137877
93.38	0.37	97.66	0.03	93.63	0.12	98.06	0.00	85.26	0.64	97.04	0.07	97.57	0.19	84.44	1.54	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.92304022
93.70	0.32	97.76	0.10	93.70	0.07	98.06	0.00	86.54	1.28	97.11	0.07	97.57	0.00	85.13	0.69	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1444650326
94.01	0.32	97.83	0.07	93.73	0.02	98.06	0.00	88.46	1.92	97.22	0.10	97.66	0.09	85.13	0.00	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1640884398
94.29	0.28	97.83	0.00	93.75	0.02	99.66	1.59	88.46	0.00	97.22	0.00	97.75	0.09	85.38	0.25	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.825500843
94.56	0.27	97.93	0.10	93.85	0.10	99.66	0.00	89.74	1.28	97.32	0.10	98.03	0.28	85.38	0.00	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.2961257083
94.79	0.23	97.99	0.05	93.89	0.05	99.66	0.00	90.38	0.64	97.42	0.10	98.22	0.19	85.93	0.55	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1097310958
95.00	0.22	98.02	0.03	93.94	0.05	99.66	0.00	91.67	1.28	97.49	0.07	98.31	0.09	85.93	0.00	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2756646070
95.22	0.22	98.07	0.05	93.97	0.02	99.66	0.00	92.95	1.28	97.56	0.07	98.41	0.09	85.93	0.00	/workspace/coverage/default/36.sysrst_ctrl_stress_all.2148606930
95.42	0.20	98.21	0.14	94.44	0.48	99.66	0.00	92.95	0.00	97.84	0.28	98.88	0.47	85.98	0.05	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.660817373
95.61	0.19	98.25	0.03	94.51	0.07	99.66	0.00	92.95	0.00	97.84	0.00	98.88	0.00	87.17	1.19	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2028766059
95.77	0.17	98.45	0.21	94.63	0.12	99.77	0.11	92.95	0.00	97.88	0.03	98.88	0.00	87.86	0.69	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.1159090251
95.92	0.15	98.45	0.00	94.63	0.00	99.77	0.00	92.95	0.00	97.88	0.00	98.88	0.00	88.90	1.04	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.2363472747
96.05	0.13	98.51	0.05	94.66	0.02	99.77	0.00	93.59	0.64	97.95	0.07	98.97	0.09	88.90	0.00	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3984852082
96.17	0.12	98.58	0.07	94.66	0.00	99.77	0.00	93.59	0.00	97.95	0.00	98.97	0.00	89.69	0.79	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1955613997
96.29	0.12	98.58	0.00	95.40	0.74	99.77	0.00	93.59	0.00	97.95	0.00	98.97	0.00	89.79	0.10	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1843652144
96.41	0.12	98.61	0.03	95.42	0.02	99.77	0.00	94.23	0.64	97.98	0.03	99.06	0.09	89.79	0.00	/workspace/coverage/default/2.sysrst_ctrl_edge_detect.783416215
96.53	0.12	98.65	0.03	95.44	0.02	99.77	0.00	94.87	0.64	98.02	0.03	99.16	0.09	89.79	0.00	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.3982217864
96.63	0.10	98.66	0.02	95.44	0.00	99.77	0.00	95.51	0.64	98.05	0.03	99.16	0.00	89.79	0.00	/workspace/coverage/default/36.sysrst_ctrl_edge_detect.1187407543
96.73	0.10	98.68	0.02	95.44	0.00	99.77	0.00	96.15	0.64	98.09	0.03	99.16	0.00	89.79	0.00	/workspace/coverage/default/9.sysrst_ctrl_stress_all.3925500154
96.82	0.09	98.75	0.07	95.52	0.07	99.77	0.00	96.15	0.00	98.19	0.10	99.16	0.00	90.19	0.40	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2468057891
96.90	0.08	98.75	0.00	95.52	0.00	99.77	0.00	96.15	0.00	98.19	0.00	99.16	0.00	90.78	0.59	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1721304113
96.97	0.06	98.75	0.00	95.52	0.00	99.77	0.00	96.15	0.00	98.19	0.00	99.16	0.00	91.23	0.45	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.619230691
97.02	0.06	98.77	0.02	95.85	0.33	99.77	0.00	96.15	0.00	98.22	0.03	99.16	0.00	91.23	0.00	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.945588583
97.08	0.05	98.77	0.00	96.04	0.19	99.77	0.00	96.15	0.00	98.22	0.00	99.34	0.19	91.23	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2442082050
97.13	0.05	98.82	0.05	96.11	0.07	100.00	0.23	96.15	0.00	98.22	0.00	99.34	0.00	91.23	0.00	/workspace/coverage/default/10.sysrst_ctrl_alert_test.1910440566
97.17	0.04	98.82	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	91.53	0.30	/workspace/coverage/default/25.sysrst_ctrl_stress_all.1204303555
97.21	0.04	98.82	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	91.82	0.30	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2072337097
97.25	0.04	98.82	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	92.07	0.25	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3670988920
97.28	0.04	98.82	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	92.32	0.25	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3550046328
97.31	0.03	98.82	0.00	96.11	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	92.52	0.20	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.4257341672
97.33	0.02	98.82	0.00	96.14	0.02	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	92.67	0.15	/workspace/coverage/default/17.sysrst_ctrl_stress_all.2200212764
97.36	0.02	98.82	0.00	96.14	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	92.81	0.15	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3360404863
97.38	0.02	98.82	0.00	96.14	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	92.96	0.15	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.1575576796
97.40	0.02	98.82	0.00	96.14	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.11	0.15	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.2303298731
97.42	0.02	98.82	0.00	96.26	0.12	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.11	0.00	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.823103579
97.43	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.21	0.10	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.2186562568
97.44	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.31	0.10	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.4194013185
97.46	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.41	0.10	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2951247338
97.47	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.51	0.10	/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3385148679
97.49	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.61	0.10	/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.608778260
97.50	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.71	0.10	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1043224511
97.51	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.81	0.10	/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1498464687
97.53	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.34	0.00	93.90	0.10	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1023236993
97.54	0.01	98.82	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.22	0.00	99.44	0.09	93.90	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2046492113
97.55	0.01	98.85	0.03	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.03	99.44	0.00	93.90	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.236055145
97.56	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	93.95	0.05	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.721936277
97.57	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.00	0.05	/workspace/coverage/default/13.sysrst_ctrl_stress_all.3485863527
97.57	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.05	0.05	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2364988423
97.58	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.10	0.05	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.658474048
97.59	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.15	0.05	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.3677358366
97.59	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.20	0.05	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3516460473
97.60	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.25	0.05	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2152400584
97.61	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.30	0.05	/workspace/coverage/default/39.sysrst_ctrl_combo_detect.1216868165
97.62	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.35	0.05	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.564941390
97.62	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.40	0.05	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.368898088
97.63	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.45	0.05	/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1070117821
97.64	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.50	0.05	/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2639629327
97.64	0.01	98.85	0.00	96.26	0.00	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.55	0.05	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3440789752
97.65	0.01	98.85	0.00	96.28	0.02	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.55	0.00	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.395783140
97.65	0.01	98.85	0.00	96.30	0.02	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.55	0.00	/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.648150194
97.65	0.01	98.85	0.00	96.33	0.02	100.00	0.00	96.15	0.00	98.26	0.00	99.44	0.00	94.55	0.00	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3938264137

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1290587266
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2321128088
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2082063050
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3945830705
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.319294159
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2740484638
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3982726228
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.390588272
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1483641630
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1181975426
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1418074587
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.718313693
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3224908955
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.996868942
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3737533226
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2142152142
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.826244483
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1571476063
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.69410989
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2989744206
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3362908099
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3186215160
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3461283020
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1657690105
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2560517644
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1385145906
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.621671998
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3499302276
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.421125629
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4112813742
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1056769801
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3971530784
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3881350919
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.284926941
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1790953727
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1369635478
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3400787086
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1672638792
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1020035918
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1561311711
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3504010807
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/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2416454699
/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3589052806
/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.841917159
/workspace/coverage/default/39.sysrst_ctrl_smoke.1888207291
/workspace/coverage/default/39.sysrst_ctrl_stress_all.2202282720
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.4055968307
/workspace/coverage/default/4.sysrst_ctrl_alert_test.2535282606
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4138675406
/workspace/coverage/default/4.sysrst_ctrl_combo_detect.2610898434
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3608480134
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1440999196
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1958176435
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3701691638
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3016707356
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.310325040
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3855743596
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.27952301
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.769395028
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3362983511
/workspace/coverage/default/4.sysrst_ctrl_smoke.2536185892
/workspace/coverage/default/4.sysrst_ctrl_stress_all.1556021312
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3846347099
/workspace/coverage/default/40.sysrst_ctrl_alert_test.1298974929
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3971747437
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2842835762
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2583914165
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.302186815
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3310305041
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1978628825
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.502636258
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3007236101
/workspace/coverage/default/40.sysrst_ctrl_smoke.4277932802
/workspace/coverage/default/40.sysrst_ctrl_stress_all.2286187097
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1381163863
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1574886117
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.310743015
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.161586590
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.424992808
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2155004019
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.3667541235
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.874812413
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1320331277
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2444039810
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2678132869
/workspace/coverage/default/41.sysrst_ctrl_smoke.362386770
/workspace/coverage/default/41.sysrst_ctrl_stress_all.517660163
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4210500642
/workspace/coverage/default/42.sysrst_ctrl_alert_test.354194865
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1797203748
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.183695567
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3580519690
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3534225469
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1224720980
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.892780280
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3465731645
/workspace/coverage/default/42.sysrst_ctrl_smoke.3712725063
/workspace/coverage/default/42.sysrst_ctrl_stress_all.2616923674
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.909487470
/workspace/coverage/default/43.sysrst_ctrl_alert_test.3611416479
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3586600201
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2277564679
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2499391044
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1969612778
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2226127813
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2873206636
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.25543957
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3437104739
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3544272762
/workspace/coverage/default/43.sysrst_ctrl_smoke.1308301324
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1339929890
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1200671879
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2854044848
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2822161309
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.594972237
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3028494579
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1621537649
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1645729998
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.4217609273
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1167102403
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3486369857
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1684638935
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2782732022
/workspace/coverage/default/44.sysrst_ctrl_smoke.2851057818
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2082006005
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2250101306
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3544523974
/workspace/coverage/default/45.sysrst_ctrl_alert_test.1340357779
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.188397169
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.4229114512
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.424058976
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2399937252
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.716330512
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3914104416
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1507592999
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.924139334
/workspace/coverage/default/45.sysrst_ctrl_smoke.3653211008
/workspace/coverage/default/45.sysrst_ctrl_stress_all.400443819
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2419559004
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.520143624
/workspace/coverage/default/46.sysrst_ctrl_alert_test.413879245
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2330485017
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3176815539
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1197462633
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.4077094768
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1762682705
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2333093495
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2851283920
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3959295286
/workspace/coverage/default/46.sysrst_ctrl_smoke.3798079520
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2091084276
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.85113158
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.635273085
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3835378944
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1583689205
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2048842941
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1202429211
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2865160924
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.853403784
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1300263372
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1924416981
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2191461548
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3946159613
/workspace/coverage/default/47.sysrst_ctrl_smoke.3418246064
/workspace/coverage/default/47.sysrst_ctrl_stress_all.4206613
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2916671370
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1749263591
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2478463955
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3261762896
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3970499252
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1828272265
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1198914344
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1300743111
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1037774939
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2161400698
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.649899002
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.558351823
/workspace/coverage/default/48.sysrst_ctrl_smoke.4085265734
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3225941872
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3586966606
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2097620902
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1767024973
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3009847889
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2768277660
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1818683488
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2685056766
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3655426959
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.103499950
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.484535602
/workspace/coverage/default/49.sysrst_ctrl_smoke.1111439941
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2395392842
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1965907275
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2077657766
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.43400001
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.128592319
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1344928475
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3474889802
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.854064317
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3430446300
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2030968704
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1402051219
/workspace/coverage/default/5.sysrst_ctrl_smoke.1942743444
/workspace/coverage/default/5.sysrst_ctrl_stress_all.45596044
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1111454561
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3173399702
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2091545310
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3328271270
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2643281796
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.830967743
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.208575159
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3613722430
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2009042064
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3569589723
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2392000886
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3670348111
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3732256530
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.306213841
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2357039261
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4001706479
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3020999766
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4233598830
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.754987080
/workspace/coverage/default/6.sysrst_ctrl_smoke.1246401925
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3772270110
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2812728821
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3281942834
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.4154958064
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3413391731
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3541917699
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3024624407
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2439775060
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1229643693
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2184651600
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3920627083
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1657105778
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2210862701
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.531717327
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.219183230
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.985318458
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1393439604
/workspace/coverage/default/7.sysrst_ctrl_smoke.764964068
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3338140240
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1552447253
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2443891315
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2006245530
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.592322034
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3500020075
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1803742501
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.182524713
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1058101304
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.639884163
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1980003553
/workspace/coverage/default/8.sysrst_ctrl_alert_test.4212195082
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.882492385
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4163685381
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2654944031
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4041993699
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3901010139
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.259827546
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.601748991
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3463973830
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.46461899
/workspace/coverage/default/8.sysrst_ctrl_smoke.2145869890
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2219520956
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.307398378
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1973810067
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.4232741062
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3431725263
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2150207351
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1977999505
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3240417549
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2232001525
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2296832960
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3906708513
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2511960540
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.550383844
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2061046198
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2434958862
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2850644421
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3651763843
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.4211168596
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2311785522
/workspace/coverage/default/9.sysrst_ctrl_smoke.337393439
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.534983088
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3920854466
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.572037792
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1313064995
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.767684283
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1495056805
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.450116309
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.11069337
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1048100711

Total test records in report: 912

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3803115837	Mar 10 01:59:02 PM PDT 24	Mar 10 01:59:13 PM PDT 24	3743499886 ps
T5	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.4125423677	Mar 10 01:59:15 PM PDT 24	Mar 10 02:05:55 PM PDT 24	1272231064612 ps
T1	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.330606675	Mar 10 01:59:28 PM PDT 24	Mar 10 01:59:31 PM PDT 24	3396441511 ps
T24	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3723128073	Mar 10 01:58:26 PM PDT 24	Mar 10 01:59:24 PM PDT 24	45838789782 ps
T2	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1300743111	Mar 10 02:00:12 PM PDT 24	Mar 10 02:00:15 PM PDT 24	4579393784 ps
T25	/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.152773964	Mar 10 01:59:43 PM PDT 24	Mar 10 02:52:53 PM PDT 24	1191479819365 ps
T6	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.1159090251	Mar 10 01:59:18 PM PDT 24	Mar 10 01:59:22 PM PDT 24	2525687229 ps
T3	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3420641373	Mar 10 01:58:51 PM PDT 24	Mar 10 01:59:32 PM PDT 24	127195551717 ps
T7	/workspace/coverage/default/17.sysrst_ctrl_stress_all.2200212764	Mar 10 01:59:09 PM PDT 24	Mar 10 02:00:15 PM PDT 24	107247209468 ps
T8	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.184405458	Mar 10 01:58:53 PM PDT 24	Mar 10 02:00:10 PM PDT 24	116690094635 ps
T26	/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4233598830	Mar 10 01:58:40 PM PDT 24	Mar 10 01:58:46 PM PDT 24	2193607246 ps
T9	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.141545425	Mar 10 01:58:21 PM PDT 24	Mar 10 01:58:24 PM PDT 24	2440850276 ps
T27	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1153342011	Mar 10 01:59:33 PM PDT 24	Mar 10 01:59:39 PM PDT 24	3542310448 ps
T28	/workspace/coverage/default/13.sysrst_ctrl_stress_all.3485863527	Mar 10 01:58:50 PM PDT 24	Mar 10 01:59:10 PM PDT 24	7307803531 ps
T29	/workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3557987711	Mar 10 01:58:57 PM PDT 24	Mar 10 01:59:00 PM PDT 24	2239194324 ps
T30	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2643281796	Mar 10 02:00:20 PM PDT 24	Mar 10 02:00:53 PM PDT 24	25338612100 ps
T31	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1656282633	Mar 10 01:59:17 PM PDT 24	Mar 10 01:59:24 PM PDT 24	3676100868 ps
T51	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.4108794078	Mar 10 01:58:50 PM PDT 24	Mar 10 01:58:53 PM PDT 24	2489215981 ps
T49	/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1749263591	Mar 10 02:00:09 PM PDT 24	Mar 10 02:00:12 PM PDT 24	6558049996 ps
T10	/workspace/coverage/default/26.sysrst_ctrl_combo_detect.4049107554	Mar 10 01:59:31 PM PDT 24	Mar 10 02:00:14 PM PDT 24	68314809024 ps
T50	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1064786342	Mar 10 01:59:09 PM PDT 24	Mar 10 01:59:12 PM PDT 24	4204769383 ps
T52	/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.546979168	Mar 10 01:59:15 PM PDT 24	Mar 10 01:59:19 PM PDT 24	2529742326 ps
T59	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2091545310	Mar 10 02:00:15 PM PDT 24	Mar 10 02:03:31 PM PDT 24	76329591471 ps
T53	/workspace/coverage/default/28.sysrst_ctrl_stress_all.3224024771	Mar 10 01:59:45 PM PDT 24	Mar 10 02:02:38 PM PDT 24	140012032160 ps
T11	/workspace/coverage/default/10.sysrst_ctrl_edge_detect.219850689	Mar 10 01:58:58 PM PDT 24	Mar 10 01:59:02 PM PDT 24	2726184645 ps
T69	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1818683488	Mar 10 02:00:12 PM PDT 24	Mar 10 02:00:17 PM PDT 24	2931163667 ps
T70	/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.502636258	Mar 10 02:00:02 PM PDT 24	Mar 10 02:00:07 PM PDT 24	2102189154 ps
T62	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.61769321	Mar 10 01:59:53 PM PDT 24	Mar 10 02:00:00 PM PDT 24	3272512625 ps
T12	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.3677358366	Mar 10 01:59:10 PM PDT 24	Mar 10 02:07:32 PM PDT 24	196659362185 ps
T13	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.712822903	Mar 10 01:59:31 PM PDT 24	Mar 10 01:59:35 PM PDT 24	3020078644 ps
T71	/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.854064317	Mar 10 01:58:41 PM PDT 24	Mar 10 01:58:45 PM PDT 24	2614526607 ps
T220	/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2583914165	Mar 10 01:59:52 PM PDT 24	Mar 10 01:59:57 PM PDT 24	2946943355 ps
T14	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.4161920559	Mar 10 01:59:10 PM PDT 24	Mar 10 02:00:58 PM PDT 24	520800756752 ps
T15	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2210862701	Mar 10 01:58:40 PM PDT 24	Mar 10 01:58:48 PM PDT 24	4356621534 ps
T16	/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.822331202	Mar 10 01:59:23 PM PDT 24	Mar 10 01:59:27 PM PDT 24	5924312421 ps
T32	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3906708513	Mar 10 01:58:49 PM PDT 24	Mar 10 01:58:59 PM PDT 24	3314426267 ps
T17	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.98188229	Mar 10 01:59:34 PM PDT 24	Mar 10 02:00:22 PM PDT 24	269232150137 ps
T33	/workspace/coverage/default/22.sysrst_ctrl_alert_test.319555076	Mar 10 01:59:13 PM PDT 24	Mar 10 01:59:19 PM PDT 24	2013642515 ps
T34	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.825500843	Mar 10 01:58:24 PM PDT 24	Mar 10 02:00:09 PM PDT 24	42013575667 ps
T35	/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1797203748	Mar 10 02:00:00 PM PDT 24	Mar 10 02:00:07 PM PDT 24	3491587443 ps
T18	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3984386673	Mar 10 01:59:42 PM PDT 24	Mar 10 02:02:04 PM PDT 24	57550902388 ps
T43	/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3747857969	Mar 10 01:59:02 PM PDT 24	Mar 10 01:59:12 PM PDT 24	3570803970 ps
T44	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.4275858847	Mar 10 01:58:26 PM PDT 24	Mar 10 01:58:44 PM PDT 24	6462147594 ps
T45	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.571268128	Mar 10 01:58:26 PM PDT 24	Mar 10 01:58:31 PM PDT 24	2263507257 ps
T72	/workspace/coverage/default/3.sysrst_ctrl_stress_all.2072548108	Mar 10 01:58:34 PM PDT 24	Mar 10 01:59:04 PM PDT 24	12218309837 ps
T126	/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2610069723	Mar 10 01:59:48 PM PDT 24	Mar 10 01:59:53 PM PDT 24	2146039547 ps
T271	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1198914344	Mar 10 02:00:13 PM PDT 24	Mar 10 02:00:15 PM PDT 24	4385551350 ps
T19	/workspace/coverage/default/31.sysrst_ctrl_combo_detect.1203029506	Mar 10 01:59:31 PM PDT 24	Mar 10 02:00:35 PM PDT 24	99099057969 ps
T20	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2916671370	Mar 10 02:00:11 PM PDT 24	Mar 10 02:00:23 PM PDT 24	16870262000 ps
T262	/workspace/coverage/default/26.sysrst_ctrl_alert_test.431329677	Mar 10 01:59:19 PM PDT 24	Mar 10 01:59:21 PM PDT 24	2067156595 ps
T21	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3009847889	Mar 10 02:00:15 PM PDT 24	Mar 10 02:00:34 PM PDT 24	137770300536 ps
T73	/workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.893501494	Mar 10 01:59:51 PM PDT 24	Mar 10 02:00:00 PM PDT 24	2609723814 ps
T64	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.515948671	Mar 10 01:58:51 PM PDT 24	Mar 10 02:00:03 PM PDT 24	29804474701 ps
T263	/workspace/coverage/default/27.sysrst_ctrl_alert_test.1698343245	Mar 10 01:59:22 PM PDT 24	Mar 10 01:59:28 PM PDT 24	2015274432 ps
T282	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.924139334	Mar 10 02:00:01 PM PDT 24	Mar 10 02:00:04 PM PDT 24	2523964776 ps
T60	/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.648150194	Mar 10 02:00:24 PM PDT 24	Mar 10 02:01:00 PM PDT 24	52132829619 ps
T283	/workspace/coverage/default/3.sysrst_ctrl_smoke.3320658258	Mar 10 01:58:28 PM PDT 24	Mar 10 01:58:35 PM PDT 24	2110690265 ps
T66	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3415495971	Mar 10 01:58:50 PM PDT 24	Mar 10 01:58:57 PM PDT 24	2449517513 ps
T359	/workspace/coverage/default/48.sysrst_ctrl_smoke.4085265734	Mar 10 02:00:09 PM PDT 24	Mar 10 02:00:11 PM PDT 24	2130462009 ps
T360	/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2685056766	Mar 10 02:00:13 PM PDT 24	Mar 10 02:00:20 PM PDT 24	2613116423 ps
T22	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3546859351	Mar 10 01:58:33 PM PDT 24	Mar 10 01:58:35 PM PDT 24	2461493663 ps
T56	/workspace/coverage/default/30.sysrst_ctrl_edge_detect.2961257083	Mar 10 01:59:39 PM PDT 24	Mar 10 01:59:42 PM PDT 24	4522348742 ps
T65	/workspace/coverage/default/2.sysrst_ctrl_stress_all.2177616405	Mar 10 01:58:33 PM PDT 24	Mar 10 01:58:43 PM PDT 24	17331076410 ps
T23	/workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.607013121	Mar 10 01:59:18 PM PDT 24	Mar 10 02:00:18 PM PDT 24	24561201903 ps
T57	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.2666153663	Mar 10 01:58:52 PM PDT 24	Mar 10 01:58:55 PM PDT 24	3692095534 ps
T36	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.450097610	Mar 10 01:59:06 PM PDT 24	Mar 10 02:00:51 PM PDT 24	45624405221 ps
T67	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1924416981	Mar 10 02:00:05 PM PDT 24	Mar 10 02:00:13 PM PDT 24	2450108067 ps
T37	/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.674317969	Mar 10 01:59:16 PM PDT 24	Mar 10 02:00:47 PM PDT 24	1227915969578 ps
T63	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2530473586	Mar 10 01:59:19 PM PDT 24	Mar 10 01:59:27 PM PDT 24	3614855408 ps
T68	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1224720980	Mar 10 01:59:57 PM PDT 24	Mar 10 02:00:05 PM PDT 24	2481394960 ps
T38	/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3846347099	Mar 10 01:58:29 PM PDT 24	Mar 10 01:58:30 PM PDT 24	4496601927 ps
T55	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.619230691	Mar 10 01:59:52 PM PDT 24	Mar 10 02:02:32 PM PDT 24	65986881940 ps
T140	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.681653798	Mar 10 01:59:48 PM PDT 24	Mar 10 01:59:57 PM PDT 24	2237905404 ps
T141	/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1917662529	Mar 10 01:59:21 PM PDT 24	Mar 10 01:59:23 PM PDT 24	2208377462 ps
T142	/workspace/coverage/default/18.sysrst_ctrl_smoke.3643416016	Mar 10 01:59:19 PM PDT 24	Mar 10 01:59:26 PM PDT 24	2112084881 ps
T74	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.182524713	Mar 10 02:00:23 PM PDT 24	Mar 10 02:00:55 PM PDT 24	25839028626 ps
T143	/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.558351823	Mar 10 02:00:11 PM PDT 24	Mar 10 02:00:14 PM PDT 24	2532856647 ps
T144	/workspace/coverage/default/46.sysrst_ctrl_smoke.3798079520	Mar 10 02:00:16 PM PDT 24	Mar 10 02:00:22 PM PDT 24	2111456820 ps
T145	/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3974100862	Mar 10 01:59:07 PM PDT 24	Mar 10 01:59:10 PM PDT 24	2094112240 ps
T54	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2028766059	Mar 10 01:59:54 PM PDT 24	Mar 10 02:00:34 PM PDT 24	228082393079 ps
T97	/workspace/coverage/default/18.sysrst_ctrl_combo_detect.2303298731	Mar 10 01:59:09 PM PDT 24	Mar 10 02:02:45 PM PDT 24	86434085467 ps
T98	/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2311785522	Mar 10 01:59:05 PM PDT 24	Mar 10 01:59:12 PM PDT 24	2509706346 ps
T160	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1684638935	Mar 10 02:00:01 PM PDT 24	Mar 10 02:00:02 PM PDT 24	2158557269 ps
T161	/workspace/coverage/default/12.sysrst_ctrl_alert_test.567468831	Mar 10 01:58:50 PM PDT 24	Mar 10 01:58:53 PM PDT 24	2019454997 ps
T162	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3655983827	Mar 10 01:59:35 PM PDT 24	Mar 10 01:59:37 PM PDT 24	2641809347 ps
T163	/workspace/coverage/default/9.sysrst_ctrl_alert_test.2296832960	Mar 10 01:58:39 PM PDT 24	Mar 10 01:58:41 PM PDT 24	2047528648 ps
T164	/workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2218800609	Mar 10 01:59:45 PM PDT 24	Mar 10 01:59:47 PM PDT 24	2479553834 ps
T39	/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3093755990	Mar 10 01:59:51 PM PDT 24	Mar 10 02:01:53 PM PDT 24	406193026421 ps
T121	/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3908168604	Mar 10 01:59:18 PM PDT 24	Mar 10 01:59:28 PM PDT 24	3134943086 ps
T122	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.769395028	Mar 10 01:58:37 PM PDT 24	Mar 10 01:58:44 PM PDT 24	2510868710 ps
T183	/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.310325040	Mar 10 01:58:32 PM PDT 24	Mar 10 01:58:40 PM PDT 24	2608213683 ps
T184	/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2444039810	Mar 10 02:00:06 PM PDT 24	Mar 10 02:00:09 PM PDT 24	2189613387 ps
T185	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.985318458	Mar 10 01:58:35 PM PDT 24	Mar 10 01:58:41 PM PDT 24	2226724365 ps
T75	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.826766554	Mar 10 01:59:39 PM PDT 24	Mar 10 02:00:07 PM PDT 24	39315954166 ps
T93	/workspace/coverage/default/48.sysrst_ctrl_stress_all.3225941872	Mar 10 02:00:10 PM PDT 24	Mar 10 02:06:41 PM PDT 24	154738186495 ps
T186	/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1320331277	Mar 10 02:00:02 PM PDT 24	Mar 10 02:00:09 PM PDT 24	2480963204 ps
T76	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1444650326	Mar 10 02:00:14 PM PDT 24	Mar 10 02:02:12 PM PDT 24	53987331033 ps
T61	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1955613997	Mar 10 02:00:23 PM PDT 24	Mar 10 02:03:32 PM PDT 24	71075713550 ps
T190	/workspace/coverage/default/8.sysrst_ctrl_stress_all.2219520956	Mar 10 01:58:44 PM PDT 24	Mar 10 01:58:54 PM PDT 24	11243652627 ps
T188	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.307398378	Mar 10 01:58:48 PM PDT 24	Mar 10 01:58:55 PM PDT 24	35219198010 ps
T40	/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1381163863	Mar 10 01:59:53 PM PDT 24	Mar 10 01:59:57 PM PDT 24	4608146980 ps
T132	/workspace/coverage/default/45.sysrst_ctrl_smoke.3653211008	Mar 10 02:00:03 PM PDT 24	Mar 10 02:00:07 PM PDT 24	2117662860 ps
T133	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.346077609	Mar 10 01:59:51 PM PDT 24	Mar 10 02:03:05 PM PDT 24	140019514102 ps
T134	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.259827546	Mar 10 01:59:20 PM PDT 24	Mar 10 01:59:25 PM PDT 24	2615581934 ps
T135	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.721936277	Mar 10 01:58:45 PM PDT 24	Mar 10 01:59:22 PM PDT 24	82102929261 ps
T94	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1640884398	Mar 10 02:00:15 PM PDT 24	Mar 10 02:00:17 PM PDT 24	2818230218 ps
T41	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.945588583	Mar 10 01:58:38 PM PDT 24	Mar 10 01:58:40 PM PDT 24	8588478423 ps
T136	/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3914104416	Mar 10 02:00:07 PM PDT 24	Mar 10 02:00:14 PM PDT 24	2469914751 ps
T137	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1954633886	Mar 10 01:59:29 PM PDT 24	Mar 10 01:59:33 PM PDT 24	2471619358 ps
T138	/workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2157164084	Mar 10 01:59:09 PM PDT 24	Mar 10 01:59:11 PM PDT 24	2632007883 ps
T42	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1097310958	Mar 10 01:59:49 PM PDT 24	Mar 10 02:01:24 PM PDT 24	47508804662 ps
T226	/workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2568328291	Mar 10 01:59:01 PM PDT 24	Mar 10 01:59:03 PM PDT 24	2521817144 ps
T227	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3310305041	Mar 10 02:00:03 PM PDT 24	Mar 10 02:00:05 PM PDT 24	2631285286 ps
T228	/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.103574710	Mar 10 01:58:52 PM PDT 24	Mar 10 01:58:56 PM PDT 24	2618523491 ps
T229	/workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3170316287	Mar 10 01:59:19 PM PDT 24	Mar 10 01:59:27 PM PDT 24	2608540411 ps
T231	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3024624407	Mar 10 02:00:16 PM PDT 24	Mar 10 02:00:53 PM PDT 24	52868980896 ps
T284	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.3474075696	Mar 10 01:59:23 PM PDT 24	Mar 10 01:59:32 PM PDT 24	2512625174 ps
T123	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.658474048	Mar 10 01:59:08 PM PDT 24	Mar 10 01:59:18 PM PDT 24	188993967438 ps
T285	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.503501981	Mar 10 01:59:35 PM PDT 24	Mar 10 01:59:43 PM PDT 24	2513406285 ps
T286	/workspace/coverage/default/47.sysrst_ctrl_smoke.3418246064	Mar 10 02:00:06 PM PDT 24	Mar 10 02:00:13 PM PDT 24	2114542421 ps
T361	/workspace/coverage/default/29.sysrst_ctrl_stress_all.3267754235	Mar 10 01:59:36 PM PDT 24	Mar 10 01:59:45 PM PDT 24	12433787655 ps
T362	/workspace/coverage/default/37.sysrst_ctrl_alert_test.3126654965	Mar 10 01:59:48 PM PDT 24	Mar 10 01:59:51 PM PDT 24	2047442378 ps
T99	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.3860462426	Mar 10 01:59:45 PM PDT 24	Mar 10 02:00:22 PM PDT 24	54451796022 ps
T95	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1036871220	Mar 10 01:58:46 PM PDT 24	Mar 10 01:58:50 PM PDT 24	6292550924 ps
T58	/workspace/coverage/default/44.sysrst_ctrl_stress_all.2082006005	Mar 10 02:00:03 PM PDT 24	Mar 10 02:00:48 PM PDT 24	937660561339 ps
T156	/workspace/coverage/default/9.sysrst_ctrl_stress_all.3925500154	Mar 10 01:58:39 PM PDT 24	Mar 10 01:59:24 PM PDT 24	17592493103 ps
T363	/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.649899002	Mar 10 02:00:11 PM PDT 24	Mar 10 02:00:17 PM PDT 24	2115436447 ps
T124	/workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.949405195	Mar 10 01:59:20 PM PDT 24	Mar 10 01:59:28 PM PDT 24	4447849997 ps
T364	/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2135919806	Mar 10 01:59:28 PM PDT 24	Mar 10 01:59:36 PM PDT 24	2612258926 ps
T365	/workspace/coverage/default/6.sysrst_ctrl_smoke.1246401925	Mar 10 01:58:35 PM PDT 24	Mar 10 01:58:41 PM PDT 24	2110729154 ps
T238	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3305290020	Mar 10 01:59:05 PM PDT 24	Mar 10 01:59:30 PM PDT 24	35924609546 ps
T306	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.1983739253	Mar 10 01:59:14 PM PDT 24	Mar 10 01:59:51 PM PDT 24	59823707059 ps
T366	/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1414644559	Mar 10 01:59:51 PM PDT 24	Mar 10 01:59:57 PM PDT 24	4594289143 ps
T119	/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3397905838	Mar 10 02:00:08 PM PDT 24	Mar 10 02:00:19 PM PDT 24	3724847491 ps
T230	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3176815539	Mar 10 02:00:06 PM PDT 24	Mar 10 02:02:15 PM PDT 24	46737994854 ps
T154	/workspace/coverage/default/39.sysrst_ctrl_edge_detect.3859844607	Mar 10 01:59:54 PM PDT 24	Mar 10 02:00:03 PM PDT 24	5371090148 ps
T367	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3696425901	Mar 10 01:59:05 PM PDT 24	Mar 10 01:59:11 PM PDT 24	4866893774 ps
T368	/workspace/coverage/default/17.sysrst_ctrl_alert_test.218219327	Mar 10 01:59:14 PM PDT 24	Mar 10 01:59:21 PM PDT 24	2009884263 ps
T193	/workspace/coverage/default/34.sysrst_ctrl_edge_detect.3704696245	Mar 10 01:59:41 PM PDT 24	Mar 10 01:59:48 PM PDT 24	3032774570 ps
T369	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3775018415	Mar 10 01:59:23 PM PDT 24	Mar 10 01:59:31 PM PDT 24	2511314549 ps
T370	/workspace/coverage/default/46.sysrst_ctrl_alert_test.413879245	Mar 10 02:00:05 PM PDT 24	Mar 10 02:00:07 PM PDT 24	2040385688 ps
T120	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1583689205	Mar 10 02:00:05 PM PDT 24	Mar 10 02:00:14 PM PDT 24	3241900627 ps
T371	/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3270268904	Mar 10 01:59:22 PM PDT 24	Mar 10 01:59:25 PM PDT 24	2530364121 ps
T372	/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3964519005	Mar 10 01:59:24 PM PDT 24	Mar 10 01:59:30 PM PDT 24	3842992636 ps
T310	/workspace/coverage/default/45.sysrst_ctrl_combo_detect.4229114512	Mar 10 02:00:02 PM PDT 24	Mar 10 02:00:29 PM PDT 24	49175198071 ps
T373	/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1402051219	Mar 10 01:58:39 PM PDT 24	Mar 10 01:58:40 PM PDT 24	2565340368 ps
T125	/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.4055968307	Mar 10 02:00:04 PM PDT 24	Mar 10 02:02:00 PM PDT 24	1676692552219 ps
T374	/workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3322139903	Mar 10 01:58:21 PM PDT 24	Mar 10 01:58:27 PM PDT 24	2521688152 ps
T232	/workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.920657633	Mar 10 01:59:29 PM PDT 24	Mar 10 01:59:48 PM PDT 24	26607450372 ps
T236	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1828272265	Mar 10 02:00:10 PM PDT 24	Mar 10 02:01:48 PM PDT 24	133253627154 ps
T272	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1111454561	Mar 10 01:58:35 PM PDT 24	Mar 10 01:59:36 PM PDT 24	25003227250 ps
T375	/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.640873679	Mar 10 01:59:52 PM PDT 24	Mar 10 02:00:02 PM PDT 24	8059553697 ps
T304	/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.42646544	Mar 10 01:59:02 PM PDT 24	Mar 10 01:59:10 PM PDT 24	11406706886 ps
T233	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.592322034	Mar 10 02:00:22 PM PDT 24	Mar 10 02:02:45 PM PDT 24	60507467985 ps
T308	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.183695567	Mar 10 02:00:04 PM PDT 24	Mar 10 02:02:17 PM PDT 24	98528438424 ps
T376	/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2678245427	Mar 10 01:58:42 PM PDT 24	Mar 10 01:58:46 PM PDT 24	2521927406 ps
T377	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.745234697	Mar 10 01:59:33 PM PDT 24	Mar 10 01:59:35 PM PDT 24	3657939953 ps
T378	/workspace/coverage/default/40.sysrst_ctrl_alert_test.1298974929	Mar 10 01:59:53 PM PDT 24	Mar 10 01:59:56 PM PDT 24	2028322950 ps
T379	/workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3226558019	Mar 10 01:58:28 PM PDT 24	Mar 10 01:58:37 PM PDT 24	2611678084 ps
T157	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.2119071391	Mar 10 01:59:08 PM PDT 24	Mar 10 01:59:12 PM PDT 24	2773847900 ps
T380	/workspace/coverage/default/13.sysrst_ctrl_smoke.2956788890	Mar 10 01:58:49 PM PDT 24	Mar 10 01:58:55 PM PDT 24	2110851627 ps
T381	/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2155004019	Mar 10 02:00:01 PM PDT 24	Mar 10 02:00:05 PM PDT 24	2674441622 ps
T210	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3694904275	Mar 10 01:58:51 PM PDT 24	Mar 10 01:59:26 PM PDT 24	55365904451 ps
T382	/workspace/coverage/default/19.sysrst_ctrl_smoke.3023793104	Mar 10 01:59:23 PM PDT 24	Mar 10 01:59:26 PM PDT 24	2115973772 ps
T383	/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.447536392	Mar 10 01:59:18 PM PDT 24	Mar 10 01:59:23 PM PDT 24	2118285775 ps
T384	/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3256842883	Mar 10 01:59:35 PM PDT 24	Mar 10 01:59:39 PM PDT 24	3920330220 ps
T90	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.92304022	Mar 10 01:59:12 PM PDT 24	Mar 10 02:00:02 PM PDT 24	78596461777 ps
T112	/workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3798427734	Mar 10 01:59:12 PM PDT 24	Mar 10 01:59:14 PM PDT 24	2518075482 ps
T113	/workspace/coverage/default/1.sysrst_ctrl_smoke.3570241352	Mar 10 01:58:30 PM PDT 24	Mar 10 01:58:31 PM PDT 24	2161271567 ps
T114	/workspace/coverage/default/40.sysrst_ctrl_stress_all.2286187097	Mar 10 02:00:05 PM PDT 24	Mar 10 02:00:10 PM PDT 24	7249179865 ps
T115	/workspace/coverage/default/10.sysrst_ctrl_alert_test.1910440566	Mar 10 01:58:47 PM PDT 24	Mar 10 01:58:52 PM PDT 24	2012257768 ps
T87	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.74158437	Mar 10 01:59:14 PM PDT 24	Mar 10 01:59:15 PM PDT 24	4819023217 ps
T100	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3240417549	Mar 10 02:00:25 PM PDT 24	Mar 10 02:01:01 PM PDT 24	26085236855 ps
T116	/workspace/coverage/default/8.sysrst_ctrl_smoke.2145869890	Mar 10 01:58:44 PM PDT 24	Mar 10 01:58:52 PM PDT 24	2124409197 ps
T117	/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.830967743	Mar 10 02:00:18 PM PDT 24	Mar 10 02:03:38 PM PDT 24	83158548520 ps
T118	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1101589851	Mar 10 01:59:09 PM PDT 24	Mar 10 01:59:11 PM PDT 24	2485667634 ps
T385	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.51838271	Mar 10 01:59:39 PM PDT 24	Mar 10 01:59:41 PM PDT 24	2206333875 ps
T386	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2854044848	Mar 10 02:00:05 PM PDT 24	Mar 10 02:00:07 PM PDT 24	9629879500 ps
T273	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3863389433	Mar 10 01:59:15 PM PDT 24	Mar 10 01:59:26 PM PDT 24	3535613286 ps
T204	/workspace/coverage/default/13.sysrst_ctrl_edge_detect.2876621566	Mar 10 01:58:58 PM PDT 24	Mar 10 02:07:02 PM PDT 24	646126479941 ps
T387	/workspace/coverage/default/18.sysrst_ctrl_alert_test.655804482	Mar 10 01:59:15 PM PDT 24	Mar 10 01:59:23 PM PDT 24	2009439012 ps
T388	/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3651763843	Mar 10 01:58:42 PM PDT 24	Mar 10 01:58:44 PM PDT 24	2506529278 ps
T389	/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.4118229162	Mar 10 01:59:20 PM PDT 24	Mar 10 01:59:24 PM PDT 24	6579652994 ps
T390	/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3855743596	Mar 10 01:58:30 PM PDT 24	Mar 10 01:58:34 PM PDT 24	2472414223 ps
T391	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2088336603	Mar 10 01:59:32 PM PDT 24	Mar 10 01:59:33 PM PDT 24	2707647607 ps
T339	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.3732892743	Mar 10 01:59:11 PM PDT 24	Mar 10 02:03:32 PM PDT 24	99888561983 ps
T392	/workspace/coverage/default/35.sysrst_ctrl_pin_override_test.236816647	Mar 10 01:59:39 PM PDT 24	Mar 10 01:59:40 PM PDT 24	2588867857 ps
T194	/workspace/coverage/default/44.sysrst_ctrl_edge_detect.4217609273	Mar 10 02:00:01 PM PDT 24	Mar 10 02:00:10 PM PDT 24	3161551591 ps
T393	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3016707356	Mar 10 01:58:32 PM PDT 24	Mar 10 01:58:34 PM PDT 24	2879052263 ps
T394	/workspace/coverage/default/30.sysrst_ctrl_alert_test.605690236	Mar 10 01:59:27 PM PDT 24	Mar 10 01:59:29 PM PDT 24	2040824917 ps
T395	/workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1266192025	Mar 10 01:59:49 PM PDT 24	Mar 10 02:00:02 PM PDT 24	3948873722 ps
T237	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.4022308727	Mar 10 01:59:16 PM PDT 24	Mar 10 02:00:12 PM PDT 24	79717917777 ps
T307	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.624524350	Mar 10 01:59:28 PM PDT 24	Mar 10 01:59:39 PM PDT 24	67146144422 ps
T158	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.302186815	Mar 10 02:00:05 PM PDT 24	Mar 10 02:00:11 PM PDT 24	2914568313 ps
T101	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3440789752	Mar 10 02:00:26 PM PDT 24	Mar 10 02:01:00 PM PDT 24	51658034075 ps
T396	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.606675161	Mar 10 01:59:50 PM PDT 24	Mar 10 01:59:56 PM PDT 24	5062386135 ps
T397	/workspace/coverage/default/5.sysrst_ctrl_stress_all.45596044	Mar 10 01:58:41 PM PDT 24	Mar 10 01:59:04 PM PDT 24	7935866123 ps
T102	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.593314708	Mar 10 01:59:51 PM PDT 24	Mar 10 02:02:27 PM PDT 24	222428681404 ps
T398	/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3131085070	Mar 10 01:59:09 PM PDT 24	Mar 10 01:59:10 PM PDT 24	2684299650 ps
T206	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.3471191652	Mar 10 01:59:09 PM PDT 24	Mar 10 01:59:12 PM PDT 24	3522707205 ps
T399	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2061046198	Mar 10 01:58:47 PM PDT 24	Mar 10 01:58:50 PM PDT 24	3083905193 ps
T400	/workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.743662308	Mar 10 01:59:39 PM PDT 24	Mar 10 01:59:44 PM PDT 24	2613421618 ps
T401	/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.601748991	Mar 10 01:58:50 PM PDT 24	Mar 10 01:58:54 PM PDT 24	2457461437 ps
T402	/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3729864035	Mar 10 01:59:18 PM PDT 24	Mar 10 01:59:28 PM PDT 24	3432136581 ps
T403	/workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1972638820	Mar 10 01:58:48 PM PDT 24	Mar 10 01:58:58 PM PDT 24	4297511576 ps
T404	/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.453369731	Mar 10 01:59:50 PM PDT 24	Mar 10 01:59:54 PM PDT 24	2783090187 ps
T405	/workspace/coverage/default/34.sysrst_ctrl_alert_test.173251745	Mar 10 01:59:48 PM PDT 24	Mar 10 01:59:53 PM PDT 24	2023010265 ps
T406	/workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3476519444	Mar 10 01:59:36 PM PDT 24	Mar 10 01:59:40 PM PDT 24	2252786901 ps
T407	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1721721875	Mar 10 01:58:54 PM PDT 24	Mar 10 01:58:56 PM PDT 24	2636753364 ps
T103	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.4194013185	Mar 10 01:59:43 PM PDT 24	Mar 10 02:00:23 PM PDT 24	62188664192 ps
T408	/workspace/coverage/default/1.sysrst_ctrl_alert_test.3744124019	Mar 10 01:58:29 PM PDT 24	Mar 10 01:58:31 PM PDT 24	2038732969 ps
T409	/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.143570300	Mar 10 01:59:17 PM PDT 24	Mar 10 01:59:23 PM PDT 24	2589771097 ps
T410	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1037774939	Mar 10 02:00:14 PM PDT 24	Mar 10 02:00:18 PM PDT 24	2617614388 ps
T274	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.599027308	Mar 10 01:59:40 PM PDT 24	Mar 10 02:00:23 PM PDT 24	16564648676 ps
T159	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2756646070	Mar 10 02:00:04 PM PDT 24	Mar 10 02:01:00 PM PDT 24	50765621210 ps
T411	/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.439414699	Mar 10 01:59:11 PM PDT 24	Mar 10 01:59:15 PM PDT 24	2099350153 ps
T91	/workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2097430092	Mar 10 01:59:11 PM PDT 24	Mar 10 01:59:39 PM PDT 24	134183487742 ps
T146	/workspace/coverage/default/6.sysrst_ctrl_stress_all.3772270110	Mar 10 01:58:42 PM PDT 24	Mar 10 02:05:07 PM PDT 24	301271944083 ps
T147	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.639884163	Mar 10 02:00:22 PM PDT 24	Mar 10 02:00:57 PM PDT 24	42267934728 ps
T148	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.1289960291	Mar 10 01:59:44 PM PDT 24	Mar 10 02:04:56 PM PDT 24	127194057831 ps
T149	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.860547596	Mar 10 01:59:13 PM PDT 24	Mar 10 01:59:17 PM PDT 24	4571605627 ps
T150	/workspace/coverage/default/48.sysrst_ctrl_alert_test.2478463955	Mar 10 02:00:12 PM PDT 24	Mar 10 02:00:14 PM PDT 24	2037155186 ps
T151	/workspace/coverage/default/46.sysrst_ctrl_combo_detect.368898088	Mar 10 02:00:04 PM PDT 24	Mar 10 02:03:01 PM PDT 24	136030002596 ps
T152	/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4041993699	Mar 10 01:58:52 PM PDT 24	Mar 10 01:59:00 PM PDT 24	3118772287 ps
T153	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2232001525	Mar 10 02:00:23 PM PDT 24	Mar 10 02:04:42 PM PDT 24	99182798909 ps
T88	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1791307878	Mar 10 01:59:11 PM PDT 24	Mar 10 02:00:29 PM PDT 24	34883657599 ps
T275	/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.909487470	Mar 10 02:00:01 PM PDT 24	Mar 10 02:01:30 PM PDT 24	35059081767 ps
T239	/workspace/coverage/default/11.sysrst_ctrl_stress_all.4090807594	Mar 10 01:58:51 PM PDT 24	Mar 10 02:03:45 PM PDT 24	107340222471 ps
T412	/workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2544226921	Mar 10 01:59:17 PM PDT 24	Mar 10 01:59:21 PM PDT 24	2470563263 ps
T413	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3245570922	Mar 10 01:59:08 PM PDT 24	Mar 10 01:59:16 PM PDT 24	2507578268 ps
T414	/workspace/coverage/default/24.sysrst_ctrl_smoke.1226779891	Mar 10 01:59:16 PM PDT 24	Mar 10 01:59:24 PM PDT 24	2110383285 ps
T415	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1869805518	Mar 10 01:58:57 PM PDT 24	Mar 10 01:59:04 PM PDT 24	2608168785 ps
T248	/workspace/coverage/default/7.sysrst_ctrl_combo_detect.3920627083	Mar 10 01:58:49 PM PDT 24	Mar 10 02:02:47 PM PDT 24	85703749122 ps
T312	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2443891315	Mar 10 02:00:19 PM PDT 24	Mar 10 02:02:18 PM PDT 24	81557749665 ps
T416	/workspace/coverage/default/4.sysrst_ctrl_smoke.2536185892	Mar 10 01:58:31 PM PDT 24	Mar 10 01:58:35 PM PDT 24	2121579249 ps
T417	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2434958862	Mar 10 01:58:39 PM PDT 24	Mar 10 01:58:42 PM PDT 24	3008137573 ps
T418	/workspace/coverage/default/29.sysrst_ctrl_alert_test.2535155546	Mar 10 01:59:29 PM PDT 24	Mar 10 01:59:30 PM PDT 24	2117550032 ps
T419	/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.188397169	Mar 10 02:00:03 PM PDT 24	Mar 10 02:00:12 PM PDT 24	3379918395 ps
T420	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.46461899	Mar 10 01:58:46 PM PDT 24	Mar 10 01:58:53 PM PDT 24	2510525858 ps
T277	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2632614957	Mar 10 01:59:16 PM PDT 24	Mar 10 01:59:54 PM PDT 24	13197606724 ps
T421	/workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1246785825	Mar 10 02:00:06 PM PDT 24	Mar 10 02:00:12 PM PDT 24	4627204432 ps
T422	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.209848188	Mar 10 01:58:54 PM PDT 24	Mar 10 01:58:57 PM PDT 24	3663786208 ps
T423	/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3463973830	Mar 10 01:58:49 PM PDT 24	Mar 10 01:58:55 PM PDT 24	2089362129 ps
T424	/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4138675406	Mar 10 01:58:32 PM PDT 24	Mar 10 02:09:46 PM PDT 24	258112729922 ps
T355	/workspace/coverage/default/46.sysrst_ctrl_stress_all.2091084276	Mar 10 02:00:15 PM PDT 24	Mar 10 02:00:52 PM PDT 24	14458021942 ps
T425	/workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1369520119	Mar 10 01:59:44 PM PDT 24	Mar 10 01:59:51 PM PDT 24	3956481049 ps
T426	/workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1090952034	Mar 10 01:59:18 PM PDT 24	Mar 10 01:59:21 PM PDT 24	2639118956 ps
T104	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1958176435	Mar 10 01:58:32 PM PDT 24	Mar 10 01:59:27 PM PDT 24	21083091353 ps
T427	/workspace/coverage/default/49.sysrst_ctrl_stress_all.2395392842	Mar 10 02:00:14 PM PDT 24	Mar 10 02:00:31 PM PDT 24	11718270059 ps
T428	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1645729998	Mar 10 02:00:06 PM PDT 24	Mar 10 02:00:17 PM PDT 24	5043738940 ps