Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1578

1

T3

25

T7

3

T8

8

auto[1]

626

1

T3

11

T7

8

T8

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1585

1

T3

36

T7

8

T8

12

auto[1]

619

1

T7

3

T10

4

T53

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1686

1

T3

36

T7

4

T8

11

auto[1]

518

1

T7

7

T8

1

T10

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1697

1

T3

36

T7

4

T8

12

auto[1]

507

1

T7

7

T10

2

T53

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2048

1

T3

36

T7

11

T8

12

auto[1]

156

1

T60

7

T55

3

T76

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2044

1

T3

25

T7

11

T8

12

auto[1]

160

1

T3

11

T55

2

T61

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1984

1

T3

34

T7

11

T8

12

auto[1]

220

1

T3

2

T60

1

T55

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2045

1

T3

34

T7

11

T8

12

auto[1]

159

1

T3

2

T61

4

T237

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2009

1

T3

36

T7

11

T8

12

auto[1]

195

1

T60

1

T55

4

T61

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1645

1

T3

36

T7

11

T12

17

auto[1]

559

1

T8

12

T10

6

T53

13

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	752	1			T7	11		T8	11		T10	6
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	70	1			T60	1		T76	2		T233	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	74	1			T55	4		T117	4		T153	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T60	1		T312	1		T322	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	61	1			T237	4		T323	4		T319	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	15	1			T61	4		T321	1		T313	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	11	1			T324	3		T325	2		T320	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T326	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	78	1			T61	3		T135	6		T327	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	25	1			T60	1		T55	3		T230	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	28	1			T236	8		T103	1		T328	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	21	1			T237	4		T329	1		T83	12
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T330	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T85	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	52	1			T3	9		T321	1		T322	8
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	9	1			T233	5		T331	1		T332	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	33	1			T61	2		T236	7		T312	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T316	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	11	1			T324	6		T319	4		T333	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T327	2		T330	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T331	1		T334	4		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	17	1			T55	2		T325	10		T335	1
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T233	1		T83	3		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T3	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T101	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

96

1

T3

11

T39

1

T210

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

79

1

T8

8

T53

6

T233

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

58

1

T8

3

T12

6

T19

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T55

3

T93

12

T236

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

69

1

T7

4

T55

2

T93

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T17

5

T133

5

T230

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T99

1

T238

1

T91

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

115

1

T60

1

T54

8

T306

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T7

4

T61

2

T239

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T53

3

T21

6

T76

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T54

2

T336

1

T337

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T17

2

T102

4

T91

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T12

3

T338

3

T318

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T10

2

T17

2

T306

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T17

1

T307

2

T91

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

70

1

T12

14

T54

10

T102

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

78

1

T21

8

T238

1

T308

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T60

1

T54

2

T39

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T135

3

T148

3

T248

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T311

7

T337

6

T240

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T61

3

T133

3

T135

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T93

4

T99

2

T312

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T12

1

T21

4

T97

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

58

1

T133

5

T91

5

T327

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T19

3

T55

4

T339

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T10

4

T19

4

T97

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T306

1

T332

4

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T7

3

T60

1

T308

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T308

2

T340

3

T326

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T53

1

T341

2

T342

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T53

1

T343

1

T245

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded