Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T7

18

T52

8

T17

29

auto[1]

1158

1

T7

22

T52

12

T17

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T7

9

T52

6

T17

16

from_0to1

547

1

T7

8

T52

6

T17

16

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1167

1

T7

22

T52

11

T17

28

auto[1]

1121

1

T7

18

T52

9

T17

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T7

24

T52

11

T17

28

auto[1]

1130

1

T7

16

T52

9

T17

32

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T7

2

T17

2

T64

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T52

1

T17

2

T64

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T7

2

T52

1

T17

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T17

2

T64

5

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T7

1

T52

1

T98

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T52

1

T17

3

T64

3

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T7

1

T17

2

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T7

1

T52

2

T17

3

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T7

1

T52

2

T17

2

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T7

3

T52

1

T17

4

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T52

1

T17

2

T282

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T7

1

T64

1

T282

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T7

1

T52

1

T17

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T7

1

T17

3

T64

2

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T17

2

T64

1

T282

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T7

3

T52

1

T17

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1183

1

T7

19

T52

12

T17

39

auto[1]

1105

1

T7

21

T52

8

T17

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T7

11

T52

6

T17

15

from_0to1

549

1

T7

11

T52

5

T17

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T7

17

T52

11

T17

32

auto[1]

1133

1

T7

23

T52

9

T17

28

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T7

22

T52

10

T17

30

auto[1]

1140

1

T7

18

T52

10

T17

30

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T52

1

T17

3

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T52

1

T17

2

T64

3

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T7

2

T52

2

T17

7

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T7

1

T64

4

T39

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T7

1

T17

2

T64

2

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T52

1

T17

3

T64

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T7

3

T64

1

T282

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T17

4

T64

2

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T7

2

T17

1

T64

2

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T7

1

T143

1

T39

6

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T7

2

T17

1

T64

3

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T7

3

T52

2

T17

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T7

3

T52

2

T17

2

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T7

1

T64

1

T98

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T7

3

T64

3

T282

1

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T52

2

T17

4

T64

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T7

21

T52

11

T17

31

auto[1]

1157

1

T7

19

T52

9

T17

29

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T7

9

T52

6

T17

15

from_0to1

542

1

T7

10

T52

7

T17

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T7

14

T52

8

T17

29

auto[1]

1148

1

T7

26

T52

12

T17

31

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T7

19

T52

9

T17

35

auto[1]

1112

1

T7

21

T52

11

T17

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T64

3

T282

1

T143

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T7

1

T52

1

T17

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T7

2

T52

1

T17

4

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T7

2

T52

2

T17

4

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T52

1

T17

3

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T7

3

T52

1

T17

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T7

3

T17

2

T64

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T7

1

T64

1

T143

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T7

2

T17

2

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T52

1

T17

1

T64

2

auto[1]

from_1to0

auto[1]

auto[0]

84

1

T7

2

T17

1

T64

6

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T52

1

T17

1

T282

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T52

1

T64

2

T98

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T7

2

T17

3

T282

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T7

1

T52

1

T17

5

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T52

3

T17

1

T64

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T7

14

T52

10

T17

24

auto[1]

1109

1

T7

26

T52

10

T17

36

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T7

10

T52

4

T17

14

from_0to1

548

1

T7

10

T52

4

T17

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T7

22

T52

9

T17

35

auto[1]

1153

1

T7

18

T52

11

T17

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T7

24

T52

11

T17

31

auto[1]

1136

1

T7

16

T52

9

T17

29

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T17

3

T64

2

T282

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T52

1

T17

2

T64

3

auto[0]

from_1to0

auto[1]

auto[0]

86

1

T7

3

T52

1

T17

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T17

3

T282

1

T143

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T7

1

T64

2

T122

2

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T52

1

T17

2

T64

2

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T7

1

T52

1

T17

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T64

1

T282

2

T143

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T7

1

T64

1

T39

2

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T7

1

T52

1

T17

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T7

3

T52

1

T17

3

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T7

2

T17

1

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T7

4

T52

1

T17

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T7

1

T52

1

T17

3

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T7

1

T17

2

T64

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T7

2

T17

4

T64

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T7

21

T52

4

T17

26

auto[1]

1171

1

T7

19

T52

16

T17

34

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T7

9

T52

5

T17

12

from_0to1

544

1

T7

9

T52

4

T17

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T7

16

T52

9

T17

28

auto[1]

1155

1

T7

24

T52

11

T17

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T7

18

T52

11

T17

25

auto[1]

1162

1

T7

22

T52

9

T17

35

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T64

1

T282

2

T226

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T17

3

T64

4

T282

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T7

2

T64

1

T143

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T7

2

T17

2

T64

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T7

1

T17

2

T282

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T7

1

T17

3

T143

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T7

3

T17

2

T64

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T17

1

T64

2

T282

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T7

2

T52

1

T17

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T7

2

T52

1

T64

3

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T7

1

T52

2

T17

2

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T52

1

T17

4

T64

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T52

2

T64

3

T98

1

auto[1]

from_0to1

auto[0]

auto[1]

78

1

T52

1

T17

1

T64

3

auto[1]

from_0to1

auto[1]

auto[0]

82

1

T7

1

T17

2

T64

5

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T7

3

T52

1

T17

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T7

22

T52

7

T17

26

auto[1]

1133

1

T7

18

T52

13

T17

34

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

551

1

T7

11

T52

5

T17

17

from_0to1

545

1

T7

12

T52

5

T17

18

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T7

23

T52

6

T17

28

auto[1]

1131

1

T7

17

T52

14

T17

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T7

21

T52

15

T17

27

auto[1]

1149

1

T7

19

T52

5

T17

33

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T7

1

T17

1

T64

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T7

1

T17

2

T64

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T7

1

T52

1

T17

3

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T64

3

T143

1

T98

2

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T7

1

T52

1

T17

5

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T7

1

T17

2

T64

4

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T7

1

T17

2

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T7

4

T52

1

T64

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T7

4

T52

1

T17

1

auto[1]

from_1to0

auto[0]

auto[1]

87

1

T7

1

T17

4

T143

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T7

2

T52

3

T17

4

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T7

1

T17

2

T64

4

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T7

1

T52

1

T17

2

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T7

2

T17

1

T98

2

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T7

2

T52

1

T17

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T52

1

T17

4

T39

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1177

1

T7

24

T52

14

T17

29

auto[1]

1111

1

T7

16

T52

6

T17

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

568

1

T7

11

T52

3

T17

13

from_0to1

578

1

T7

11

T52

4

T17

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T7

19

T52

11

T17

32

auto[1]

1133

1

T7

21

T52

9

T17

28

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T7

24

T52

8

T17

29

auto[1]

1122

1

T7

16

T52

12

T17

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T7

2

T17

1

T64

4

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T7

3

T52

1

T64

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T7

1

T52

1

T64

2

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T7

1

T52

1

T17

4

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T7

1

T52

1

T17

3

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T7

1

T52

1

T17

1

auto[0]

from_0to1

auto[1]

auto[0]

81

1

T7

3

T52

1

T17

1

auto[0]

from_0to1

auto[1]

auto[1]

87

1

T7

1

T52

1

T17

2

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T7

1

T17

3

T64

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T17

2

T282

2

T98

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T7

2

T17

3

T64

2

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T7

1

T64

3

T98

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T17

2

T64

3

T122

2

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T17

2

T64

3

T282

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T7

2

T17

2

T64

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T7

3

T282

1

T39

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T7

24

T52

13

T17

34

auto[1]

1137

1

T7

16

T52

7

T17

26

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

556

1

T7

12

T52

3

T17

14

from_0to1

561

1

T7

12

T52

4

T17

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T7

19

T52

11

T17

26

auto[1]

1161

1

T7

21

T52

9

T17

34

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T7

21

T52

7

T17

29

auto[1]

1151

1

T7

19

T52

13

T17

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T7

3

T17

3

T64

4

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T7

5

T52

1

T17

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T7

1

T17

3

T64

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T52

1

T17

3

T64

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T7

1

T17

3

T64

2

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T7

2

T52

2

T17

3

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T7

3

T52

2

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T7

2

T17

1

T64

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T7

2

T17

1

T282

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T52

1

T17

1

T64

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T7

1

T64

1

T282

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T17

1

T64

3

T98

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T17

1

T64

2

T39

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T17

3

T64

2

T143

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T7

3

T17

1

T64

2

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T7

1

T17

2

T64

2