Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120021

1

T4

6

T5

12

T1

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144711	1			T4	8		T5	16		T1	6
values[0x0]	66537	1			T4	3		T5	5		T1	1
values[0x1]	67452	1			T4	4		T5	2		T1	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150286

1

T4

11

T5

15

T1

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	772	1			T3	4		T7	3		T8	1
valid_sources[0x01]	1270	1			T3	6		T7	1		T8	1
valid_sources[0x02]	875	1			T3	4		T7	3		T30	5
valid_sources[0x03]	1019	1			T24	5		T3	4		T7	4
valid_sources[0x04]	1154	1			T24	3		T3	4		T7	9
valid_sources[0x05]	873	1			T24	3		T3	5		T8	2
valid_sources[0x06]	925	1			T5	1		T3	5		T7	2
valid_sources[0x07]	1379	1			T5	1		T24	1		T3	2
valid_sources[0x08]	1111	1			T5	1		T3	3		T7	6
valid_sources[0x09]	808	1			T24	6		T3	2		T7	1
valid_sources[0x0a]	862	1			T24	1		T3	7		T8	1
valid_sources[0x0b]	1087	1			T24	4		T3	4		T7	3
valid_sources[0x0c]	843	1			T24	8		T3	7		T7	2
valid_sources[0x0d]	2316	1			T24	5		T3	4		T7	3
valid_sources[0x0e]	1038	1			T5	1		T3	10		T7	3
valid_sources[0x0f]	1195	1			T3	6		T7	1		T8	2
valid_sources[0x10]	1702	1			T3	7		T7	3		T8	1
valid_sources[0x11]	937	1			T24	5		T3	8		T7	4
valid_sources[0x12]	1649	1			T24	6		T3	2		T7	1
valid_sources[0x13]	788	1			T3	4		T7	2		T8	3
valid_sources[0x14]	978	1			T24	1		T3	3		T7	4
valid_sources[0x15]	1091	1			T24	2		T3	6		T7	3
valid_sources[0x16]	1119	1			T24	3		T3	8		T7	3
valid_sources[0x17]	880	1			T24	9		T3	9		T7	1
valid_sources[0x18]	906	1			T3	2		T7	2		T8	1
valid_sources[0x19]	987	1			T24	8		T3	3		T7	7
valid_sources[0x1a]	996	1			T1	1		T3	2		T7	3
valid_sources[0x1b]	1109	1			T24	1		T3	2		T7	2
valid_sources[0x1c]	909	1			T24	3		T3	4		T7	1
valid_sources[0x1d]	926	1			T3	4		T7	1		T8	2
valid_sources[0x1e]	833	1			T24	2		T3	9		T7	1
valid_sources[0x1f]	932	1			T3	7		T7	3		T8	5
valid_sources[0x20]	964	1			T24	1		T3	6		T7	3
valid_sources[0x21]	1519	1			T24	1		T3	1		T7	2
valid_sources[0x22]	1045	1			T3	4		T7	5		T8	3
valid_sources[0x23]	1120	1			T3	5		T7	11		T8	4
valid_sources[0x24]	1272	1			T3	5		T7	5		T8	4
valid_sources[0x25]	1151	1			T3	2		T7	3		T8	2
valid_sources[0x26]	950	1			T24	3		T3	2		T7	2
valid_sources[0x27]	835	1			T24	3		T3	8		T7	3
valid_sources[0x28]	1370	1			T24	5		T3	4		T7	6
valid_sources[0x29]	916	1			T3	4		T7	8		T8	5
valid_sources[0x2a]	1052	1			T24	5		T3	6		T7	2
valid_sources[0x2b]	890	1			T5	1		T6	9		T3	4
valid_sources[0x2c]	1235	1			T4	1		T3	6		T7	6
valid_sources[0x2d]	907	1			T5	1		T3	5		T7	6
valid_sources[0x2e]	980	1			T3	3		T7	3		T28	2
valid_sources[0x2f]	987	1			T24	7		T3	4		T7	5
valid_sources[0x30]	1037	1			T3	3		T7	2		T8	2
valid_sources[0x31]	990	1			T4	1		T24	1		T3	4
valid_sources[0x32]	1003	1			T5	1		T1	1		T3	5
valid_sources[0x33]	927	1			T24	1		T3	4		T7	2
valid_sources[0x34]	1133	1			T24	1		T3	5		T7	2
valid_sources[0x35]	1132	1			T24	2		T3	4		T7	2
valid_sources[0x36]	1101	1			T24	3		T3	3		T7	4
valid_sources[0x37]	985	1			T7	9		T8	3		T30	2
valid_sources[0x38]	1128	1			T24	2		T3	5		T7	3
valid_sources[0x39]	871	1			T1	2		T24	1		T3	6
valid_sources[0x3a]	962	1			T24	2		T3	1		T7	3
valid_sources[0x3b]	1260	1			T24	12		T3	7		T7	2
valid_sources[0x3c]	1071	1			T1	2		T24	6		T3	4
valid_sources[0x3d]	877	1			T3	7		T7	6		T8	2
valid_sources[0x3e]	994	1			T24	2		T3	7		T7	3
valid_sources[0x3f]	1607	1			T24	3		T3	2		T7	4
valid_sources[0x40]	988	1			T3	5		T8	2		T53	8
valid_sources[0x41]	1190	1			T5	1		T1	1		T24	6
valid_sources[0x42]	875	1			T3	2		T7	3		T28	1
valid_sources[0x43]	816	1			T24	6		T3	7		T7	5
valid_sources[0x44]	942	1			T4	1		T1	1		T24	2
valid_sources[0x45]	1131	1			T3	1		T7	1		T8	1
valid_sources[0x46]	1004	1			T24	2		T3	4		T7	3
valid_sources[0x47]	935	1			T24	5		T3	5		T7	4
valid_sources[0x48]	904	1			T5	1		T3	2		T7	2
valid_sources[0x49]	1135	1			T3	7		T7	2		T8	2
valid_sources[0x4a]	1134	1			T24	2		T3	4		T7	8
valid_sources[0x4b]	820	1			T3	7		T7	3		T8	8
valid_sources[0x4c]	1064	1			T24	2		T3	8		T7	3
valid_sources[0x4d]	813	1			T24	3		T3	3		T7	2
valid_sources[0x4e]	912	1			T24	6		T3	7		T7	4
valid_sources[0x4f]	806	1			T24	6		T2	3		T3	2
valid_sources[0x50]	1435	1			T3	3		T7	5		T30	4
valid_sources[0x51]	795	1			T3	5		T7	3		T8	3
valid_sources[0x52]	758	1			T24	3		T3	9		T7	2
valid_sources[0x53]	1287	1			T24	5		T3	2		T7	1
valid_sources[0x54]	1931	1			T24	1		T3	2		T7	3
valid_sources[0x55]	1121	1			T3	5		T7	4		T8	1
valid_sources[0x56]	1147	1			T3	7		T7	4		T8	1
valid_sources[0x57]	886	1			T5	1		T24	1		T2	2
valid_sources[0x58]	1032	1			T1	1		T24	1		T3	5
valid_sources[0x59]	1121	1			T3	9		T7	3		T8	3
valid_sources[0x5a]	1195	1			T24	4		T3	1		T7	3
valid_sources[0x5b]	1215	1			T3	4		T7	2		T8	1
valid_sources[0x5c]	1009	1			T24	2		T3	11		T7	4
valid_sources[0x5d]	941	1			T24	2		T3	2		T7	2
valid_sources[0x5e]	879	1			T3	4		T7	4		T8	3
valid_sources[0x5f]	931	1			T3	5		T7	10		T8	1
valid_sources[0x60]	942	1			T24	2		T3	9		T7	3
valid_sources[0x61]	785	1			T3	8		T7	6		T8	2
valid_sources[0x62]	903	1			T3	5		T7	6		T8	1
valid_sources[0x63]	906	1			T3	7		T7	3		T8	2
valid_sources[0x64]	1112	1			T3	5		T7	5		T8	3
valid_sources[0x65]	878	1			T24	4		T3	2		T7	3
valid_sources[0x66]	1057	1			T3	6		T7	2		T8	1
valid_sources[0x67]	886	1			T3	12		T7	2		T8	3
valid_sources[0x68]	1036	1			T3	6		T7	7		T8	3
valid_sources[0x69]	975	1			T24	5		T3	2		T7	4
valid_sources[0x6a]	978	1			T3	5		T7	3		T8	2
valid_sources[0x6b]	2449	1			T3	10		T7	1		T8	1
valid_sources[0x6c]	1036	1			T24	4		T3	5		T7	1
valid_sources[0x6d]	816	1			T24	4		T3	6		T7	3
valid_sources[0x6e]	1145	1			T3	10		T7	6		T8	2
valid_sources[0x6f]	2073	1			T3	3		T7	5		T8	1
valid_sources[0x70]	1636	1			T24	7		T2	2		T3	4
valid_sources[0x71]	1778	1			T5	1		T3	6		T26	3
valid_sources[0x72]	1394	1			T4	1		T24	1		T3	2
valid_sources[0x73]	993	1			T24	5		T3	2		T7	6
valid_sources[0x74]	1122	1			T24	1		T3	5		T7	1
valid_sources[0x75]	1236	1			T5	1		T24	1		T3	3
valid_sources[0x76]	874	1			T3	3		T7	1		T28	2
valid_sources[0x77]	918	1			T24	5		T3	3		T7	4
valid_sources[0x78]	837	1			T24	8		T3	1		T7	2
valid_sources[0x79]	1036	1			T24	1		T3	4		T7	2
valid_sources[0x7a]	911	1			T24	4		T3	1		T7	3
valid_sources[0x7b]	990	1			T3	4		T7	4		T8	3
valid_sources[0x7c]	872	1			T2	1		T3	3		T7	4
valid_sources[0x7d]	832	1			T5	1		T24	1		T3	5
valid_sources[0x7e]	1086	1			T3	1		T7	6		T8	3
valid_sources[0x7f]	847	1			T3	6		T7	4		T8	2
valid_sources[0x80]	1027	1			T24	1		T3	6		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65285

1

T4

4

T5

9

T1

3

values[0x0]

all_enables

biggest_size

32119

1

T4

1

T5

2

T24

71

values[0x1]

all_enables

biggest_size

22617

1

T4

1

T5

1

T1

2