Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1193245780	9728	0	0
auto_block_debounce_ctl_rd_A	1193245780	1417	0	0
auto_block_out_ctl_rd_A	1193245780	2238	0	0
com_det_ctl_0_rd_A	1193245780	3202	0	0
com_det_ctl_1_rd_A	1193245780	3451	0	0
com_det_ctl_2_rd_A	1193245780	3376	0	0
com_det_ctl_3_rd_A	1193245780	3297	0	0
com_out_ctl_0_rd_A	1193245780	3918	0	0
com_out_ctl_1_rd_A	1193245780	3953	0	0
com_out_ctl_2_rd_A	1193245780	3819	0	0
com_out_ctl_3_rd_A	1193245780	3902	0	0
com_pre_det_ctl_0_rd_A	1193245780	1028	0	0
com_pre_det_ctl_1_rd_A	1193245780	1028	0	0
com_pre_det_ctl_2_rd_A	1193245780	1050	0	0
com_pre_det_ctl_3_rd_A	1193245780	937	0	0
com_pre_sel_ctl_0_rd_A	1193245780	3995	0	0
com_pre_sel_ctl_1_rd_A	1193245780	4263	0	0
com_pre_sel_ctl_2_rd_A	1193245780	4107	0	0
com_pre_sel_ctl_3_rd_A	1193245780	3961	0	0
com_sel_ctl_0_rd_A	1193245780	4000	0	0
com_sel_ctl_1_rd_A	1193245780	4147	0	0
com_sel_ctl_2_rd_A	1193245780	4285	0	0
com_sel_ctl_3_rd_A	1193245780	4347	0	0
ec_rst_ctl_rd_A	1193245780	1961	0	0
intr_enable_rd_A	1193245780	1489	0	0
key_intr_ctl_rd_A	1193245780	4116	0	0
key_intr_debounce_ctl_rd_A	1193245780	1036	0	0
key_invert_ctl_rd_A	1193245780	5278	0	0
pin_allowed_ctl_rd_A	1193245780	5926	0	0
pin_out_ctl_rd_A	1193245780	4936	0	0
pin_out_value_rd_A	1193245780	5124	0	0
regwen_rd_A	1193245780	1050	0	0
ulp_ac_debounce_ctl_rd_A	1193245780	1106	0	0
ulp_ctl_rd_A	1193245780	1080	0	0
ulp_lid_debounce_ctl_rd_A	1193245780	1182	0	0
ulp_pwrb_debounce_ctl_rd_A	1193245780	1058	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	9728	0	0
T17	160791	9	0	0
T18	505676	11	0	0
T20	0	12	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T36	0	14	0	0
T39	0	15	0	0
T42	0	18	0	0
T43	342783	0	0	0
T44	639751	2	0	0
T45	149384	0	0	0
T54	0	2	0	0
T64	0	22	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T188	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1417	0	0
T10	163954	0	0	0
T17	0	19	0	0
T18	0	27	0	0
T23	0	24	0	0
T27	170033	15	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	12	0	0
T32	0	1	0	0
T39	0	18	0	0
T44	0	6	0	0
T49	51022	0	0	0
T50	52392	0	0	0
T51	69697	0	0	0
T52	68303	0	0	0
T272	0	10	0	0
T273	0	13	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	2238	0	0
T10	163954	0	0	0
T17	0	24	0	0
T18	0	4	0	0
T23	0	20	0	0
T27	170033	6	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	10	0	0
T32	0	18	0	0
T39	0	21	0	0
T44	0	13	0	0
T49	51022	0	0	0
T50	52392	0	0	0
T51	69697	0	0	0
T52	68303	0	0	0
T272	0	25	0	0
T273	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3202	0	0
T3	139915	47	0	0
T7	257391	69	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	70	0	0
T12	0	70	0	0
T17	0	172	0	0
T18	0	30	0	0
T23	0	23	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	17	0	0
T44	0	20	0	0
T55	0	41	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3451	0	0
T3	139915	64	0	0
T7	257391	80	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	67	0	0
T12	0	78	0	0
T17	0	173	0	0
T18	0	30	0	0
T23	0	11	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	29	0	0
T44	0	18	0	0
T55	0	60	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3376	0	0
T3	139915	55	0	0
T7	257391	120	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	79	0	0
T12	0	85	0	0
T17	0	171	0	0
T18	0	27	0	0
T23	0	18	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	19	0	0
T44	0	17	0	0
T55	0	55	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3297	0	0
T3	139915	16	0	0
T7	257391	81	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	81	0	0
T12	0	73	0	0
T17	0	135	0	0
T18	0	21	0	0
T23	0	14	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	7	0	0
T44	0	19	0	0
T55	0	23	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3918	0	0
T3	139915	19	0	0
T7	257391	64	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	71	0	0
T12	0	65	0	0
T17	0	174	0	0
T18	0	39	0	0
T23	0	23	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	5	0	0
T44	0	9	0	0
T55	0	33	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3953	0	0
T3	139915	66	0	0
T7	257391	60	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	61	0	0
T12	0	67	0	0
T17	0	160	0	0
T18	0	30	0	0
T23	0	17	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	11	0	0
T44	0	12	0	0
T55	0	21	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3819	0	0
T3	139915	71	0	0
T7	257391	55	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	71	0	0
T12	0	71	0	0
T17	0	166	0	0
T18	0	24	0	0
T23	0	11	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	15	0	0
T44	0	18	0	0
T55	0	39	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3902	0	0
T3	139915	32	0	0
T7	257391	65	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	64	0	0
T12	0	66	0	0
T17	0	149	0	0
T18	0	25	0	0
T23	0	22	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	17	0	0
T44	0	30	0	0
T55	0	42	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1028	0	0
T17	160791	15	0	0
T18	505676	36	0	0
T23	0	26	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T39	0	6	0	0
T43	342783	0	0	0
T44	639751	16	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	4	0	0
T272	0	14	0	0
T274	0	38	0	0
T275	0	16	0	0
T276	0	17	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1028	0	0
T17	160791	13	0	0
T18	505676	31	0	0
T23	0	21	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T39	0	4	0	0
T43	342783	0	0	0
T44	639751	6	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	14	0	0
T272	0	17	0	0
T274	0	26	0	0
T275	0	10	0	0
T276	0	23	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1050	0	0
T17	160791	19	0	0
T18	505676	22	0	0
T23	0	21	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T39	0	9	0	0
T43	342783	0	0	0
T44	639751	33	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	12	0	0
T272	0	17	0	0
T274	0	13	0	0
T275	0	39	0	0
T276	0	11	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	937	0	0
T17	160791	11	0	0
T18	505676	33	0	0
T23	0	13	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T43	342783	0	0	0
T44	639751	15	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	6	0	0
T166	0	26	0	0
T272	0	18	0	0
T274	0	27	0	0
T275	0	7	0	0
T276	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3995	0	0
T3	139915	37	0	0
T7	257391	77	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	64	0	0
T12	0	74	0	0
T17	0	174	0	0
T18	0	18	0	0
T23	0	14	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T44	0	15	0	0
T55	0	29	0	0
T75	0	42	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4263	0	0
T3	139915	54	0	0
T7	257391	66	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	72	0	0
T12	0	60	0	0
T17	0	164	0	0
T18	0	32	0	0
T23	0	13	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	18	0	0
T44	0	10	0	0
T55	0	43	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4107	0	0
T3	139915	60	0	0
T7	257391	61	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	75	0	0
T12	0	59	0	0
T17	0	169	0	0
T18	0	24	0	0
T23	0	14	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	3	0	0
T44	0	25	0	0
T55	0	29	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3961	0	0
T3	139915	58	0	0
T7	257391	70	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	45	0	0
T12	0	61	0	0
T17	0	164	0	0
T18	0	24	0	0
T23	0	8	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	21	0	0
T44	0	19	0	0
T55	0	35	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4000	0	0
T3	139915	12	0	0
T7	257391	62	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	68	0	0
T12	0	58	0	0
T17	0	156	0	0
T18	0	33	0	0
T23	0	20	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	15	0	0
T44	0	20	0	0
T55	0	31	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4147	0	0
T3	139915	68	0	0
T7	257391	77	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	71	0	0
T12	0	60	0	0
T17	0	142	0	0
T18	0	27	0	0
T23	0	23	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	6	0	0
T44	0	29	0	0
T55	0	48	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4285	0	0
T3	139915	73	0	0
T7	257391	92	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	64	0	0
T12	0	77	0	0
T17	0	170	0	0
T18	0	42	0	0
T23	0	23	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	8	0	0
T44	0	15	0	0
T55	0	34	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4347	0	0
T3	139915	24	0	0
T7	257391	71	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	81	0	0
T12	0	58	0	0
T17	0	162	0	0
T18	0	52	0	0
T23	0	17	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	7	0	0
T44	0	19	0	0
T55	0	33	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1961	0	0
T3	139915	12	0	0
T7	257391	22	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T10	0	17	0	0
T12	0	66	0	0
T17	0	56	0	0
T18	0	53	0	0
T23	0	15	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T44	0	20	0	0
T59	0	2	0	0
T69	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1489	0	0
T17	160791	69	0	0
T18	505676	21	0	0
T23	0	9	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T39	0	4	0	0
T43	342783	0	0	0
T44	639751	22	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	26	0	0
T190	0	28	0	0
T272	0	15	0	0
T274	0	16	0	0
T275	0	30	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4116	0	0
T1	78118	2	0	0
T2	80874	5	0	0
T3	139915	0	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	26	0	0
T18	0	27	0	0
T23	0	10	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T39	0	14	0	0
T44	0	25	0	0
T93	0	2	0	0
T94	0	6	0	0
T272	0	25	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1036	0	0
T17	160791	16	0	0
T18	505676	24	0	0
T23	0	18	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T39	0	6	0	0
T43	342783	0	0	0
T44	639751	26	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	5	0	0
T272	0	4	0	0
T274	0	25	0	0
T275	0	20	0	0
T276	0	13	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5278	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	332	0	0
T18	0	98	0	0
T23	0	81	0	0
T39	0	10	0	0
T44	0	19	0	0
T49	51022	0	0	0
T50	52392	0	0	0
T51	69697	68	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T59	748035	0	0	0
T69	146556	0	0	0
T70	149248	0	0	0
T137	0	52	0	0
T186	0	51	0	0
T190	0	80	0	0
T272	0	10	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5926	0	0
T7	257391	153	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	261	0	0
T18	0	28	0	0
T23	0	9	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	129	0	0
T44	0	21	0	0
T51	69697	0	0	0
T98	0	65	0	0
T122	0	97	0	0
T143	0	68	0	0
T226	0	38	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	4936	0	0
T7	257391	133	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	233	0	0
T18	0	29	0	0
T23	0	32	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	125	0	0
T44	0	32	0	0
T51	69697	0	0	0
T98	0	77	0	0
T122	0	67	0	0
T143	0	70	0	0
T226	0	39	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5124	0	0
T7	257391	149	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	254	0	0
T18	0	13	0	0
T23	0	9	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T39	0	156	0	0
T44	0	27	0	0
T51	69697	0	0	0
T98	0	64	0	0
T122	0	90	0	0
T143	0	65	0	0
T226	0	26	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1050	0	0
T17	160791	17	0	0
T18	505676	30	0	0
T23	0	7	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T39	0	1	0	0
T43	342783	0	0	0
T44	639751	18	0	0
T45	149384	0	0	0
T72	118520	0	0	0
T126	51503	0	0	0
T159	0	14	0	0
T272	0	14	0	0
T274	0	26	0	0
T275	0	4	0	0
T276	0	20	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1106	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	16	0	0
T18	0	20	0	0
T23	0	14	0	0
T39	0	6	0	0
T40	0	5	0	0
T41	0	13	0	0
T44	0	18	0	0
T49	51022	3	0	0
T50	52392	0	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T58	0	6	0	0
T59	748035	0	0	0
T62	202895	0	0	0
T69	146556	0	0	0
T70	149248	0	0	0
T164	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1080	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	10	0	0
T18	0	49	0	0
T23	0	33	0	0
T39	0	14	0	0
T40	0	13	0	0
T41	0	9	0	0
T44	0	12	0	0
T49	51022	8	0	0
T50	52392	0	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T59	748035	0	0	0
T62	202895	0	0	0
T69	146556	0	0	0
T70	149248	0	0	0
T164	0	1	0	0
T272	0	24	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1182	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	26	0	0
T18	0	27	0	0
T23	0	30	0	0
T39	0	5	0	0
T40	0	8	0	0
T41	0	4	0	0
T44	0	26	0	0
T49	51022	7	0	0
T50	52392	0	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T58	0	2	0	0
T59	748035	0	0	0
T62	202895	0	0	0
T69	146556	0	0	0
T70	149248	0	0	0
T164	0	5	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1058	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	20	0	0
T18	0	35	0	0
T23	0	27	0	0
T39	0	10	0	0
T40	0	9	0	0
T41	0	8	0	0
T44	0	12	0	0
T49	51022	8	0	0
T50	52392	0	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T58	0	1	0	0
T59	748035	0	0	0
T62	202895	0	0	0
T69	146556	0	0	0
T70	149248	0	0	0
T164	0	2	0	0