Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T24,T25
1	0	Covered	T5,T24,T25
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T24,T25
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T24,T25

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	234987	0	0
SrcPulseCheck_M	2147483647	237314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	234987
T1	315862	0
T2	2045640	0
T3	4184701	27
T4	742706	14
T5	927148	0
T6	1591630	0
T7	7013898	21
T8	7923251	27
T9	1359494	2
T10	163954	15
T12	0	51
T17	0	9
T24	5739067	3
T25	9174371	0
T26	4854221	0
T27	3586269	16
T28	1461	14
T29	447	0
T30	5067	3
T31	735	14
T32	0	14
T35	0	14
T36	0	16
T43	0	12
T49	51022	0
T50	52392	0
T51	69697	0
T53	0	29
T59	0	3
T62	0	16
T63	0	14

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	237314
T1	393302	0
T2	2125599	0
T3	4413655	27
T4	742706	14
T5	927148	0
T6	1654265	0
T7	7485782	21
T8	8460025	27
T9	1475674	2
T10	13663	15
T12	0	51
T17	0	9
T24	5949929	3
T25	9055222	0
T26	5274499	0
T27	3755594	16
T28	730777	14
T29	55977	0
T30	119089	3
T31	191153	14
T32	0	14
T35	0	14
T36	0	16
T43	0	12
T49	1311	0
T50	840	0
T51	497	0
T53	0	29
T59	0	3
T62	0	16
T63	0	14

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T24,T25,T3
1	1	Covered	T46,T48,T77

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T46,T48,T77
1	1	Covered	T24,T25,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1979	0	0
SrcPulseCheck_M	1193245780	2041	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1979
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T24	9167	1
T25	238296	1
T26	438	0
T27	708	0
T30	0	1
T53	0	10
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	2041
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T24	220029	1
T25	119147	1
T26	210577	0
T27	170033	0
T30	0	1
T53	0	10
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T24,T25,T3
1	1	Covered	T46,T48,T77

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T46,T48,T77
1	1	Covered	T24,T25,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	2034	0	0
SrcPulseCheck_M	7166523	2034	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	2034
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T24	220029	1
T25	119147	1
T26	210577	0
T27	170033	0
T30	0	1
T53	0	10
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	2034
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T24	9167	1
T25	238296	1
T26	438	0
T27	708	0
T30	0	1
T53	0	10
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1096	0	0
SrcPulseCheck_M	1193245780	1157	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1096
T1	678	0
T2	915	0
T3	25438	0
T5	254446	2
T6	505	0
T7	21449	0
T8	23338	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	9167	0
T25	238296	0
T26	438	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1157
T1	78118	0
T2	80874	0
T3	139915	0
T5	209128	2
T6	63140	0
T7	257391	0
T8	291725	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	220029	0
T25	119147	0
T26	210577	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1150	0	0
SrcPulseCheck_M	7166523	1150	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1150
T1	78118	0
T2	80874	0
T3	139915	0
T5	209128	2
T6	63140	0
T7	257391	0
T8	291725	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	220029	0
T25	119147	0
T26	210577	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1150
T1	678	0
T2	915	0
T3	25438	0
T5	254446	2
T6	505	0
T7	21449	0
T8	23338	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	9167	0
T25	238296	0
T26	438	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1103	0	0
SrcPulseCheck_M	1193245780	1167	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1103
T1	678	0
T2	915	0
T3	25438	0
T5	254446	2
T6	505	0
T7	21449	0
T8	23338	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	9167	0
T25	238296	0
T26	438	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1167
T1	78118	0
T2	80874	0
T3	139915	0
T5	209128	2
T6	63140	0
T7	257391	0
T8	291725	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	220029	0
T25	119147	0
T26	210577	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1161	0	0
SrcPulseCheck_M	7166523	1161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1161
T1	78118	0
T2	80874	0
T3	139915	0
T5	209128	2
T6	63140	0
T7	257391	0
T8	291725	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	220029	0
T25	119147	0
T26	210577	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1161
T1	678	0
T2	915	0
T3	25438	0
T5	254446	2
T6	505	0
T7	21449	0
T8	23338	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	9167	0
T25	238296	0
T26	438	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1101	0	0
SrcPulseCheck_M	1193245780	1164	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1101
T1	678	0
T2	915	0
T3	25438	0
T5	254446	2
T6	505	0
T7	21449	0
T8	23338	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	9167	0
T25	238296	0
T26	438	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1164
T1	78118	0
T2	80874	0
T3	139915	0
T5	209128	2
T6	63140	0
T7	257391	0
T8	291725	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	220029	0
T25	119147	0
T26	210577	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T5,T49,T50
1	0	Covered	T5,T49,T16
1	1	Covered	T5,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1154	0	0
SrcPulseCheck_M	7166523	1154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1154
T1	78118	0
T2	80874	0
T3	139915	0
T5	209128	2
T6	63140	0
T7	257391	0
T8	291725	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	220029	0
T25	119147	0
T26	210577	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1154
T1	678	0
T2	915	0
T3	25438	0
T5	254446	2
T6	505	0
T7	21449	0
T8	23338	0
T16	0	3
T17	0	2
T18	0	1
T23	0	1
T24	9167	0
T25	238296	0
T26	438	0
T36	0	1
T49	0	2
T50	0	1
T53	0	1
T64	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1110	0	0
SrcPulseCheck_M	1193245780	1172	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1110
T16	1184	2
T17	53846	2
T18	11510	0
T23	0	2
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	2
T37	0	2
T38	0	2
T39	0	2
T40	0	2
T41	0	6
T42	0	4
T43	714	0
T44	1292	0
T45	452	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1172
T16	117292	2
T17	160791	2
T18	505676	0
T23	0	2
T32	331440	0
T33	201361	0
T34	394938	0
T35	233941	0
T36	0	2
T37	0	2
T38	0	2
T39	0	2
T40	0	2
T41	0	6
T42	0	4
T43	342783	0
T44	639751	0
T45	149384	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1165	0	0
SrcPulseCheck_M	7166523	1165	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1165
T16	117292	2
T17	160791	2
T18	505676	0
T23	0	2
T32	331440	0
T33	201361	0
T34	394938	0
T35	233941	0
T36	0	2
T37	0	2
T38	0	2
T39	0	2
T40	0	2
T41	0	6
T42	0	4
T43	342783	0
T44	639751	0
T45	149384	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1165
T16	1184	2
T17	53846	2
T18	11510	0
T23	0	2
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	2
T37	0	2
T38	0	2
T39	0	2
T40	0	2
T41	0	6
T42	0	4
T43	714	0
T44	1292	0
T45	452	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T16,T17,T23
1	1	Covered	T41,T304,T305

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T41,T304,T305
1	1	Covered	T16,T17,T23

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	535	0	0
SrcPulseCheck_M	1193245780	598	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	535
T16	1184	1
T17	53846	1
T18	11510	0
T23	0	1
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	3
T42	0	2
T43	714	0
T44	1292	0
T45	452	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	598
T16	117292	1
T17	160791	1
T18	505676	0
T23	0	1
T32	331440	0
T33	201361	0
T34	394938	0
T35	233941	0
T36	0	1
T37	0	1
T38	0	1
T39	0	1
T40	0	1
T41	0	3
T42	0	2
T43	342783	0
T44	639751	0
T45	149384	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8
1	1	Covered	T41,T306,T304

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T8
1	0	Covered	T41,T306,T304
1	1	Covered	T3,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1007	0	0
SrcPulseCheck_M	1193245780	1086	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1007
T3	25438	8
T7	21449	3
T8	23338	8
T9	488	1
T10	0	4
T12	0	6
T16	0	1
T17	0	8
T19	0	4
T21	0	4
T26	438	0
T27	708	0
T28	1461	0
T29	447	0
T30	5067	0
T31	735	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1086
T3	139915	8
T7	257391	3
T8	291725	8
T9	58578	1
T10	0	4
T12	0	6
T16	0	1
T17	0	8
T19	0	4
T21	0	4
T26	210577	0
T27	170033	0
T28	730777	0
T29	55977	0
T30	119089	0
T31	191153	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T51,T17,T18
1	0	Covered	T51,T17,T18
1	1	Covered	T51,T17,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T51,T17,T18
1	0	Covered	T51,T17,T18
1	1	Covered	T51,T17,T18

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	3106	0	0
SrcPulseCheck_M	1193245780	3163	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	3106
T10	13663	0
T11	544	0
T17	0	100
T18	0	20
T20	0	20
T23	0	20
T36	0	40
T49	1311	0
T50	840	0
T51	497	20
T52	505	0
T53	28002	0
T54	0	20
T59	15265	0
T66	0	20
T67	0	20
T68	0	20
T69	585	0
T70	420	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	3163
T10	163954	0
T11	130858	0
T17	0	100
T18	0	20
T20	0	20
T23	0	20
T36	0	40
T49	51022	0
T50	52392	0
T51	69697	20
T52	68303	0
T53	692564	0
T54	0	20
T59	748035	0
T66	0	20
T67	0	20
T68	0	20
T69	146556	0
T70	149248	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T51,T17,T18
1	0	Covered	T51,T17,T18
1	1	Covered	T51,T17,T18

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T51,T17,T18
1	0	Covered	T51,T17,T18
1	1	Covered	T51,T17,T18

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	3159	0	0
SrcPulseCheck_M	7166523	3159	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	3159
T10	163954	0
T11	130858	0
T17	0	100
T18	0	20
T20	0	20
T23	0	20
T36	0	40
T49	51022	0
T50	52392	0
T51	69697	20
T52	68303	0
T53	692564	0
T54	0	20
T59	748035	0
T66	0	20
T67	0	20
T68	0	20
T69	146556	0
T70	149248	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	3159
T10	13663	0
T11	544	0
T17	0	100
T18	0	20
T20	0	20
T23	0	20
T36	0	40
T49	1311	0
T50	840	0
T51	497	20
T52	505	0
T53	28002	0
T54	0	20
T59	15265	0
T66	0	20
T67	0	20
T68	0	20
T69	585	0
T70	420	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T51,T52
1	0	Covered	T7,T51,T52
1	1	Covered	T7,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T51,T52
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T51,T52

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	6564	0	0
SrcPulseCheck_M	1193245780	6633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	6564
T7	21449	80
T8	23338	0
T9	488	0
T17	0	165
T18	0	41
T20	0	21
T26	438	0
T27	708	0
T28	1461	0
T29	447	0
T30	5067	0
T31	735	0
T51	497	1
T52	0	20
T53	0	20
T71	0	20
T72	0	20
T73	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	6633
T7	257391	80
T8	291725	0
T9	58578	0
T17	0	165
T18	0	41
T20	0	21
T26	210577	0
T27	170033	0
T28	730777	0
T29	55977	0
T30	119089	0
T31	191153	0
T51	69697	1
T52	0	20
T53	0	20
T71	0	20
T72	0	20
T73	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T51,T52
1	0	Covered	T7,T51,T52
1	1	Covered	T7,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T51,T52
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T51,T52

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	6622	0	0
SrcPulseCheck_M	7166523	6622	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	6622
T7	257391	80
T8	291725	0
T9	58578	0
T17	0	165
T18	0	41
T20	0	21
T26	210577	0
T27	170033	0
T28	730777	0
T29	55977	0
T30	119089	0
T31	191153	0
T51	69697	1
T52	0	20
T53	0	20
T71	0	20
T72	0	20
T73	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	6622
T7	21449	80
T8	23338	0
T9	488	0
T17	0	165
T18	0	41
T20	0	21
T26	438	0
T27	708	0
T28	1461	0
T29	447	0
T30	5067	0
T31	735	0
T51	497	1
T52	0	20
T53	0	20
T71	0	20
T72	0	20
T73	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T24,T25,T3
1	1	Covered	T7,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T7,T52,T53
1	1	Covered	T24,T25,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7598	0	0
SrcPulseCheck_M	1193245780	7667	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7598
T2	915	0
T3	25438	9
T6	505	0
T7	21449	87
T8	23338	9
T9	488	1
T10	0	5
T24	9167	1
T25	238296	1
T26	438	0
T27	708	0
T30	0	1
T51	0	1
T52	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7667
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	87
T8	291725	9
T9	58578	1
T10	0	5
T24	220029	1
T25	119147	1
T26	210577	0
T27	170033	0
T30	0	1
T51	0	1
T52	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T24,T25,T3
1	1	Covered	T7,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T25,T3
1	0	Covered	T7,T52,T53
1	1	Covered	T24,T25,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7659	0	0
SrcPulseCheck_M	7166523	7659	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7659
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	87
T8	291725	9
T9	58578	1
T10	0	5
T24	220029	1
T25	119147	1
T26	210577	0
T27	170033	0
T30	0	1
T51	0	1
T52	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7659
T2	915	0
T3	25438	9
T6	505	0
T7	21449	87
T8	23338	9
T9	488	1
T10	0	5
T24	9167	1
T25	238296	1
T26	438	0
T27	708	0
T30	0	1
T51	0	1
T52	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T52,T53
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T52,T53
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	6491	0	0
SrcPulseCheck_M	1193245780	6554	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	6491
T7	21449	80
T8	23338	0
T9	488	0
T17	0	160
T18	0	40
T20	0	20
T26	438	0
T27	708	0
T28	1461	0
T29	447	0
T30	5067	0
T31	735	0
T51	497	0
T52	0	20
T53	0	20
T64	0	80
T71	0	20
T72	0	20
T73	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	6554
T7	257391	80
T8	291725	0
T9	58578	0
T17	0	160
T18	0	40
T20	0	20
T26	210577	0
T27	170033	0
T28	730777	0
T29	55977	0
T30	119089	0
T31	191153	0
T51	69697	0
T52	0	20
T53	0	20
T64	0	80
T71	0	20
T72	0	20
T73	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T52,T53
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T7,T52,T53
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	6545	0	0
SrcPulseCheck_M	7166523	6545	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	6545
T7	257391	80
T8	291725	0
T9	58578	0
T17	0	160
T18	0	40
T20	0	20
T26	210577	0
T27	170033	0
T28	730777	0
T29	55977	0
T30	119089	0
T31	191153	0
T51	69697	0
T52	0	20
T53	0	20
T64	0	80
T71	0	20
T72	0	20
T73	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	6545
T7	21449	80
T8	23338	0
T9	488	0
T17	0	160
T18	0	40
T20	0	20
T26	438	0
T27	708	0
T28	1461	0
T29	447	0
T30	5067	0
T31	735	0
T51	497	0
T52	0	20
T53	0	20
T64	0	80
T71	0	20
T72	0	20
T73	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T6
1	0	Covered	T88,T89,T46
1	1	Covered	T1,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1115	0	0
SrcPulseCheck_M	1193245780	1179	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1115
T1	678	1
T2	915	1
T3	25438	0
T6	505	1
T7	21449	0
T8	23338	0
T9	488	0
T11	0	1
T13	0	1
T14	0	1
T15	0	1
T17	0	2
T18	0	1
T20	0	1
T24	9167	0
T25	238296	0
T26	438	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1179
T1	78118	1
T2	80874	1
T3	139915	0
T6	63140	1
T7	257391	0
T8	291725	0
T9	58578	0
T11	0	1
T13	0	1
T14	0	1
T15	0	1
T17	0	2
T18	0	1
T20	0	1
T24	220029	0
T25	119147	0
T26	210577	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T6
1	0	Covered	T88,T89,T46
1	1	Covered	T1,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1173	0	0
SrcPulseCheck_M	7166523	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1173
T1	78118	1
T2	80874	1
T3	139915	0
T6	63140	1
T7	257391	0
T8	291725	0
T9	58578	0
T11	0	1
T13	0	1
T14	0	1
T15	0	1
T17	0	2
T18	0	1
T20	0	1
T24	220029	0
T25	119147	0
T26	210577	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1173
T1	678	1
T2	915	1
T3	25438	0
T6	505	1
T7	21449	0
T8	23338	0
T9	488	0
T11	0	1
T13	0	1
T14	0	1
T15	0	1
T17	0	2
T18	0	1
T20	0	1
T24	9167	0
T25	238296	0
T26	438	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T24,T2
1	0	Covered	T1,T24,T2
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T24,T2
1	0	Covered	T88,T89,T46
1	1	Covered	T1,T24,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1944	0	0
SrcPulseCheck_M	1193245780	2003	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1944
T1	678	1
T2	915	1
T3	25438	9
T6	505	1
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T24	9167	1
T25	238296	0
T26	438	0
T30	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	2003
T1	78118	1
T2	80874	1
T3	139915	9
T6	63140	1
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T24	220029	1
T25	119147	0
T26	210577	0
T30	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T24,T2
1	0	Covered	T1,T24,T2
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T24,T2
1	0	Covered	T88,T89,T46
1	1	Covered	T1,T24,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1995	0	0
SrcPulseCheck_M	7166523	1995	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1995
T1	78118	1
T2	80874	1
T3	139915	9
T6	63140	1
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T24	220029	1
T25	119147	0
T26	210577	0
T30	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1995
T1	678	1
T2	915	1
T3	25438	9
T6	505	1
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T24	9167	1
T25	238296	0
T26	438	0
T30	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1406	0	0
SrcPulseCheck_M	1193245780	1468	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1406
T1	678	0
T2	915	0
T3	25438	0
T4	748	4
T5	254446	0
T6	505	0
T7	21449	0
T8	23338	0
T24	9167	0
T25	238296	0
T27	0	5
T28	0	4
T31	0	4
T32	0	4
T35	0	4
T36	0	5
T43	0	3
T62	0	5
T63	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1468
T1	78118	0
T2	80874	0
T3	139915	0
T4	370605	4
T5	209128	0
T6	63140	0
T7	257391	0
T8	291725	0
T24	220029	0
T25	119147	0
T27	0	5
T28	0	4
T31	0	4
T32	0	4
T35	0	4
T36	0	5
T43	0	3
T62	0	5
T63	0	4

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1460	0	0
SrcPulseCheck_M	7166523	1460	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1460
T1	78118	0
T2	80874	0
T3	139915	0
T4	370605	4
T5	209128	0
T6	63140	0
T7	257391	0
T8	291725	0
T24	220029	0
T25	119147	0
T27	0	5
T28	0	4
T31	0	4
T32	0	4
T35	0	4
T36	0	5
T43	0	3
T62	0	5
T63	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1460
T1	678	0
T2	915	0
T3	25438	0
T4	748	4
T5	254446	0
T6	505	0
T7	21449	0
T8	23338	0
T24	9167	0
T25	238296	0
T27	0	5
T28	0	4
T31	0	4
T32	0	4
T35	0	4
T36	0	5
T43	0	3
T62	0	5
T63	0	4

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1274	0	0
SrcPulseCheck_M	1193245780	1335	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1274
T1	678	0
T2	915	0
T3	25438	0
T4	748	3
T5	254446	0
T6	505	0
T7	21449	0
T8	23338	0
T24	9167	0
T25	238296	0
T27	0	3
T28	0	3
T31	0	3
T32	0	3
T35	0	3
T36	0	3
T43	0	3
T62	0	3
T63	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1335
T1	78118	0
T2	80874	0
T3	139915	0
T4	370605	3
T5	209128	0
T6	63140	0
T7	257391	0
T8	291725	0
T24	220029	0
T25	119147	0
T27	0	3
T28	0	3
T31	0	3
T32	0	3
T35	0	3
T36	0	3
T43	0	3
T62	0	3
T63	0	3

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1327	0	0
SrcPulseCheck_M	7166523	1327	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1327
T1	78118	0
T2	80874	0
T3	139915	0
T4	370605	3
T5	209128	0
T6	63140	0
T7	257391	0
T8	291725	0
T24	220029	0
T25	119147	0
T27	0	3
T28	0	3
T31	0	3
T32	0	3
T35	0	3
T36	0	3
T43	0	3
T62	0	3
T63	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1327
T1	678	0
T2	915	0
T3	25438	0
T4	748	3
T5	254446	0
T6	505	0
T7	21449	0
T8	23338	0
T24	9167	0
T25	238296	0
T27	0	3
T28	0	3
T31	0	3
T32	0	3
T35	0	3
T36	0	3
T43	0	3
T62	0	3
T63	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7176	0	0
SrcPulseCheck_M	1193245780	7245	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7176
T2	915	0
T3	25438	64
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	70
T59	0	51
T60	0	65
T61	0	80
T74	0	51
T75	0	75
T76	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7245
T2	80874	0
T3	139915	64
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	70
T59	0	51
T60	0	65
T61	0	80
T74	0	51
T75	0	75
T76	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7237	0	0
SrcPulseCheck_M	7166523	7237	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7237
T2	80874	0
T3	139915	64
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	70
T59	0	51
T60	0	65
T61	0	80
T74	0	51
T75	0	75
T76	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7237
T2	915	0
T3	25438	64
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	70
T59	0	51
T60	0	65
T61	0	80
T74	0	51
T75	0	75
T76	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7251	0	0
SrcPulseCheck_M	1193245780	7312	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7251
T2	915	0
T3	25438	84
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	87
T59	0	51
T60	0	67
T61	0	89
T74	0	51
T75	0	75
T76	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7312
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	87
T59	0	51
T60	0	67
T61	0	89
T74	0	51
T75	0	75
T76	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7307	0	0
SrcPulseCheck_M	7166523	7307	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7307
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	87
T59	0	51
T60	0	67
T61	0	89
T74	0	51
T75	0	75
T76	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7307
T2	915	0
T3	25438	84
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	87
T59	0	51
T60	0	67
T61	0	89
T74	0	51
T75	0	75
T76	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7111	0	0
SrcPulseCheck_M	1193245780	7175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7111
T2	915	0
T3	25438	84
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	65
T59	0	51
T60	0	74
T61	0	76
T74	0	51
T75	0	75
T76	0	53

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7175
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	65
T59	0	51
T60	0	74
T61	0	76
T74	0	51
T75	0	75
T76	0	53

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7169	0	0
SrcPulseCheck_M	7166523	7169	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7169
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	65
T59	0	51
T60	0	74
T61	0	76
T74	0	51
T75	0	75
T76	0	53

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7169
T2	915	0
T3	25438	84
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	65
T59	0	51
T60	0	74
T61	0	76
T74	0	51
T75	0	75
T76	0	53

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7129	0	0
SrcPulseCheck_M	1193245780	7191	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7129
T2	915	0
T3	25438	80
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	73
T59	0	51
T60	0	52
T61	0	68
T74	0	51
T75	0	51
T76	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7191
T2	80874	0
T3	139915	80
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	73
T59	0	51
T60	0	52
T61	0	68
T74	0	51
T75	0	51
T76	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7185	0	0
SrcPulseCheck_M	7166523	7185	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7185
T2	80874	0
T3	139915	80
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T55	0	73
T59	0	51
T60	0	52
T61	0	68
T74	0	51
T75	0	51
T76	0	79

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7185
T2	915	0
T3	25438	80
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T55	0	73
T59	0	51
T60	0	52
T61	0	68
T74	0	51
T75	0	51
T76	0	79

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1283	0	0
SrcPulseCheck_M	1193245780	1343	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1283
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1343
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1336	0	0
SrcPulseCheck_M	7166523	1336	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1336
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1336
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1257	0	0
SrcPulseCheck_M	1193245780	1319	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1257
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1319
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1312	0	0
SrcPulseCheck_M	7166523	1312	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1312
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1312
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1304	0	0
SrcPulseCheck_M	1193245780	1361	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1304
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1361
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1355	0	0
SrcPulseCheck_M	7166523	1355	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1355
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1355
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1298	0	0
SrcPulseCheck_M	1193245780	1355	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1298
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1355
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T24,T3,T30
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T30
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T30

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1350	0	0
SrcPulseCheck_M	7166523	1350	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1350
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	0
T8	291725	0
T9	58578	0
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1350
T2	915	0
T3	25438	9
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T55	0	4
T59	0	1
T60	0	2
T61	0	4
T74	0	1
T75	0	1
T76	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7755	0	0
SrcPulseCheck_M	1193245780	7815	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7755
T2	915	0
T3	25438	64
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T12	0	17
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	10
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7815
T2	80874	0
T3	139915	64
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T12	0	17
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	10
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7809	0	0
SrcPulseCheck_M	7166523	7809	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7809
T2	80874	0
T3	139915	64
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T12	0	17
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	10
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7809
T2	915	0
T3	25438	64
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T12	0	17
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	10
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7760	0	0
SrcPulseCheck_M	1193245780	7824	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7760
T2	915	0
T3	25438	84
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	9
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7824
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	9
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7818	0	0
SrcPulseCheck_M	7166523	7818	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7818
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	9
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7818
T2	915	0
T3	25438	84
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	9
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7610	0	0
SrcPulseCheck_M	1193245780	7681	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7610
T2	915	0
T3	25438	84
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	9
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7681
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	9
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7673	0	0
SrcPulseCheck_M	7166523	7673	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7673
T2	80874	0
T3	139915	84
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	9
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7673
T2	915	0
T3	25438	84
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	9
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	7650	0	0
SrcPulseCheck_M	1193245780	7719	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	7650
T2	915	0
T3	25438	80
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	9
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	7719
T2	80874	0
T3	139915	80
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	9
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	7712	0	0
SrcPulseCheck_M	7166523	7712	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	7712
T2	80874	0
T3	139915	80
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	51
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	51
T53	0	9
T59	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	7712
T2	915	0
T3	25438	80
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	51
T25	238296	0
T26	438	0
T27	708	0
T30	0	51
T53	0	9
T59	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1869	0	0
SrcPulseCheck_M	1193245780	1930	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1869
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T12	0	17
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	10
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1930
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T12	0	17
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	10
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1924	0	0
SrcPulseCheck_M	7166523	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1924
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T12	0	17
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	10
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1924
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T12	0	17
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	10
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1753	0	0
SrcPulseCheck_M	1193245780	1814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1753
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1814
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1808	0	0
SrcPulseCheck_M	7166523	1808	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1808
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1808
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1823	0	0
SrcPulseCheck_M	1193245780	1882	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1823
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1882
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1875	0	0
SrcPulseCheck_M	7166523	1875	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1875
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1875
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1784	0	0
SrcPulseCheck_M	1193245780	1845	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1784
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1845
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1839	0	0
SrcPulseCheck_M	7166523	1839	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1839
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1839
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1873	0	0
SrcPulseCheck_M	1193245780	1936	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1873
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T12	0	17
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	10
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1936
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T12	0	17
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	10
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1929	0	0
SrcPulseCheck_M	7166523	1929	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1929
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	1
T10	0	5
T12	0	17
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	10
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1929
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	1
T10	0	5
T12	0	17
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	10
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1834	0	0
SrcPulseCheck_M	1193245780	1894	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1834
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1894
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1887	0	0
SrcPulseCheck_M	7166523	1887	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1887
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1887
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1785	0	0
SrcPulseCheck_M	1193245780	1845	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1785
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1845
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1838	0	0
SrcPulseCheck_M	7166523	1838	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1838
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1838
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	1793	0	0
SrcPulseCheck_M	1193245780	1856	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	1793
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	1856
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T88,T89,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T24,T3,T7
1	0	Covered	T88,T89,T46
1	1	Covered	T24,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1193245780	1850	0	0
SrcPulseCheck_M	7166523	1850	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1193245780	1850
T2	80874	0
T3	139915	9
T6	63140	0
T7	257391	7
T8	291725	9
T9	58578	0
T10	0	5
T12	0	17
T17	0	9
T24	220029	1
T25	119147	0
T26	210577	0
T27	170033	0
T30	0	1
T53	0	9
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7166523	1850
T2	915	0
T3	25438	9
T6	505	0
T7	21449	7
T8	23338	9
T9	488	0
T10	0	5
T12	0	17
T17	0	9
T24	9167	1
T25	238296	0
T26	438	0
T27	708	0
T30	0	1
T53	0	9
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8
1	1	Covered	T306,T233,T91

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T8
1	0	Covered	T306,T233,T91
1	1	Covered	T3,T7,T8

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	937	0	0
SrcPulseCheck_M	1193245780	995	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	937
T3	25438	8
T7	21449	3
T8	23338	8
T9	488	1
T10	0	4
T12	0	6
T17	0	7
T19	0	4
T21	0	4
T22	0	1
T26	438	0
T27	708	0
T28	1461	0
T29	447	0
T30	5067	0
T31	735	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	995
T3	139915	8
T7	257391	3
T8	291725	8
T9	58578	1
T10	0	4
T12	0	6
T17	0	7
T19	0	4
T21	0	4
T22	0	1
T26	210577	0
T27	170033	0
T28	730777	0
T29	55977	0
T30	119089	0
T31	191153	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T2,T15,T17

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T15,T17
1	1	Covered	T1,T2,T6

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7166523	706	0	0
SrcPulseCheck_M	1193245780	773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7166523	706
T1	678	1
T2	915	2
T3	25438	0
T6	505	1
T7	21449	0
T8	23338	0
T9	488	0
T11	0	1
T13	0	1
T14	0	1
T15	0	2
T17	0	2
T18	0	1
T20	0	1
T24	9167	0
T25	238296	0
T26	438	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1193245780	773
T1	78118	1
T2	80874	2
T3	139915	0
T6	63140	1
T7	257391	0
T8	291725	0
T9	58578	0
T11	0	1
T13	0	1
T14	0	1
T15	0	2
T17	0	2
T18	0	1
T20	0	1
T24	220029	0
T25	119147	0
T26	210577	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc