Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1932

1

T1

7

T2

24

T13

5

auto[1]

805

1

T1

1

T13

7

T4

10

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1975

1

T1

7

T2

17

T13

5

auto[1]

762

1

T1

1

T2

7

T13

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2060

1

T1

8

T2

16

T13

11

auto[1]

677

1

T2

8

T13

1

T5

16

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2056

1

T1

8

T2

18

T13

6

auto[1]

681

1

T2

6

T13

6

T4

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T1

7

T2

6

T13

12

auto[1]

243

1

T1

1

T2

18

T5

41

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445

1

T1

8

T2

19

T13

12

auto[1]

292

1

T2

5

T5

1

T8

13

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T1

7

T2

24

T13

12

auto[1]

306

1

T1

1

T5

9

T9

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2452

1

T1

7

T2

12

T13

12

auto[1]

285

1

T1

1

T2

12

T8

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2503

1

T1

8

T2

22

T13

12

auto[1]

234

1

T2

2

T5

1

T8

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1952

1

T1

6

T2

8

T13

11

auto[1]

785

1

T1

2

T2

16

T13

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	950	1			T13	6		T4	10		T34	8
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	67	1			T2	6		T5	2		T8	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	75	1			T115	4		T330	16		T339	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T91	4		T210	4		T115	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	67	1			T1	1		T8	5		T9	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	34	1			T2	5		T89	5		T340	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	29	1			T229	5		T341	7		T337	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	10	1			T2	2		T342	2		T338	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	92	1			T82	1		T228	5		T210	20
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	16	1			T1	1		T5	1		T327	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T228	4		T327	2		T343	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T91	2		T341	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	74	1			T344	1		T116	1		T345	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T9	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	103	1			T8	7		T9	6		T90	7
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	22	1			T330	7		T345	2		T346	7
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	42	1			T5	1		T8	4		T91	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T347	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T329	6		T348	1		T338	6
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	8	1			T2	5		T223	3		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	23	1			T341	1		T335	6		T346	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T349	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	7	1			T350	7		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	28	1			T223	3		T351	25		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

138

1

T4

8

T96

11

T90

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

107

1

T1

1

T2

5

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

137

1

T24

5

T30

1

T96

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

134

1

T13

5

T5

1

T8

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

54

1

T36

3

T340

5

T333

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T9

8

T34

4

T352

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T8

7

T58

3

T184

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

88

1

T8

5

T40

3

T97

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

67

1

T89

5

T149

5

T240

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T24

4

T239

4

T99

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T230

4

T116

1

T274

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

90

1

T30

1

T122

6

T210

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T30

1

T49

3

T229

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

29

1

T2

6

T34

4

T228

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T64

1

T233

2

T334

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

76

1

T5

1

T89

5

T228

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

81

1

T9

2

T58

2

T119

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

78

1

T2

5

T24

3

T183

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

61

1

T1

1

T99

4

T107

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

80

1

T119

6

T184

3

T91

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T4

2

T49

2

T36

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T122

2

T274

1

T240

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T40

2

T100

4

T223

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

71

1

T2

2

T5

1

T58

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T9

5

T40

3

T97

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T122

1

T340

2

T241

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T30

1

T353

1

T331

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

20

1

T122

2

T183

2

T91

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T354

1

T355

2

T356

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T40

2

T89

5

T85

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T13

1

T357

2

T356

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded