Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.52 98.77 96.78 100.00 95.51 98.23 99.52 93.86


Total tests in report: 910
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.86 60.86 79.29 79.29 68.50 68.50 91.89 91.89 20.51 20.51 79.59 79.59 69.46 69.46 16.79 16.79 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.184363354
84.79 23.92 95.61 16.33 89.69 21.18 96.46 4.57 66.03 45.51 95.30 15.71 91.33 21.87 59.10 42.30 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2162072970
88.05 3.26 96.70 1.08 90.75 1.06 96.46 0.00 76.92 10.90 96.38 1.07 93.74 2.41 65.39 6.30 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.451883038
90.01 1.96 97.01 0.32 91.03 0.28 96.46 0.00 79.49 2.56 96.52 0.15 97.40 3.66 72.17 6.78 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3946745671
91.38 1.37 97.07 0.06 93.45 2.43 96.46 0.00 79.49 0.00 96.60 0.07 97.98 0.58 78.63 6.46 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.662020406
92.29 0.90 97.37 0.30 93.55 0.10 96.46 0.00 84.62 5.13 96.89 0.30 98.36 0.39 78.74 0.11 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.376474971
92.89 0.60 97.37 0.00 93.58 0.03 96.46 0.00 84.62 0.00 96.89 0.00 98.55 0.19 82.72 3.98 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1212839671
93.35 0.46 97.41 0.04 93.60 0.03 96.46 0.00 85.90 1.28 96.97 0.07 98.55 0.00 84.55 1.83 /workspace/coverage/default/44.sysrst_ctrl_stress_all.2745708763
93.77 0.42 97.72 0.32 93.78 0.18 97.15 0.68 87.18 1.28 97.08 0.11 98.94 0.39 84.55 0.00 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.3615006254
94.16 0.39 97.82 0.09 93.81 0.03 97.15 0.00 89.10 1.92 97.19 0.11 99.04 0.10 85.04 0.48 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.349195803
94.46 0.30 97.87 0.06 93.81 0.00 97.15 0.00 91.03 1.92 97.30 0.11 99.04 0.00 85.04 0.00 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.3584035554
94.76 0.30 98.32 0.45 94.36 0.56 97.15 0.00 91.67 0.64 97.74 0.44 99.04 0.00 85.04 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2257668774
95.03 0.27 98.40 0.07 94.51 0.15 97.49 0.34 91.67 0.00 97.89 0.15 99.04 0.00 86.22 1.18 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1845610777
95.27 0.24 98.41 0.02 94.82 0.30 98.17 0.68 91.67 0.00 97.93 0.04 99.04 0.00 86.87 0.65 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2191948591
95.51 0.24 98.47 0.06 94.89 0.08 99.54 1.37 91.67 0.00 97.93 0.00 99.04 0.00 87.03 0.16 /workspace/coverage/default/14.sysrst_ctrl_alert_test.900183881
95.73 0.22 98.51 0.04 94.92 0.03 99.54 0.00 91.67 0.00 97.93 0.00 99.04 0.00 88.48 1.45 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2456335375
95.93 0.20 98.54 0.04 94.92 0.00 99.54 0.00 92.95 1.28 98.00 0.07 99.04 0.00 88.48 0.00 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2714801713
96.12 0.20 98.58 0.04 94.92 0.00 99.54 0.00 94.23 1.28 98.08 0.07 99.04 0.00 88.48 0.00 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3483766116
96.28 0.16 98.58 0.00 95.80 0.88 99.54 0.00 94.23 0.00 98.08 0.00 99.04 0.00 88.70 0.22 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3185016627
96.40 0.12 98.62 0.04 95.83 0.03 99.54 0.00 94.87 0.64 98.11 0.04 99.13 0.10 88.70 0.00 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1438252125
96.51 0.11 98.62 0.00 95.83 0.00 99.54 0.00 94.87 0.00 98.11 0.00 99.13 0.00 89.45 0.75 /workspace/coverage/default/5.sysrst_ctrl_stress_all.1198311968
96.61 0.10 98.64 0.02 95.83 0.00 99.54 0.00 95.51 0.64 98.15 0.04 99.13 0.00 89.45 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.87707469
96.71 0.10 98.64 0.00 95.85 0.03 100.00 0.46 95.51 0.00 98.15 0.00 99.23 0.10 89.56 0.11 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1171541562
96.79 0.08 98.69 0.06 95.85 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.23 0.00 90.10 0.54 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1226643736
96.85 0.06 98.69 0.00 95.85 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.23 0.00 90.53 0.43 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.41016246
96.91 0.05 98.69 0.00 95.85 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.23 0.00 90.90 0.38 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.109398361
96.96 0.05 98.71 0.02 95.88 0.03 100.00 0.00 95.51 0.00 98.15 0.00 99.23 0.00 91.23 0.32 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.4243973456
97.01 0.05 98.75 0.04 96.03 0.15 100.00 0.00 95.51 0.00 98.23 0.07 99.33 0.10 91.23 0.00 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2742463143
97.06 0.05 98.75 0.00 96.33 0.30 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 91.28 0.05 /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2120743165
97.11 0.05 98.75 0.00 96.33 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 91.60 0.32 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3492111572
97.15 0.04 98.75 0.00 96.33 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 91.87 0.27 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3711110313
97.18 0.04 98.75 0.00 96.33 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.14 0.27 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3164972248
97.21 0.02 98.75 0.00 96.33 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.30 0.16 /workspace/coverage/default/1.sysrst_ctrl_stress_all.542749608
97.23 0.02 98.75 0.00 96.39 0.05 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.41 0.11 /workspace/coverage/default/49.sysrst_ctrl_stress_all.1757095608
97.25 0.02 98.75 0.00 96.54 0.15 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.41 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3896362473
97.27 0.02 98.75 0.00 96.56 0.03 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.52 0.11 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.658702751
97.29 0.02 98.75 0.00 96.59 0.03 100.00 0.00 95.51 0.00 98.23 0.00 99.42 0.10 92.52 0.00 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.148970749
97.30 0.02 98.75 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.42 0.00 92.63 0.11 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.907688050
97.32 0.02 98.75 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.42 0.00 92.73 0.11 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2517576563
97.33 0.02 98.75 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.42 0.00 92.84 0.11 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3812168978
97.35 0.02 98.75 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.42 0.00 92.95 0.11 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1362848503
97.36 0.01 98.75 0.00 96.64 0.05 100.00 0.00 95.51 0.00 98.23 0.00 99.42 0.00 93.00 0.05 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4051781237
97.38 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.10 93.00 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.598781414
97.39 0.01 98.75 0.00 96.66 0.03 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.06 0.05 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1337465870
97.40 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.11 0.05 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3627239704
97.40 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.16 0.05 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1885418238
97.41 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.22 0.05 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3984694737
97.42 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.27 0.05 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.2198136382
97.43 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.33 0.05 /workspace/coverage/default/24.sysrst_ctrl_stress_all.3507932370
97.44 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.38 0.05 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1130741007
97.44 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.43 0.05 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.75679869
97.45 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.49 0.05 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.133023326
97.46 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.54 0.05 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.978730677
97.47 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.60 0.05 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.746291415
97.47 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.65 0.05 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1249391339
97.48 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.70 0.05 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.942644120
97.49 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.76 0.05 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1440177785
97.50 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.81 0.05 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.473286301
97.50 0.01 98.75 0.00 96.66 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.86 0.05 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4094410744
97.51 0.01 98.75 0.00 96.71 0.05 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.86 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2564331267
97.52 0.01 98.75 0.00 96.74 0.03 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.86 0.00 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.300272425
97.52 0.01 98.75 0.00 96.76 0.03 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.86 0.00 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.410603818
97.52 0.01 98.77 0.02 96.76 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.52 0.00 93.86 0.00 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1764892874

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2669036053
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3011353598
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2567305905
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3994900877
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.4171338546
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3940482327
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.669841442
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3735196632
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2434761611
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1470373323
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2316489709
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2792903139
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2979106097
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2343182876
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2512170495
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.340336084
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2730086013
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2297518277
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2555273037
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.872501142
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.34140563
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3960601832
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3789965063
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2456751889
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2781238741
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2493721490
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2616272557
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3948709521
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2267378376
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3957893540
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3674896838
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3423116068
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.701440739
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3312473763
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.798680036
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3305203148
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2181300939
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1294740664
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3559103436
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.858754662
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2177708667
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3507633913
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1777039173
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2936821005
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1374866040
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.565352196
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2567419851
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.458042365
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1819391587
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.168145227
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3446971993
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.290240745
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3678192292
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3268876405
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3802040205
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.232448682
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3847999213
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.80530080
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1735680805
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.150982416
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.296991630
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.35257329
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.4214595143
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1758158246
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2967295036
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4155032359
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4138399765
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.951550671
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3778887310
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3276223742
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2217755325
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1598772673
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1258794743
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.942211038
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.792526724
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1804819366
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1942608305
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2964898682
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3376645338
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2383951409
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1688818283
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1289856142
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.50884784
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1266573535
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1973986790
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3637734853
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2621736054
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2640497071
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1260992700
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2336788285
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3058622116
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3003717930
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4173773148
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/workspace/coverage/default/42.sysrst_ctrl_alert_test.4216615823
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2518546230
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.4033694135
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.833687293
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.640995941
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.11163155
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3202692555
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3874564403
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.480278207
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3537297009
/workspace/coverage/default/42.sysrst_ctrl_smoke.113710084
/workspace/coverage/default/42.sysrst_ctrl_stress_all.902348920
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3329523140
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3660487512
/workspace/coverage/default/43.sysrst_ctrl_alert_test.958058666
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3530254418
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2067875362
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3418481654
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.359421987
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3887731620
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2062416839
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2435239856
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1159370602
/workspace/coverage/default/43.sysrst_ctrl_smoke.663615208
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1938009733
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3925850472
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.867535334
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1084736067
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2913530706
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.4070359644
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.755382659
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3025156391
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.183943591
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3981191952
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3980258533
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1682527065
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1113236837
/workspace/coverage/default/44.sysrst_ctrl_smoke.4040248497
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1171021283
/workspace/coverage/default/45.sysrst_ctrl_alert_test.4129973451
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3176958266
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.4027968193
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2283017495
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3813448268
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3527306546
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.888002869
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3274204345
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.451015321
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1947205061
/workspace/coverage/default/45.sysrst_ctrl_smoke.1642910548
/workspace/coverage/default/45.sysrst_ctrl_stress_all.4051325220
/workspace/coverage/default/46.sysrst_ctrl_alert_test.621309544
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.904386215
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3305398941
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.610844682
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3887530586
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2994229487
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.4217650364
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3024259428
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1427168050
/workspace/coverage/default/46.sysrst_ctrl_smoke.1181795725
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3805873848
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.755811420
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1833619030
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2932595864
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3409167755
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3934773945
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2169691386
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1451971491
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3179186022
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2025114205
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2776741685
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4195868667
/workspace/coverage/default/47.sysrst_ctrl_smoke.4033358657
/workspace/coverage/default/47.sysrst_ctrl_stress_all.1482680743
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.797544043
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.497735652
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2834773460
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1019429817
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3880356996
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1332097204
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.422352839
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3869566016
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.869025529
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2071769110
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1771511638
/workspace/coverage/default/48.sysrst_ctrl_smoke.4028807761
/workspace/coverage/default/48.sysrst_ctrl_stress_all.4235405098
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2165165920
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2912274421
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1529986784
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.4238663114
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2073087823
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4123786591
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.617760448
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3970226236
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.405754462
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3382480665
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.266356935
/workspace/coverage/default/49.sysrst_ctrl_smoke.1372762886
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1650428447
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3735898142
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1836579341
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3577492322
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3235703983
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2183087431
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2015144293
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2457171563
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3972655129
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1931191587
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2711564318
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3427224246
/workspace/coverage/default/5.sysrst_ctrl_smoke.2824090860
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2018161695
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3325935219
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1521154452
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3809279312
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1238985985
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2123344810
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3554855811
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1545329924
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3238919080
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.609831260
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.382143586
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1577110373
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.711824555
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1037117092
/workspace/coverage/default/6.sysrst_ctrl_smoke.2070324766
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1509044574
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4029596214
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4236769586
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3890081437
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.580719646
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1579999623
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.721194684
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3611554821
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1014204079
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1530973875
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3329869616
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1347740140
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4116914248
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1077747756
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3814687896
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.986147825
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1381421024
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2304156878
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2312982333
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2235380064
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.409772211
/workspace/coverage/default/7.sysrst_ctrl_smoke.3759660464
/workspace/coverage/default/7.sysrst_ctrl_stress_all.213448590
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.289109792
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.254496421
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2643327302
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2723829940
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2869775946
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2679049325
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1069217119
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1176099730
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.420972311
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3014194811
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2826274746
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.474594473
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1994440048
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.544675686
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3005964475
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1249486380
/workspace/coverage/default/8.sysrst_ctrl_smoke.970702785
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3912199328
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3698696955
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.4289888794
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3505871567
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1970706093
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1256577819
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2814142599
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4229435894
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2494734514
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.319732541
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2999412504
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2204933344
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.132772241
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2648224546
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.233972260
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.243029746
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1186227569
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1687395783
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2440385077
/workspace/coverage/default/9.sysrst_ctrl_smoke.1174341774
/workspace/coverage/default/9.sysrst_ctrl_stress_all.958039719
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.895188642
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2568750344
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2360473573
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2061623308
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.496947595
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1349705868
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1911887415



Total test records in report: 910
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T6 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.901658368 Mar 12 02:50:32 PM PDT 24 Mar 12 02:50:35 PM PDT 24 2535241627 ps
T1 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4051781237 Mar 12 02:50:17 PM PDT 24 Mar 12 02:51:40 PM PDT 24 59200816011 ps
T2 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.184363354 Mar 12 02:51:35 PM PDT 24 Mar 12 02:55:04 PM PDT 24 77535897144 ps
T12 /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3382480665 Mar 12 02:51:28 PM PDT 24 Mar 12 02:51:30 PM PDT 24 2219200244 ps
T13 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1461009057 Mar 12 02:50:16 PM PDT 24 Mar 12 02:50:39 PM PDT 24 85462382953 ps
T14 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1874579375 Mar 12 02:50:15 PM PDT 24 Mar 12 02:50:18 PM PDT 24 2475780032 ps
T15 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.880876592 Mar 12 02:50:44 PM PDT 24 Mar 12 02:52:36 PM PDT 24 82334046457 ps
T16 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2169691386 Mar 12 02:51:18 PM PDT 24 Mar 12 02:51:25 PM PDT 24 2576911471 ps
T17 /workspace/coverage/default/40.sysrst_ctrl_smoke.2773857869 Mar 12 02:51:07 PM PDT 24 Mar 12 02:51:13 PM PDT 24 2109929114 ps
T18 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.132772241 Mar 12 02:49:27 PM PDT 24 Mar 12 02:49:36 PM PDT 24 3358189141 ps
T3 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.617760448 Mar 12 02:51:24 PM PDT 24 Mar 12 02:51:33 PM PDT 24 3125772843 ps
T4 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1845610777 Mar 12 02:50:41 PM PDT 24 Mar 12 02:55:51 PM PDT 24 114000855014 ps
T50 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.170951146 Mar 12 02:49:50 PM PDT 24 Mar 12 02:49:57 PM PDT 24 4000700527 ps
T51 /workspace/coverage/default/31.sysrst_ctrl_alert_test.2921964062 Mar 12 02:50:33 PM PDT 24 Mar 12 02:50:34 PM PDT 24 2115440656 ps
T52 /workspace/coverage/default/36.sysrst_ctrl_stress_all.3168104403 Mar 12 02:50:46 PM PDT 24 Mar 12 02:50:51 PM PDT 24 6084581432 ps
T53 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.208377590 Mar 12 02:49:40 PM PDT 24 Mar 12 02:49:45 PM PDT 24 3527019745 ps
T5 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.300272425 Mar 12 02:50:15 PM PDT 24 Mar 12 02:53:33 PM PDT 24 82905282142 ps
T54 /workspace/coverage/default/42.sysrst_ctrl_alert_test.4216615823 Mar 12 02:51:06 PM PDT 24 Mar 12 02:51:12 PM PDT 24 2013533326 ps
T7 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.3615006254 Mar 12 02:49:34 PM PDT 24 Mar 12 02:49:36 PM PDT 24 3251043626 ps
T55 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.425370384 Mar 12 02:49:57 PM PDT 24 Mar 12 02:50:04 PM PDT 24 2171229340 ps
T8 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2517576563 Mar 12 02:50:56 PM PDT 24 Mar 12 02:52:29 PM PDT 24 131429930770 ps
T9 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1226643736 Mar 12 02:51:30 PM PDT 24 Mar 12 02:56:11 PM PDT 24 103524637524 ps
T27 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3838933022 Mar 12 02:50:57 PM PDT 24 Mar 12 02:51:05 PM PDT 24 2461419381 ps
T10 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.6458765 Mar 12 02:50:17 PM PDT 24 Mar 12 02:50:19 PM PDT 24 4143295964 ps
T28 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1628005148 Mar 12 02:49:56 PM PDT 24 Mar 12 02:50:02 PM PDT 24 2508777696 ps
T150 /workspace/coverage/default/14.sysrst_ctrl_alert_test.900183881 Mar 12 02:49:43 PM PDT 24 Mar 12 02:49:44 PM PDT 24 2042913609 ps
T151 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1857932599 Mar 12 02:51:05 PM PDT 24 Mar 12 02:51:10 PM PDT 24 3198611690 ps
T152 /workspace/coverage/default/26.sysrst_ctrl_smoke.2213353296 Mar 12 02:50:20 PM PDT 24 Mar 12 02:50:27 PM PDT 24 2112358565 ps
T187 /workspace/coverage/default/13.sysrst_ctrl_smoke.764332236 Mar 12 02:49:49 PM PDT 24 Mar 12 02:49:53 PM PDT 24 2115022457 ps
T11 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2397548121 Mar 12 02:50:36 PM PDT 24 Mar 12 02:50:45 PM PDT 24 4449856571 ps
T34 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.3238919080 Mar 12 02:49:15 PM PDT 24 Mar 12 02:50:46 PM PDT 24 71868442718 ps
T29 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.266356935 Mar 12 02:51:21 PM PDT 24 Mar 12 02:51:28 PM PDT 24 2511648134 ps
T77 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1396771474 Mar 12 02:50:36 PM PDT 24 Mar 12 02:50:39 PM PDT 24 2634731517 ps
T24 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2162072970 Mar 12 02:50:07 PM PDT 24 Mar 12 02:51:06 PM PDT 24 1237984455949 ps
T65 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.351146449 Mar 12 02:50:22 PM PDT 24 Mar 12 02:50:24 PM PDT 24 2246114655 ps
T66 /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3805189898 Mar 12 02:49:02 PM PDT 24 Mar 12 02:49:10 PM PDT 24 2612183897 ps
T67 /workspace/coverage/default/30.sysrst_ctrl_stress_all.426093242 Mar 12 02:50:33 PM PDT 24 Mar 12 02:50:43 PM PDT 24 6545981334 ps
T58 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2702801332 Mar 12 02:49:48 PM PDT 24 Mar 12 02:52:56 PM PDT 24 80627218974 ps
T68 /workspace/coverage/default/28.sysrst_ctrl_alert_test.533648906 Mar 12 02:50:24 PM PDT 24 Mar 12 02:50:26 PM PDT 24 2069056338 ps
T69 /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1577110373 Mar 12 02:49:14 PM PDT 24 Mar 12 02:49:15 PM PDT 24 2474670711 ps
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T40 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3946745671 Mar 12 02:50:54 PM PDT 24 Mar 12 02:52:44 PM PDT 24 170191363501 ps
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T48 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.4075131277 Mar 12 02:50:41 PM PDT 24 Mar 12 02:50:44 PM PDT 24 3624760244 ps
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T285 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2973206386 Mar 12 02:50:50 PM PDT 24 Mar 12 02:50:57 PM PDT 24 2511590523 ps
T120 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2018161695 Mar 12 02:49:06 PM PDT 24 Mar 12 02:50:24 PM PDT 24 33565328466 ps
T376 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.151685958 Mar 12 02:50:46 PM PDT 24 Mar 12 02:50:48 PM PDT 24 2660229801 ps
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T121 /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.904386215 Mar 12 02:51:17 PM PDT 24 Mar 12 02:51:22 PM PDT 24 3410617534 ps
T378 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.177417221 Mar 12 02:50:24 PM PDT 24 Mar 12 02:50:29 PM PDT 24 3048370343 ps
T89 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1337465870 Mar 12 02:51:39 PM PDT 24 Mar 12 02:52:24 PM PDT 24 66434218744 ps
T379 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2075976923 Mar 12 02:50:53 PM PDT 24 Mar 12 02:51:00 PM PDT 24 2201311205 ps
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T381 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2644614542 Mar 12 02:49:51 PM PDT 24 Mar 12 02:49:53 PM PDT 24 3794723249 ps
T382 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3307516234 Mar 12 02:50:34 PM PDT 24 Mar 12 02:50:40 PM PDT 24 2206736365 ps
T61 /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2870212761 Mar 12 02:51:02 PM PDT 24 Mar 12 02:51:08 PM PDT 24 6738304554 ps
T137 /workspace/coverage/default/44.sysrst_ctrl_alert_test.1084736067 Mar 12 02:51:12 PM PDT 24 Mar 12 02:51:15 PM PDT 24 2028750331 ps
T90 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1349705868 Mar 12 02:51:43 PM PDT 24 Mar 12 02:53:03 PM PDT 24 116464665025 ps
T138 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3621100648 Mar 12 02:49:56 PM PDT 24 Mar 12 02:50:04 PM PDT 24 2512846559 ps
T139 /workspace/coverage/default/20.sysrst_ctrl_stress_all.3343662580 Mar 12 02:50:04 PM PDT 24 Mar 12 02:50:33 PM PDT 24 11476095862 ps
T140 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1742155351 Mar 12 02:51:04 PM PDT 24 Mar 12 02:51:05 PM PDT 24 3963447038 ps
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T76 /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1284097810 Mar 12 02:50:02 PM PDT 24 Mar 12 02:50:07 PM PDT 24 2481865407 ps
T62 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.123947550 Mar 12 02:49:57 PM PDT 24 Mar 12 02:50:05 PM PDT 24 5002617354 ps
T383 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2884221667 Mar 12 02:48:56 PM PDT 24 Mar 12 02:48:58 PM PDT 24 2631391542 ps
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T88 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1484505661 Mar 12 02:50:08 PM PDT 24 Mar 12 02:50:10 PM PDT 24 3213905117 ps
T384 /workspace/coverage/default/17.sysrst_ctrl_smoke.568738796 Mar 12 02:49:49 PM PDT 24 Mar 12 02:49:55 PM PDT 24 2116957977 ps
T227 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2588379907 Mar 12 02:48:42 PM PDT 24 Mar 12 02:48:44 PM PDT 24 2333096966 ps
T162 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3887530586 Mar 12 02:51:18 PM PDT 24 Mar 12 02:51:20 PM PDT 24 2497099230 ps
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T275 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1445588377 Mar 12 02:50:03 PM PDT 24 Mar 12 02:50:07 PM PDT 24 3546452254 ps
T386 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1689260607 Mar 12 02:50:42 PM PDT 24 Mar 12 02:50:50 PM PDT 24 2610301055 ps
T246 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1164029201 Mar 12 02:49:04 PM PDT 24 Mar 12 02:49:33 PM PDT 24 42085455072 ps
T270 /workspace/coverage/default/30.sysrst_ctrl_alert_test.3105771705 Mar 12 02:50:32 PM PDT 24 Mar 12 02:50:34 PM PDT 24 2033800091 ps
T97 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1271953135 Mar 12 02:50:41 PM PDT 24 Mar 12 02:52:18 PM PDT 24 161197691427 ps
T271 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1994440048 Mar 12 02:49:30 PM PDT 24 Mar 12 02:49:32 PM PDT 24 2635348738 ps
T272 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.644753305 Mar 12 02:50:39 PM PDT 24 Mar 12 02:50:45 PM PDT 24 2142380697 ps
T273 /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3223785852 Mar 12 02:49:49 PM PDT 24 Mar 12 02:49:59 PM PDT 24 3452306392 ps
T91 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.658702751 Mar 12 02:51:38 PM PDT 24 Mar 12 02:52:15 PM PDT 24 78414780850 ps
T228 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2456335375 Mar 12 02:51:30 PM PDT 24 Mar 12 02:53:38 PM PDT 24 101887659479 ps
T63 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2261546919 Mar 12 02:49:56 PM PDT 24 Mar 12 02:50:02 PM PDT 24 4693340905 ps
T229 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.4243973456 Mar 12 02:50:08 PM PDT 24 Mar 12 02:50:35 PM PDT 24 91021444991 ps
T35 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.881406446 Mar 12 02:50:44 PM PDT 24 Mar 12 02:50:47 PM PDT 24 3612095936 ps
T36 /workspace/coverage/default/44.sysrst_ctrl_stress_all.2745708763 Mar 12 02:51:08 PM PDT 24 Mar 12 02:57:37 PM PDT 24 605192424382 ps
T37 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.3155779693 Mar 12 02:48:40 PM PDT 24 Mar 12 02:48:45 PM PDT 24 3130091396 ps
T98 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1238985985 Mar 12 02:51:37 PM PDT 24 Mar 12 02:52:44 PM PDT 24 24334496662 ps
T214 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1919441383 Mar 12 02:51:07 PM PDT 24 Mar 12 02:51:13 PM PDT 24 3739823007 ps
T215 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3283789309 Mar 12 02:48:56 PM PDT 24 Mar 12 02:48:59 PM PDT 24 2521581681 ps
T216 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3417266704 Mar 12 02:50:57 PM PDT 24 Mar 12 02:51:06 PM PDT 24 3361224768 ps
T217 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3333562282 Mar 12 02:48:45 PM PDT 24 Mar 12 02:48:46 PM PDT 24 2517553511 ps
T218 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2025114205 Mar 12 02:51:19 PM PDT 24 Mar 12 02:51:23 PM PDT 24 2452003700 ps
T219 /workspace/coverage/default/18.sysrst_ctrl_smoke.2332036039 Mar 12 02:50:00 PM PDT 24 Mar 12 02:50:06 PM PDT 24 2109975485 ps
T64 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.451883038 Mar 12 02:49:43 PM PDT 24 Mar 12 02:50:29 PM PDT 24 865746403704 ps
T202 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.968654740 Mar 12 02:49:43 PM PDT 24 Mar 12 02:49:48 PM PDT 24 3572855623 ps
T203 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3713304699 Mar 12 02:48:44 PM PDT 24 Mar 12 02:48:52 PM PDT 24 2402627267 ps
T204 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.4077805633 Mar 12 02:49:48 PM PDT 24 Mar 12 02:50:02 PM PDT 24 4232460001 ps
T205 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4195868667 Mar 12 02:51:18 PM PDT 24 Mar 12 02:51:25 PM PDT 24 2512232359 ps
T206 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1421094729 Mar 12 02:50:10 PM PDT 24 Mar 12 02:50:17 PM PDT 24 2515544145 ps
T207 /workspace/coverage/default/24.sysrst_ctrl_smoke.2800846126 Mar 12 02:50:12 PM PDT 24 Mar 12 02:50:14 PM PDT 24 2123758678 ps
T208 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3689837987 Mar 12 02:50:17 PM PDT 24 Mar 12 02:50:19 PM PDT 24 2535984444 ps
T209 /workspace/coverage/default/43.sysrst_ctrl_smoke.663615208 Mar 12 02:51:03 PM PDT 24 Mar 12 02:51:06 PM PDT 24 2127962528 ps
T210 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3329869616 Mar 12 02:51:32 PM PDT 24 Mar 12 02:57:19 PM PDT 24 137406017167 ps
T387 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1429012262 Mar 12 02:50:54 PM PDT 24 Mar 12 02:51:00 PM PDT 24 2101176666 ps
T84 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.463425953 Mar 12 02:50:15 PM PDT 24 Mar 12 02:52:08 PM PDT 24 48769731692 ps
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T85 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3711110313 Mar 12 02:50:25 PM PDT 24 Mar 12 02:51:02 PM PDT 24 57345184250 ps
T388 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1257800639 Mar 12 02:49:53 PM PDT 24 Mar 12 02:50:00 PM PDT 24 2460309248 ps
T170 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.183943591 Mar 12 02:51:13 PM PDT 24 Mar 12 02:51:16 PM PDT 24 3559911209 ps
T99 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.2979381508 Mar 12 02:50:19 PM PDT 24 Mar 12 02:50:56 PM PDT 24 66858090583 ps
T389 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1921932044 Mar 12 02:50:14 PM PDT 24 Mar 12 02:50:16 PM PDT 24 2214240375 ps
T340 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2266693926 Mar 12 02:49:50 PM PDT 24 Mar 12 02:52:07 PM PDT 24 100001853988 ps
T390 /workspace/coverage/default/3.sysrst_ctrl_stress_all.2669167629 Mar 12 02:48:58 PM PDT 24 Mar 12 02:49:35 PM PDT 24 13885361718 ps
T222 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.319732541 Mar 12 02:51:41 PM PDT 24 Mar 12 02:53:28 PM PDT 24 41973677452 ps
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T391 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2312982333 Mar 12 02:49:23 PM PDT 24 Mar 12 02:49:25 PM PDT 24 2470661691 ps
T392 /workspace/coverage/default/0.sysrst_ctrl_stress_all.749454024 Mar 12 02:48:43 PM PDT 24 Mar 12 02:48:54 PM PDT 24 6958980480 ps
T230 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1779384649 Mar 12 02:51:05 PM PDT 24 Mar 12 02:56:10 PM PDT 24 125165180066 ps
T86 /workspace/coverage/default/18.sysrst_ctrl_stress_all.819644702 Mar 12 02:49:58 PM PDT 24 Mar 12 02:50:09 PM PDT 24 17937147423 ps
T333 /workspace/coverage/default/10.sysrst_ctrl_stress_all.522614333 Mar 12 02:49:37 PM PDT 24 Mar 12 02:50:14 PM PDT 24 103246369722 ps
T100 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1126178537 Mar 12 02:50:24 PM PDT 24 Mar 12 02:50:52 PM PDT 24 41655080838 ps
T393 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3597399759 Mar 12 02:50:48 PM PDT 24 Mar 12 02:50:51 PM PDT 24 3219941960 ps
T394 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.588330296 Mar 12 02:50:23 PM PDT 24 Mar 12 02:50:32 PM PDT 24 2613639871 ps
T395 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2269794855 Mar 12 02:49:45 PM PDT 24 Mar 12 02:49:52 PM PDT 24 2455412186 ps
T396 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4136252121 Mar 12 02:50:58 PM PDT 24 Mar 12 02:51:06 PM PDT 24 3087704594 ps
T397 /workspace/coverage/default/6.sysrst_ctrl_alert_test.3554855811 Mar 12 02:49:19 PM PDT 24 Mar 12 02:49:22 PM PDT 24 2023953340 ps
T398 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2494734514 Mar 12 02:51:35 PM PDT 24 Mar 12 02:53:04 PM PDT 24 35285010523 ps
T101 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3809279312 Mar 12 02:51:32 PM PDT 24 Mar 12 02:51:40 PM PDT 24 25374426163 ps
T276 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3789302078 Mar 12 02:48:55 PM PDT 24 Mar 12 02:48:57 PM PDT 24 3629434907 ps
T344 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.31707517 Mar 12 02:50:23 PM PDT 24 Mar 12 02:52:39 PM PDT 24 51430153315 ps
T399 /workspace/coverage/default/20.sysrst_ctrl_smoke.2399783088 Mar 12 02:49:56 PM PDT 24 Mar 12 02:49:57 PM PDT 24 2161590911 ps
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T279 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.822106547 Mar 12 02:50:10 PM PDT 24 Mar 12 02:50:18 PM PDT 24 10607842878 ps
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T306 /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.1369828225 Mar 12 02:49:46 PM PDT 24 Mar 12 02:49:53 PM PDT 24 2169757172 ps
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