Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T6

11

T28

9

T29

10

auto[1]

955

1

T6

9

T28

11

T29

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

462

1

T6

6

T28

4

T29

5

from_0to1

461

1

T6

5

T28

5

T29

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977

1

T6

8

T28

8

T29

12

auto[1]

939

1

T6

12

T28

12

T29

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T6

13

T28

11

T29

9

auto[1]

944

1

T6

7

T28

9

T29

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T29

1

T70

1

T78

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T6

1

T28

1

T30

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T6

1

T28

1

T29

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T6

1

T28

2

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T6

1

T29

1

T59

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T29

2

T24

1

T67

3

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T6

2

T28

1

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T24

1

T67

1

T59

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T29

2

T67

1

T138

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T29

1

T24

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T6

1

T24

3

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T6

2

T24

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T6

1

T29

1

T24

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T28

2

T67

1

T30

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T6

1

T28

1

T78

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T28

1

T24

3

T30

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951

1

T6

12

T28

10

T29

8

auto[1]

965

1

T6

8

T28

10

T29

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

468

1

T6

5

T28

5

T29

4

from_0to1

468

1

T6

6

T28

5

T29

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T6

7

T28

11

T29

13

auto[1]

918

1

T6

13

T28

9

T29

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

964

1

T6

8

T28

11

T29

9

auto[1]

952

1

T6

12

T28

9

T29

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T24

2

T70

1

T30

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T6

1

T28

2

T29

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T6

2

T24

3

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T6

1

T29

2

T24

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T24

1

T70

1

T78

3

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T6

2

T28

1

T24

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T6

1

T28

1

T59

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T6

1

T67

1

T78

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T28

1

T24

1

T78

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T29

1

T67

1

T70

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T28

1

T78

1

T285

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T6

1

T28

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T6

1

T29

1

T24

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T28

2

T29

2

T70

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T6

1

T29

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T28

1

T24

4

T70

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T6

9

T28

8

T29

14

auto[1]

923

1

T6

11

T28

12

T29

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

446

1

T6

5

T28

6

T29

5

from_0to1

443

1

T6

6

T28

6

T29

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

938

1

T6

10

T28

10

T29

12

auto[1]

978

1

T6

10

T28

10

T29

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T6

15

T28

7

T29

11

auto[1]

927

1

T6

5

T28

13

T29

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T29

1

T24

3

T70

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T28

2

T29

1

T70

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T6

3

T29

1

T24

5

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T28

2

T24

1

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T6

1

T28

1

T29

2

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T6

1

T29

1

T24

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T24

2

T67

1

T70

3

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T6

1

T29

2

T24

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T29

1

T67

2

T30

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T6

1

T29

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T6

1

T28

1

T24

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T28

1

T24

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T28

1

T24

2

T285

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T28

2

T67

1

T78

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T6

1

T28

1

T24

2

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T6

2

T28

1

T24

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968

1

T6

12

T28

11

T29

9

auto[1]

948

1

T6

8

T28

9

T29

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

473

1

T6

7

T28

5

T29

5

from_0to1

475

1

T6

7

T28

5

T29

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

966

1

T6

10

T28

9

T29

10

auto[1]

950

1

T6

10

T28

11

T29

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968

1

T6

12

T28

9

T29

8

auto[1]

948

1

T6

8

T28

11

T29

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T6

3

T28

2

T29

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T6

1

T24

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T6

1

T24

3

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T29

1

T24

3

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T6

2

T28

1

T70

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T28

1

T78

1

T30

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T6

2

T28

1

T24

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T6

1

T28

1

T29

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T6

1

T28

2

T29

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T6

1

T30

1

T59

2

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T29

1

T24

1

T70

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T28

1

T29

1

T24

2

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T28

1

T29

2

T24

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T6

1

T29

1

T24

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T24

2

T30

1

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T6

1

T29

1

T24

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951

1

T6

10

T28

12

T29

12

auto[1]

965

1

T6

10

T28

8

T29

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

445

1

T6

5

T28

5

T29

3

from_0to1

448

1

T6

5

T28

4

T29

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

949

1

T6

15

T28

9

T29

11

auto[1]

967

1

T6

5

T28

11

T29

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

964

1

T6

8

T28

8

T29

9

auto[1]

952

1

T6

12

T28

12

T29

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T6

1

T29

1

T24

2

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T6

2

T28

1

T67

2

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T6

1

T28

1

T24

2

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T28

1

T67

1

T78

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T6

2

T28

1

T24

2

auto[0]

from_0to1

auto[0]

auto[1]

48

1

T29

1

T67

2

T205

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T28

1

T24

1

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T28

1

T29

1

T24

4

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T24

2

T70

1

T30

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T29

1

T285

1

T138

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T29

1

T24

2

T67

3

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T6

1

T28

2

T24

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T6

1

T67

1

T78

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T6

1

T28

1

T24

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T24

1

T70

1

T30

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T6

1

T70

2

T78

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T6

9

T28

10

T29

13

auto[1]

942

1

T6

11

T28

10

T29

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

431

1

T6

5

T28

3

T29

5

from_0to1

440

1

T6

5

T28

4

T29

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968

1

T6

10

T28

8

T29

10

auto[1]

948

1

T6

10

T28

12

T29

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T6

9

T28

11

T29

8

auto[1]

928

1

T6

11

T28

9

T29

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T29

1

T24

1

T67

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T6

1

T29

1

T24

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T28

2

T29

1

T24

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T28

1

T29

1

T24

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T6

1

T30

1

T285

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T6

1

T29

1

T67

3

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T6

1

T29

2

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T28

1

T29

1

T24

3

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T6

1

T29

1

T24

1

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T6

1

T24

3

T78

2

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T6

1

T70

2

T30

2

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T6

1

T24

1

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T28

1

T24

1

T78

2

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T6

1

T70

2

T30

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T6

1

T28

1

T24

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T28

1

T29

1

T24

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T6

8

T28

12

T29

6

auto[1]

955

1

T6

12

T28

8

T29

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

472

1

T6

3

T28

7

T29

3

from_0to1

465

1

T6

3

T28

6

T29

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

935

1

T6

10

T28

11

T29

6

auto[1]

981

1

T6

10

T28

9

T29

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T6

9

T28

11

T29

10

auto[1]

944

1

T6

11

T28

9

T29

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T6

1

T28

1

T24

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T28

1

T67

1

T78

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T28

1

T29

1

T24

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T6

1

T28

1

T24

3

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T28

2

T24

2

T70

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T24

1

T67

1

T78

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T28

1

T29

1

T24

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T24

1

T78

1

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T28

1

T29

1

T24

2

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T24

2

T67

1

T78

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T28

1

T24

1

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T6

1

T28

1

T29

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T6

1

T28

1

T29

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T6

2

T28

1

T24

4

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T24

1

T59

2

T285

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T28

1

T29

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

978

1

T6

10

T28

9

T29

10

auto[1]

938

1

T6

10

T28

11

T29

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

465

1

T6

6

T28

6

T29

3

from_0to1

460

1

T6

5

T28

6

T29

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T6

11

T28

11

T29

10

auto[1]

969

1

T6

9

T28

9

T29

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

975

1

T6

11

T28

9

T29

12

auto[1]

941

1

T6

9

T28

11

T29

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T6

1

T28

1

T67

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T6

1

T28

1

T29

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T6

1

T28

1

T24

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T6

2

T29

2

T24

3

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T6

1

T24

3

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T30

1

T138

1

T64

5

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T6

1

T28

1

T24

2

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T6

1

T28

1

T24

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T24

2

T67

2

T78

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T6

1

T28

2

T24

3

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T24

1

T70

1

T78

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T28

1

T24

1

T67

3

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T28

2

T29

1

T24

2

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T6

2

T28

1

T24

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T29

1

T24

2

T67

2

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T28

1

T24

1

T59

1