Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120476

1

T6

43

T1

318

T2

316

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143935	1			T6	62		T1	267		T2	259
values[0x0]	66289	1			T6	26		T1	331		T2	313
values[0x1]	66277	1			T6	35		T1	316		T2	316

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126480	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150021

1

T6

60

T1

408

T2

402

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	696	1			T2	1		T13	1		T5	2
valid_sources[0x01]	773	1			T1	13		T13	4		T8	7
valid_sources[0x02]	1904	1			T1	9		T2	2		T13	1
valid_sources[0x03]	1257	1			T2	4		T15	1		T8	8
valid_sources[0x04]	902	1			T1	7		T2	1		T13	4
valid_sources[0x05]	1539	1			T2	9		T13	1		T52	1
valid_sources[0x06]	892	1			T1	4		T2	1		T13	3
valid_sources[0x07]	976	1			T1	8		T2	8		T13	1
valid_sources[0x08]	1198	1			T1	3		T2	1		T13	5
valid_sources[0x09]	1695	1			T1	4		T2	8		T13	3
valid_sources[0x0a]	1040	1			T1	2		T13	2		T15	2
valid_sources[0x0b]	963	1			T1	5		T2	4		T13	1
valid_sources[0x0c]	767	1			T1	2		T2	11		T13	1
valid_sources[0x0d]	808	1			T1	5		T13	1		T15	3
valid_sources[0x0e]	1179	1			T1	4		T13	6		T15	2
valid_sources[0x0f]	986	1			T1	1		T2	2		T13	3
valid_sources[0x10]	769	1			T2	3		T13	1		T15	2
valid_sources[0x11]	625	1			T1	4		T14	1		T15	2
valid_sources[0x12]	1101	1			T1	3		T2	3		T13	1
valid_sources[0x13]	1110	1			T1	11		T2	3		T13	1
valid_sources[0x14]	2213	1			T1	6		T2	2		T13	2
valid_sources[0x15]	1513	1			T13	1		T15	3		T55	35
valid_sources[0x16]	1731	1			T1	4		T2	3		T13	4
valid_sources[0x17]	1080	1			T1	3		T13	1		T15	4
valid_sources[0x18]	919	1			T1	2		T2	1		T13	2
valid_sources[0x19]	956	1			T2	1		T15	4		T5	11
valid_sources[0x1a]	1135	1			T2	7		T15	5		T8	3
valid_sources[0x1b]	912	1			T1	2		T2	1		T13	5
valid_sources[0x1c]	905	1			T1	2		T13	1		T15	1
valid_sources[0x1d]	796	1			T1	1		T2	4		T13	1
valid_sources[0x1e]	896	1			T1	7		T13	5		T9	6
valid_sources[0x1f]	1148	1			T13	4		T15	1		T5	11
valid_sources[0x20]	1341	1			T2	10		T13	2		T15	4
valid_sources[0x21]	2382	1			T1	7		T2	5		T13	3
valid_sources[0x22]	1091	1			T2	7		T12	3		T13	4
valid_sources[0x23]	1181	1			T1	5		T2	3		T13	1
valid_sources[0x24]	855	1			T1	9		T2	5		T13	1
valid_sources[0x25]	945	1			T1	13		T13	1		T14	1
valid_sources[0x26]	2639	1			T1	15		T2	15		T13	5
valid_sources[0x27]	921	1			T1	9		T13	3		T14	2
valid_sources[0x28]	846	1			T1	1		T2	4		T15	1
valid_sources[0x29]	1103	1			T13	6		T15	7		T52	1
valid_sources[0x2a]	1088	1			T1	9		T2	4		T13	3
valid_sources[0x2b]	1034	1			T1	10		T2	5		T13	1
valid_sources[0x2c]	903	1			T2	5		T13	1		T52	1
valid_sources[0x2d]	1052	1			T1	6		T13	2		T15	2
valid_sources[0x2e]	783	1			T2	4		T13	3		T15	6
valid_sources[0x2f]	1268	1			T1	2		T13	3		T15	1
valid_sources[0x30]	901	1			T1	4		T13	1		T15	4
valid_sources[0x31]	1076	1			T1	4		T2	3		T13	2
valid_sources[0x32]	947	1			T2	5		T15	6		T8	17
valid_sources[0x33]	1092	1			T1	4		T2	5		T13	3
valid_sources[0x34]	1213	1			T2	5		T13	4		T15	1
valid_sources[0x35]	959	1			T15	2		T8	8		T9	5
valid_sources[0x36]	999	1			T2	2		T8	4		T9	4
valid_sources[0x37]	845	1			T1	1		T2	1		T15	6
valid_sources[0x38]	817	1			T1	4		T2	2		T13	2
valid_sources[0x39]	1043	1			T2	6		T14	1		T15	1
valid_sources[0x3a]	1406	1			T1	1		T2	13		T12	1
valid_sources[0x3b]	868	1			T1	1		T15	2		T5	15
valid_sources[0x3c]	1309	1			T2	2		T13	1		T15	3
valid_sources[0x3d]	1906	1			T1	7		T2	3		T12	2
valid_sources[0x3e]	1057	1			T1	4		T2	3		T13	1
valid_sources[0x3f]	1092	1			T2	9		T9	8		T34	4
valid_sources[0x40]	1780	1			T2	4		T13	3		T8	3
valid_sources[0x41]	1887	1			T1	14		T2	2		T13	2
valid_sources[0x42]	1496	1			T1	4		T2	1		T13	5
valid_sources[0x43]	2072	1			T1	1		T2	4		T13	1
valid_sources[0x44]	1360	1			T1	1		T2	6		T13	1
valid_sources[0x45]	1135	1			T6	123		T1	9		T13	3
valid_sources[0x46]	1072	1			T1	1		T2	7		T12	3
valid_sources[0x47]	774	1			T2	1		T15	2		T8	9
valid_sources[0x48]	1804	1			T1	1		T2	4		T13	2
valid_sources[0x49]	1076	1			T2	7		T13	6		T16	1
valid_sources[0x4a]	937	1			T1	5		T15	3		T8	5
valid_sources[0x4b]	858	1			T1	5		T13	2		T15	1
valid_sources[0x4c]	1225	1			T1	4		T13	5		T14	1
valid_sources[0x4d]	890	1			T1	1		T13	2		T15	1
valid_sources[0x4e]	980	1			T1	1		T2	1		T12	1
valid_sources[0x4f]	1211	1			T2	7		T13	2		T14	1
valid_sources[0x50]	1053	1			T1	3		T2	1		T13	11
valid_sources[0x51]	1033	1			T1	6		T13	3		T15	1
valid_sources[0x52]	1575	1			T1	3		T2	1		T13	3
valid_sources[0x53]	1998	1			T1	8		T2	13		T15	2
valid_sources[0x54]	1451	1			T1	3		T2	9		T8	13
valid_sources[0x55]	910	1			T1	6		T2	3		T13	2
valid_sources[0x56]	1170	1			T1	6		T2	10		T15	1
valid_sources[0x57]	753	1			T1	6		T12	4		T8	1
valid_sources[0x58]	952	1			T1	4		T2	2		T12	1
valid_sources[0x59]	1094	1			T1	3		T15	1		T8	1
valid_sources[0x5a]	885	1			T1	5		T2	3		T15	4
valid_sources[0x5b]	861	1			T1	4		T2	4		T13	5
valid_sources[0x5c]	825	1			T1	2		T2	6		T13	1
valid_sources[0x5d]	932	1			T1	3		T2	1		T14	1
valid_sources[0x5e]	785	1			T1	10		T2	2		T13	2
valid_sources[0x5f]	891	1			T1	5		T2	2		T13	1
valid_sources[0x60]	779	1			T2	1		T13	4		T14	1
valid_sources[0x61]	966	1			T1	4		T2	4		T13	2
valid_sources[0x62]	1547	1			T1	2		T13	2		T15	4
valid_sources[0x63]	831	1			T1	3		T2	4		T13	1
valid_sources[0x64]	827	1			T13	3		T14	1		T8	2
valid_sources[0x65]	1012	1			T1	3		T2	9		T13	1
valid_sources[0x66]	1158	1			T1	5		T2	5		T13	4
valid_sources[0x67]	968	1			T1	5		T2	3		T13	3
valid_sources[0x68]	1233	1			T1	2		T2	5		T13	3
valid_sources[0x69]	1120	1			T1	3		T2	7		T13	1
valid_sources[0x6a]	864	1			T2	7		T13	2		T5	7
valid_sources[0x6b]	1214	1			T1	3		T13	2		T15	2
valid_sources[0x6c]	1476	1			T1	1		T2	5		T13	6
valid_sources[0x6d]	1210	1			T1	2		T2	10		T8	5
valid_sources[0x6e]	793	1			T2	3		T5	5		T8	5
valid_sources[0x6f]	1025	1			T1	4		T2	4		T13	4
valid_sources[0x70]	1109	1			T1	3		T2	2		T13	2
valid_sources[0x71]	785	1			T1	1		T2	6		T13	2
valid_sources[0x72]	960	1			T1	3		T2	2		T13	3
valid_sources[0x73]	896	1			T1	6		T13	1		T15	1
valid_sources[0x74]	1451	1			T1	3		T2	15		T13	4
valid_sources[0x75]	826	1			T1	1		T13	1		T8	3
valid_sources[0x76]	862	1			T2	1		T13	5		T15	1
valid_sources[0x77]	867	1			T1	6		T2	1		T13	2
valid_sources[0x78]	1612	1			T13	7		T5	5		T8	6
valid_sources[0x79]	1418	1			T1	1		T2	1		T15	1
valid_sources[0x7a]	923	1			T1	4		T13	1		T15	1
valid_sources[0x7b]	976	1			T1	2		T2	4		T12	4
valid_sources[0x7c]	949	1			T1	1		T2	1		T13	3
valid_sources[0x7d]	663	1			T1	6		T2	1		T13	2
valid_sources[0x7e]	1614	1			T1	5		T13	4		T15	1
valid_sources[0x7f]	813	1			T1	1		T2	2		T13	1
valid_sources[0x80]	1398	1			T1	6		T2	5		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64932

1

T6

27

T1

135

T2

125

values[0x0]

all_enables

biggest_size

32656

1

T6

8

T1

124

T2

112

values[0x1]

all_enables

biggest_size

22888

1

T6

8

T1

59

T2

79