Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	95.65	100.00		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T18,T24,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T18,T24,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T18,T24,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T24,T30
1	0	Covered	T6,T1,T2
1	1	Covered	T18,T24,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T24,T42
0	1	Covered	T103,T110
1	0	Covered	T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T24,T42
0	1	Covered	T18,T24,T42
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T24,T42
1	-	Covered	T18,T24,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T24,T30
DetectSt	168	Covered	T18,T24,T42
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T18,T24,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T24,T42
DebounceSt->IdleSt	163	Covered	T30,T42,T43
DetectSt->IdleSt	186	Covered	T103,T110,T57
DetectSt->StableSt	191	Covered	T18,T24,T42
IdleSt->DebounceSt	148	Covered	T18,T24,T30
StableSt->IdleSt	206	Covered	T18,T24,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T24,T30
0	1	Covered	T18,T24,T30
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T24,T42
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T24,T30
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T24,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T42,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T24,T30
DetectSt	-	-	-	-	1	-	-	Covered	T103,T110,T57
DetectSt	-	-	-	-	0	1	-	Covered	T18,T24,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T24,T42
StableSt	-	-	-	-	-	-	0	Covered	T18,T24,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	290	0	0
CntIncr_A	9144370	135674	0	0
CntNoWrap_A	9144370	8508165	0	0
DetectStDropOut_A	9144370	2	0	0
DetectedOut_A	9144370	900	0	0
DetectedPulseOut_A	9144370	129	0	0
DisabledIdleSt_A	9144370	8365904	0	0
DisabledNoDetection_A	9144370	8368149	0	0
EnterDebounceSt_A	9144370	161	0	0
EnterDetectSt_A	9144370	132	0	0
EnterStableSt_A	9144370	129	0	0
PulseIsPulse_A	9144370	129	0	0
StayInStableSt	9144370	771	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9144370	6739	0	0
gen_low_level_sva.LowLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	128	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	290	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	2	0	0
T24	0	4	0	0
T30	0	1	0	0
T40	0	1	0	0
T42	0	5	0	0
T43	0	4	0	0
T45	0	2	0	0
T47	0	6	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	135674	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	37	0	0
T24	0	62	0	0
T30	0	94	0	0
T40	0	76	0	0
T42	0	137	0	0
T43	0	252	0	0
T45	0	14	0	0
T47	0	41393	0	0
T48	0	77	0	0
T49	0	127	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508165	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	269	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2	0	0
T103	671	1	0	0
T104	4566	0	0	0
T110	0	1	0	0
T111	422	0	0	0
T112	1345	0	0	0
T113	422	0	0	0
T114	428	0	0	0
T115	15811	0	0	0
T116	14745	0	0	0
T117	428	0	0	0
T118	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	900	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	9	0	0
T24	0	13	0	0
T42	0	9	0	0
T43	0	5	0	0
T45	0	2	0	0
T47	0	10	0	0
T48	0	4	0	0
T49	0	15	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	6	0	0
T121	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	129	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	1	0	0
T24	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	1	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8365904	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	187	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8368149	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	188	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	161	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	1	0	0
T24	0	2	0	0
T30	0	1	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	132	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	1	0	0
T24	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	129	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	1	0	0
T24	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	1	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	129	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	1	0	0
T24	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	1	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	771	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	8	0	0
T24	0	11	0	0
T42	0	7	0	0
T43	0	4	0	0
T45	0	1	0	0
T47	0	7	0	0
T48	0	3	0	0
T49	0	13	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	5	0	0
T121	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6739	0	0
T1	11840	29	0	0
T2	15507	28	0	0
T4	0	10	0	0
T6	507	6	0	0
T12	443	4	0	0
T13	17092	10	0	0
T14	494	8	0	0
T15	16466	22	0	0
T16	515	0	0	0
T17	422	3	0	0
T18	672	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	128	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	1	0	0
T24	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	3	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T120	0	1	0	0
T121	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T24,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T25,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T6,T1,T2
1	1	Covered	T24,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Covered	T24,T62,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Unreachable
1	0	Covered	T24,T25,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T25,T26
DetectSt	168	Covered	T24,T25,T26
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T24,T25,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T25,T26
DebounceSt->IdleSt	163	Covered	T49,T62,T64
DetectSt->IdleSt	186	Covered	T24,T62,T95
DetectSt->StableSt	191	Covered	T24,T25,T26
IdleSt->DebounceSt	148	Covered	T24,T25,T26
StableSt->IdleSt	206	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T25,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T62,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T24,T62,T95
DetectSt	-	-	-	-	0	1	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T25,T26
StableSt	-	-	-	-	-	-	0	Covered	T24,T25,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	196	0	0
CntIncr_A	9144370	311895	0	0
CntNoWrap_A	9144370	8508259	0	0
DetectStDropOut_A	9144370	21	0	0
DetectedOut_A	9144370	99868	0	0
DetectedPulseOut_A	9144370	44	0	0
DisabledIdleSt_A	9144370	6840600	0	0
DisabledNoDetection_A	9144370	6842895	0	0
EnterDebounceSt_A	9144370	133	0	0
EnterDetectSt_A	9144370	65	0	0
EnterStableSt_A	9144370	44	0	0
PulseIsPulse_A	9144370	44	0	0
StayInStableSt	9144370	99824	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9144370	6739	0	0
gen_low_level_sva.LowLevelEvent_A	9144370	8510753	0	0
gen_sticky_sva.StableStDropOut_A	9144370	740310	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	196	0	0
T24	247596	10	0	0
T25	1657	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	16125	0	0	0
T61	0	2	0	0
T62	0	8	0	0
T64	0	4	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	311895	0	0
T24	247596	359	0	0
T25	1657	118	0	0
T26	0	38	0	0
T49	0	120	0	0
T58	16125	0	0	0
T61	0	47	0	0
T62	0	315	0	0
T64	0	52	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	70	0	0
T85	0	25	0	0
T86	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508259	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	21	0	0
T24	247596	3	0	0
T25	1657	0	0	0
T58	16125	0	0	0
T62	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T95	0	3	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	3	0	0
T128	0	3	0	0
T129	0	4	0	0
T130	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	99868	0	0
T24	247596	161	0	0
T25	1657	308	0	0
T26	0	190	0	0
T58	16125	0	0	0
T61	0	330	0	0
T62	0	1	0	0
T64	0	48	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	259	0	0
T85	0	169	0	0
T86	0	361	0	0
T93	0	547	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	44	0	0
T24	247596	2	0	0
T25	1657	2	0	0
T26	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6840600	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6842895	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	133	0	0
T24	247596	5	0	0
T25	1657	2	0	0
T26	0	1	0	0
T49	0	2	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	5	0	0
T64	0	3	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	65	0	0
T24	247596	5	0	0
T25	1657	2	0	0
T26	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	3	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	44	0	0
T24	247596	2	0	0
T25	1657	2	0	0
T26	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	44	0	0
T24	247596	2	0	0
T25	1657	2	0	0
T26	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	99824	0	0
T24	247596	159	0	0
T25	1657	306	0	0
T26	0	189	0	0
T58	16125	0	0	0
T61	0	329	0	0
T64	0	47	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	258	0	0
T85	0	168	0	0
T86	0	360	0	0
T93	0	546	0	0
T123	0	574	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6739	0	0
T1	11840	29	0	0
T2	15507	28	0	0
T4	0	10	0	0
T6	507	6	0	0
T12	443	4	0	0
T13	17092	10	0	0
T14	494	8	0	0
T15	16466	22	0	0
T16	515	0	0	0
T17	422	3	0	0
T18	672	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	740310	0	0
T24	247596	76	0	0
T25	1657	488	0	0
T26	0	278	0	0
T58	16125	0	0	0
T61	0	188	0	0
T62	0	45	0	0
T64	0	150590	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	57	0	0
T85	0	258	0	0
T86	0	339	0	0
T93	0	84	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T12,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T12,T14
1	1	Covered	T6,T12,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T24,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T25,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T6,T12,T14
1	1	Covered	T24,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T49
0	1	Covered	T61,T62,T64
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T49
0	1	Unreachable
1	0	Covered	T24,T25,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T25,T26
DetectSt	168	Covered	T24,T25,T49
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T24,T25,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T25,T49
DebounceSt->IdleSt	163	Covered	T26,T61,T62
DetectSt->IdleSt	186	Covered	T61,T62,T64
DetectSt->StableSt	191	Covered	T24,T25,T49
IdleSt->DebounceSt	148	Covered	T24,T25,T26
StableSt->IdleSt	206	Covered	T24,T25,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T49
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T12,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T25,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T61,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T61,T62,T64
DetectSt	-	-	-	-	0	1	-	Covered	T24,T25,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T25,T49
StableSt	-	-	-	-	-	-	0	Covered	T24,T25,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	211	0	0
CntIncr_A	9144370	119063	0	0
CntNoWrap_A	9144370	8508244	0	0
DetectStDropOut_A	9144370	28	0	0
DetectedOut_A	9144370	455930	0	0
DetectedPulseOut_A	9144370	42	0	0
DisabledIdleSt_A	9144370	6840600	0	0
DisabledNoDetection_A	9144370	6842895	0	0
EnterDebounceSt_A	9144370	143	0	0
EnterDetectSt_A	9144370	70	0	0
EnterStableSt_A	9144370	42	0	0
PulseIsPulse_A	9144370	42	0	0
StayInStableSt	9144370	455888	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_sticky_sva.StableStDropOut_A	9144370	642468	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	211	0	0
T24	247596	6	0	0
T25	1657	4	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T61	0	6	0	0
T62	0	9	0	0
T64	0	7	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	119063	0	0
T24	247596	33623	0	0
T25	1657	112	0	0
T26	0	144	0	0
T49	0	63	0	0
T58	16125	0	0	0
T61	0	445	0	0
T62	0	370	0	0
T64	0	315	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	91	0	0
T85	0	47	0	0
T86	0	220	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508244	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	28	0	0
T61	1347	1	0	0
T62	1000	3	0	0
T64	0	2	0	0
T76	496	0	0	0
T90	23292	0	0	0
T127	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	8	0	0
T137	405	0	0	0
T138	502	0	0	0
T139	2294	0	0	0
T140	792	0	0	0
T141	428	0	0	0
T142	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	455930	0	0
T24	247596	66228	0	0
T25	1657	642	0	0
T49	0	87	0	0
T58	16125	0	0	0
T62	0	1	0	0
T64	0	37	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	217	0	0
T85	0	200	0	0
T93	0	147	0	0
T123	0	314	0	0
T124	0	698	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	42	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T49	0	1	0	0
T58	16125	0	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6840600	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6842895	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	143	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T26	0	3	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	5	0	0
T62	0	5	0	0
T64	0	4	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	70	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	4	0	0
T64	0	3	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	42	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T49	0	1	0	0
T58	16125	0	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	42	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T49	0	1	0	0
T58	16125	0	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T93	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	455888	0	0
T24	247596	66225	0	0
T25	1657	640	0	0
T49	0	86	0	0
T58	16125	0	0	0
T64	0	36	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	216	0	0
T85	0	199	0	0
T93	0	146	0	0
T123	0	313	0	0
T124	0	696	0	0
T143	0	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	642468	0	0
T24	247596	378	0	0
T25	1657	148	0	0
T49	0	79	0	0
T58	16125	0	0	0
T62	0	30	0	0
T64	0	193	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	74	0	0
T85	0	211	0	0
T93	0	530	0	0
T123	0	375	0	0
T124	0	119	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T24,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T25,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T6,T1,T2
1	1	Covered	T24,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Covered	T24,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Unreachable
1	0	Covered	T24,T25,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T25,T26
DetectSt	168	Covered	T24,T25,T26
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T24,T25,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T25,T26
DebounceSt->IdleSt	163	Covered	T64,T123,T144
DetectSt->IdleSt	186	Covered	T24,T93,T94
DetectSt->StableSt	191	Covered	T24,T25,T26
IdleSt->DebounceSt	148	Covered	T24,T25,T26
StableSt->IdleSt	206	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T25,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T123,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T24,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T25,T26
StableSt	-	-	-	-	-	-	0	Covered	T24,T25,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	188	0	0
CntIncr_A	9144370	260596	0	0
CntNoWrap_A	9144370	8508267	0	0
DetectStDropOut_A	9144370	16	0	0
DetectedOut_A	9144370	435141	0	0
DetectedPulseOut_A	9144370	54	0	0
DisabledIdleSt_A	9144370	6840600	0	0
DisabledNoDetection_A	9144370	6842895	0	0
EnterDebounceSt_A	9144370	120	0	0
EnterDetectSt_A	9144370	70	0	0
EnterStableSt_A	9144370	54	0	0
PulseIsPulse_A	9144370	54	0	0
StayInStableSt	9144370	435087	0	0
gen_high_event_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_sticky_sva.StableStDropOut_A	9144370	484090	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	188	0	0
T24	247596	8	0	0
T25	1657	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	16125	0	0	0
T61	0	2	0	0
T62	0	4	0	0
T64	0	5	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	260596	0	0
T24	247596	182	0	0
T25	1657	98	0	0
T26	0	72	0	0
T49	0	17	0	0
T58	16125	0	0	0
T61	0	10	0	0
T62	0	74	0	0
T64	0	150689	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	73	0	0
T85	0	97	0	0
T86	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508267	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	16	0	0
T24	247596	1	0	0
T25	1657	0	0	0
T58	16125	0	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T93	0	2	0	0
T94	0	4	0	0
T134	0	4	0	0
T145	0	3	0	0
T146	0	1	0	0
T147	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	435141	0	0
T24	247596	183	0	0
T25	1657	491	0	0
T26	0	296	0	0
T49	0	35	0	0
T58	16125	0	0	0
T61	0	58	0	0
T62	0	140	0	0
T64	0	146	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	148	0	0
T85	0	327	0	0
T86	0	409	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	54	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T26	0	1	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6840600	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6842895	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	120	0	0
T24	247596	4	0	0
T25	1657	2	0	0
T26	0	1	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	2	0	0
T64	0	4	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	70	0	0
T24	247596	4	0	0
T25	1657	2	0	0
T26	0	1	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	54	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T26	0	1	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	54	0	0
T24	247596	3	0	0
T25	1657	2	0	0
T26	0	1	0	0
T49	0	1	0	0
T58	16125	0	0	0
T61	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	435087	0	0
T24	247596	180	0	0
T25	1657	489	0	0
T26	0	295	0	0
T49	0	34	0	0
T58	16125	0	0	0
T61	0	57	0	0
T62	0	138	0	0
T64	0	145	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	147	0	0
T85	0	326	0	0
T86	0	408	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	484090	0	0
T24	247596	50081	0	0
T25	1657	343	0	0
T26	0	138	0	0
T49	0	180	0	0
T58	16125	0	0	0
T61	0	499	0	0
T62	0	318	0	0
T64	0	36	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	168	0	0
T85	0	41	0	0
T86	0	266	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T7,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T7,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T7,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T11
1	0	Covered	T6,T1,T2
1	1	Covered	T7,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T24
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T24,T120
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T11
1	-	Covered	T7,T24,T120

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T11
DetectSt	168	Covered	T7,T10,T11
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T11
DebounceSt->IdleSt	163	Covered	T148
DetectSt->IdleSt	186	Covered	T24
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T7,T10,T11
StableSt->IdleSt	206	Covered	T7,T24,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T148
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T24
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T24,T120
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	75	0	0
CntIncr_A	9144370	22721	0	0
CntNoWrap_A	9144370	8508380	0	0
DetectStDropOut_A	9144370	1	0	0
DetectedOut_A	9144370	2462	0	0
DetectedPulseOut_A	9144370	36	0	0
DisabledIdleSt_A	9144370	8447983	0	0
DisabledNoDetection_A	9144370	8450241	0	0
EnterDebounceSt_A	9144370	38	0	0
EnterDetectSt_A	9144370	37	0	0
EnterStableSt_A	9144370	36	0	0
PulseIsPulse_A	9144370	36	0	0
StayInStableSt	9144370	2405	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	75	0	0
T7	649	4	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	2	0	0
T11	0	2	0	0
T24	0	10	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	2	0	0
T40	0	2	0	0
T55	434	0	0	0
T64	0	2	0	0
T84	0	2	0	0
T120	0	4	0	0
T149	0	2	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	22721	0	0
T7	649	60	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	38	0	0
T11	0	84	0	0
T24	0	256	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	81	0	0
T40	0	82	0	0
T55	434	0	0	0
T64	0	78	0	0
T84	0	26	0	0
T120	0	112	0	0
T149	0	25	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508380	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1	0	0
T24	247596	1	0	0
T25	1657	0	0	0
T58	16125	0	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2462	0	0
T7	649	89	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	312	0	0
T11	0	39	0	0
T24	0	428	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	40	0	0
T40	0	126	0	0
T55	434	0	0	0
T64	0	131	0	0
T84	0	40	0	0
T120	0	45	0	0
T149	0	44	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	36	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	4	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T84	0	1	0	0
T120	0	2	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8447983	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8450241	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	38	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	5	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T84	0	1	0	0
T120	0	2	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	37	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	5	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T84	0	1	0	0
T120	0	2	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	36	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	4	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T84	0	1	0	0
T120	0	2	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	36	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	4	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T84	0	1	0	0
T120	0	2	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2405	0	0
T7	649	86	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	310	0	0
T11	0	37	0	0
T24	0	422	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	38	0	0
T40	0	124	0	0
T55	434	0	0	0
T64	0	129	0	0
T84	0	38	0	0
T120	0	42	0	0
T149	0	43	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	13	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T55	434	0	0	0
T120	0	1	0	0
T136	0	1	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T7,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T7,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T7,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T11
1	0	Covered	T6,T1,T2
1	1	Covered	T7,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T153,T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T11
1	-	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T11
DetectSt	168	Covered	T7,T10,T11
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T11
DebounceSt->IdleSt	163	Covered	T159,T133
DetectSt->IdleSt	186	Covered	T7,T153,T158
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T7,T10,T11
StableSt->IdleSt	206	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T159,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T7,T153,T158
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	108	0	0
CntIncr_A	9144370	23295	0	0
CntNoWrap_A	9144370	8508347	0	0
DetectStDropOut_A	9144370	3	0	0
DetectedOut_A	9144370	9104	0	0
DetectedPulseOut_A	9144370	50	0	0
DisabledIdleSt_A	9144370	8447692	0	0
DisabledNoDetection_A	9144370	8449939	0	0
EnterDebounceSt_A	9144370	56	0	0
EnterDetectSt_A	9144370	53	0	0
EnterStableSt_A	9144370	50	0	0
PulseIsPulse_A	9144370	50	0	0
StayInStableSt	9144370	9029	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9144370	2372	0	0
gen_low_level_sva.LowLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	108	0	0
T7	649	4	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	2	0	0
T11	0	2	0	0
T24	0	4	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T55	434	0	0	0
T64	0	2	0	0
T120	0	2	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	23295	0	0
T7	649	60	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	38	0	0
T11	0	84	0	0
T24	0	118	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	81	0	0
T40	0	82	0	0
T41	0	38	0	0
T55	434	0	0	0
T64	0	21	0	0
T120	0	66	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508347	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	3	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T27	491	0	0	0
T28	502	0	0	0
T55	434	0	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T153	0	1	0	0
T158	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	9104	0	0
T7	649	28	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	29	0	0
T11	0	170	0	0
T24	0	86	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	12	0	0
T40	0	44	0	0
T41	0	90	0	0
T55	434	0	0	0
T64	0	133	0	0
T120	0	36	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	50	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8447692	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8449939	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	56	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	53	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	50	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	50	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	9029	0	0
T7	649	27	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	28	0	0
T11	0	169	0	0
T24	0	84	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	11	0	0
T40	0	43	0	0
T41	0	88	0	0
T55	434	0	0	0
T64	0	131	0	0
T120	0	35	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T160	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2372	0	0
T1	11840	0	0	0
T2	15507	0	0	0
T3	0	1	0	0
T6	507	6	0	0
T7	0	2	0	0
T10	0	1	0	0
T12	443	4	0	0
T13	17092	0	0	0
T14	494	5	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	3	0	0
T18	672	0	0	0
T27	0	4	0	0
T28	0	5	0	0
T55	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	23	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	1	0	0
T11	0	1	0	0
T24	0	2	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T55	434	0	0	0
T120	0	1	0	0
T148	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T159	0	1	0	0
T161	0	1	0	0