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Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.92 89.13 90.48 66.67 85.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.92 89.13 90.48 66.67 85.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 95.65 95.24 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 95.65 95.24 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 95.65 95.24 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 95.65 95.24 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.77 91.30 90.48 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.77 91.30 90.48 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 95.65 95.24 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 95.65 95.24 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.77 91.30 90.48 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.77 91.30 90.48 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464189.13
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322784.38
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT6,T1,T2
10CoveredT6,T1,T2
11CoveredT6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT7,T24,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT6,T1,T2 VC_COV_UNR
1CoveredT7,T24,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT7,T24,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T7,T10
10CoveredT6,T1,T2
11CoveredT7,T24,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T24,T38
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT7,T24,T38
01CoveredT7,T24,T38
10CoveredT56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT7,T24,T38
1-CoveredT7,T24,T38

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T7,T24,T38
DetectSt 168 Covered T7,T24,T38
IdleSt 163 Covered T6,T1,T2
StableSt 191 Covered T7,T24,T38


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T7,T24,T38
DebounceSt->IdleSt 163 Not Covered
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T7,T24,T38
IdleSt->DebounceSt 148 Covered T7,T24,T38
StableSt->IdleSt 206 Covered T7,T24,T38



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 17 85.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 7 70.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T7,T24,T38
0 1 Covered T7,T24,T38
0 0 Excluded T6,T1,T2 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T24,T38
0 Covered T6,T1,T2


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T24,T38
IdleSt 0 - - - - - - Covered T6,T1,T2
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T7,T24,T38
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T7,T24,T38
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T7,T24,T38
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T7,T24,T38
StableSt - - - - - - 0 Covered T7,T24,T38
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 9144370 72 0 0
CntIncr_A 9144370 2095 0 0
CntNoWrap_A 9144370 8508383 0 0
DetectStDropOut_A 9144370 0 0 0
DetectedOut_A 9144370 2957 0 0
DetectedPulseOut_A 9144370 36 0 0
DisabledIdleSt_A 9144370 8490645 0 0
DisabledNoDetection_A 9144370 8492884 0 0
EnterDebounceSt_A 9144370 36 0 0
EnterDetectSt_A 9144370 36 0 0
EnterStableSt_A 9144370 36 0 0
PulseIsPulse_A 9144370 36 0 0
StayInStableSt 9144370 2902 0 0
gen_high_level_sva.HighLevelEvent_A 9144370 8510753 0 0
gen_not_sticky_sva.StableStDropOut_A 9144370 15 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 72 0 0
T7 649 2 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 4 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 2 0 0
T38 0 2 0 0
T40 0 2 0 0
T55 434 0 0 0
T86 0 2 0 0
T88 0 2 0 0
T123 0 2 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 2 0 0
T163 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2095 0 0
T7 649 30 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 118 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 66 0 0
T38 0 52 0 0
T40 0 82 0 0
T55 434 0 0 0
T86 0 78 0 0
T88 0 92 0 0
T123 0 50 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 23 0 0
T163 0 71 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8508383 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2957 0 0
T7 649 71 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 190 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 347 0 0
T38 0 24 0 0
T40 0 44 0 0
T55 434 0 0 0
T86 0 40 0 0
T88 0 47 0 0
T123 0 40 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 42 0 0
T163 0 94 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 36 0 0
T7 649 1 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 2 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T55 434 0 0 0
T86 0 1 0 0
T88 0 1 0 0
T123 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 1 0 0
T163 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8490645 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8492884 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 36 0 0
T7 649 1 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 2 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T55 434 0 0 0
T86 0 1 0 0
T88 0 1 0 0
T123 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 1 0 0
T163 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 36 0 0
T7 649 1 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 2 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T55 434 0 0 0
T86 0 1 0 0
T88 0 1 0 0
T123 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 1 0 0
T163 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 36 0 0
T7 649 1 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 2 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T55 434 0 0 0
T86 0 1 0 0
T88 0 1 0 0
T123 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 1 0 0
T163 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 36 0 0
T7 649 1 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 2 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T55 434 0 0 0
T86 0 1 0 0
T88 0 1 0 0
T123 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 1 0 0
T163 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2902 0 0
T7 649 70 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 187 0 0
T27 491 0 0 0
T28 502 0 0 0
T36 0 345 0 0
T38 0 23 0 0
T40 0 42 0 0
T55 434 0 0 0
T86 0 38 0 0
T88 0 45 0 0
T123 0 38 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T162 0 40 0 0
T163 0 92 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8510753 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 15 0 0
T7 649 1 0 0
T8 26285 0 0 0
T9 20704 0 0 0
T10 828 0 0 0
T24 0 1 0 0
T27 491 0 0 0
T28 502 0 0 0
T38 0 1 0 0
T55 434 0 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T156 0 2 0 0
T159 0 1 0 0
T164 0 1 0 0
T165 0 1 0 0
T166 0 1 0 0
T167 0 1 0 0
T168 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT6,T1,T2
10CoveredT6,T1,T2
11CoveredT6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT24,T30,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT6,T1,T2 VC_COV_UNR
1CoveredT24,T30,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT24,T30,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT24,T30,T39
10CoveredT6,T1,T2
11CoveredT24,T30,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT24,T39,T41
01CoveredT30,T88,T169
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT24,T39,T41
01CoveredT24,T39,T35
10CoveredT56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT24,T39,T41
1-CoveredT24,T39,T35

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T24,T30,T39
DetectSt 168 Covered T24,T30,T39
IdleSt 163 Covered T6,T1,T2
StableSt 191 Covered T24,T39,T41


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T24,T30,T39
DebounceSt->IdleSt 163 Covered T30,T35,T123
DetectSt->IdleSt 186 Covered T30,T88,T169
DetectSt->StableSt 191 Covered T24,T39,T41
IdleSt->DebounceSt 148 Covered T24,T30,T39
StableSt->IdleSt 206 Covered T24,T39,T35



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T24,T30,T39
0 1 Covered T24,T30,T39
0 0 Excluded T6,T1,T2 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T24,T30,T39
0 Covered T6,T1,T2


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T24,T30,T39
IdleSt 0 - - - - - - Covered T6,T1,T2
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T24,T30,T39
DebounceSt - 0 1 0 - - - Covered T30,T35,T123
DebounceSt - 0 0 - - - - Covered T24,T30,T39
DetectSt - - - - 1 - - Covered T30,T88,T169
DetectSt - - - - 0 1 - Covered T24,T39,T41
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T24,T39,T35
StableSt - - - - - - 0 Covered T24,T39,T41
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 9144370 125 0 0
CntIncr_A 9144370 28214 0 0
CntNoWrap_A 9144370 8508330 0 0
DetectStDropOut_A 9144370 4 0 0
DetectedOut_A 9144370 4294 0 0
DetectedPulseOut_A 9144370 55 0 0
DisabledIdleSt_A 9144370 8431310 0 0
DisabledNoDetection_A 9144370 8433555 0 0
EnterDebounceSt_A 9144370 66 0 0
EnterDetectSt_A 9144370 59 0 0
EnterStableSt_A 9144370 55 0 0
PulseIsPulse_A 9144370 55 0 0
StayInStableSt 9144370 4215 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 9144370 2755 0 0
gen_low_level_sva.LowLevelEvent_A 9144370 8510753 0 0
gen_not_sticky_sva.StableStDropOut_A 9144370 29 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 125 0 0
T24 247596 6 0 0
T25 1657 0 0 0
T30 0 3 0 0
T35 0 5 0 0
T36 0 2 0 0
T37 0 2 0 0
T39 0 4 0 0
T41 0 2 0 0
T58 16125 0 0 0
T64 0 4 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T88 0 2 0 0
T170 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 28214 0 0
T24 247596 168 0 0
T25 1657 0 0 0
T30 0 96 0 0
T35 0 90 0 0
T36 0 24838 0 0
T37 0 81 0 0
T39 0 98 0 0
T41 0 38 0 0
T58 16125 0 0 0
T64 0 182 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T88 0 92 0 0
T170 0 41 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8508330 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 4 0 0
T26 1624 0 0 0
T30 11511 1 0 0
T42 648 0 0 0
T43 780 0 0 0
T73 489 0 0 0
T80 697 0 0 0
T88 0 1 0 0
T96 18716 0 0 0
T169 0 1 0 0
T171 0 1 0 0
T172 424 0 0 0
T173 427 0 0 0
T174 428 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 4294 0 0
T24 247596 301 0 0
T25 1657 0 0 0
T35 0 97 0 0
T36 0 42 0 0
T37 0 134 0 0
T39 0 49 0 0
T41 0 89 0 0
T58 16125 0 0 0
T64 0 149 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 47 0 0
T170 0 261 0 0
T175 0 153 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 55 0 0
T24 247596 3 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 2 0 0
T41 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8431310 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8433555 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 66 0 0
T24 247596 3 0 0
T25 1657 0 0 0
T30 0 2 0 0
T35 0 3 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 2 0 0
T41 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T88 0 1 0 0
T170 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 59 0 0
T24 247596 3 0 0
T25 1657 0 0 0
T30 0 1 0 0
T35 0 2 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 2 0 0
T41 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T88 0 1 0 0
T170 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 55 0 0
T24 247596 3 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 2 0 0
T41 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 55 0 0
T24 247596 3 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 2 0 0
T41 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 4215 0 0
T24 247596 297 0 0
T25 1657 0 0 0
T35 0 94 0 0
T36 0 40 0 0
T37 0 132 0 0
T39 0 46 0 0
T41 0 87 0 0
T58 16125 0 0 0
T64 0 147 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 45 0 0
T170 0 259 0 0
T175 0 151 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2755 0 0
T1 11840 0 0 0
T2 15507 0 0 0
T3 0 1 0 0
T6 507 4 0 0
T7 0 2 0 0
T12 443 6 0 0
T13 17092 0 0 0
T14 494 6 0 0
T15 16466 0 0 0
T16 515 4 0 0
T17 422 2 0 0
T18 672 0 0 0
T50 0 6 0 0
T53 0 4 0 0
T55 0 4 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8510753 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 29 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 1 0 0
T39 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T153 0 2 0 0
T161 0 2 0 0
T163 0 1 0 0
T176 0 1 0 0
T177 0 1 0 0
T178 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT6,T1,T2
10CoveredT6,T1,T2
11CoveredT6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT6,T1,T2 VC_COV_UNR
1CoveredT3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT6,T1,T2
11CoveredT3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT3,T10,T11
01CoveredT40,T175,T179
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT3,T10,T11
01CoveredT10,T24,T80
10CoveredT56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT3,T10,T11
1-CoveredT10,T24,T80

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T3,T10,T11
DetectSt 168 Covered T3,T10,T11
IdleSt 163 Covered T6,T1,T2
StableSt 191 Covered T3,T10,T11


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T3,T10,T11
DebounceSt->IdleSt 163 Covered T148,T180,T181
DetectSt->IdleSt 186 Covered T40,T175,T179
DetectSt->StableSt 191 Covered T3,T10,T11
IdleSt->DebounceSt 148 Covered T3,T10,T11
StableSt->IdleSt 206 Covered T10,T24,T80



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T3,T10,T11
0 1 Covered T3,T10,T11
0 0 Excluded T6,T1,T2 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T3,T10,T11
0 Covered T6,T1,T2


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T3,T10,T11
IdleSt 0 - - - - - - Covered T6,T1,T2
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T3,T10,T11
DebounceSt - 0 1 0 - - - Covered T148,T180,T181
DebounceSt - 0 0 - - - - Covered T3,T10,T11
DetectSt - - - - 1 - - Covered T40,T175,T179
DetectSt - - - - 0 1 - Covered T3,T10,T11
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T10,T24,T80
StableSt - - - - - - 0 Covered T3,T10,T11
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 9144370 127 0 0
CntIncr_A 9144370 37185 0 0
CntNoWrap_A 9144370 8508328 0 0
DetectStDropOut_A 9144370 6 0 0
DetectedOut_A 9144370 11110 0 0
DetectedPulseOut_A 9144370 56 0 0
DisabledIdleSt_A 9144370 8358468 0 0
DisabledNoDetection_A 9144370 8360715 0 0
EnterDebounceSt_A 9144370 65 0 0
EnterDetectSt_A 9144370 62 0 0
EnterStableSt_A 9144370 56 0 0
PulseIsPulse_A 9144370 56 0 0
StayInStableSt 9144370 11028 0 0
gen_high_level_sva.HighLevelEvent_A 9144370 8510753 0 0
gen_not_sticky_sva.StableStDropOut_A 9144370 28 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 127 0 0
T3 625 2 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 2 0 0
T11 0 2 0 0
T24 0 8 0 0
T36 0 2 0 0
T37 0 2 0 0
T39 0 2 0 0
T40 0 4 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 4 0 0
T88 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 37185 0 0
T3 625 88 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 38 0 0
T11 0 84 0 0
T24 0 191 0 0
T36 0 24838 0 0
T37 0 81 0 0
T39 0 49 0 0
T40 0 164 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 86 0 0
T88 0 92 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8508328 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 6 0 0
T39 853 0 0 0
T40 34038 1 0 0
T45 594 0 0 0
T46 5566 0 0 0
T47 41907 0 0 0
T155 0 1 0 0
T175 0 1 0 0
T179 0 1 0 0
T181 0 2 0 0
T182 612 0 0 0
T183 17244 0 0 0
T184 35234 0 0 0
T185 423 0 0 0
T186 522 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 11110 0 0
T3 625 128 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 110 0 0
T11 0 395 0 0
T24 0 249 0 0
T36 0 42 0 0
T37 0 39 0 0
T39 0 97 0 0
T40 0 43 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 81 0 0
T88 0 140 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 56 0 0
T3 625 1 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 1 0 0
T11 0 1 0 0
T24 0 4 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 2 0 0
T88 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8358468 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8360715 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 65 0 0
T3 625 1 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 1 0 0
T11 0 1 0 0
T24 0 4 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 2 0 0
T88 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 62 0 0
T3 625 1 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 1 0 0
T11 0 1 0 0
T24 0 4 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 2 0 0
T88 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 56 0 0
T3 625 1 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 1 0 0
T11 0 1 0 0
T24 0 4 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 2 0 0
T88 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 56 0 0
T3 625 1 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 1 0 0
T11 0 1 0 0
T24 0 4 0 0
T36 0 1 0 0
T37 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 2 0 0
T88 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 11028 0 0
T3 625 126 0 0
T4 22800 0 0 0
T5 16581 0 0 0
T7 649 0 0 0
T10 0 109 0 0
T11 0 393 0 0
T24 0 244 0 0
T36 0 40 0 0
T37 0 37 0 0
T39 0 96 0 0
T40 0 42 0 0
T50 800 0 0 0
T51 422 0 0 0
T52 1217 0 0 0
T53 705 0 0 0
T54 402 0 0 0
T55 434 0 0 0
T80 0 78 0 0
T88 0 138 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8510753 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 28 0 0
T10 828 1 0 0
T11 889 0 0 0
T24 0 3 0 0
T28 502 0 0 0
T29 502 0 0 0
T34 14374 0 0 0
T39 0 1 0 0
T40 0 1 0 0
T64 0 3 0 0
T77 527 0 0 0
T80 0 1 0 0
T148 0 1 0 0
T149 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T161 0 1 0 0
T170 0 1 0 0
T187 422 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464291.30
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322887.50
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT6,T1,T2
10CoveredT6,T1,T2
11CoveredT6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT24,T30,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT6,T1,T2 VC_COV_UNR
1CoveredT24,T30,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT24,T30,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT24,T30,T40
10CoveredT6,T1,T2
11CoveredT24,T30,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT24,T30,T40
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT24,T30,T40
01CoveredT24,T40,T35
10CoveredT56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT24,T30,T40
1-CoveredT24,T40,T35

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T24,T30,T40
DetectSt 168 Covered T24,T30,T40
IdleSt 163 Covered T6,T1,T2
StableSt 191 Covered T24,T30,T40


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T24,T30,T40
DebounceSt->IdleSt 163 Covered T153,T145
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T24,T30,T40
IdleSt->DebounceSt 148 Covered T24,T30,T40
StableSt->IdleSt 206 Covered T24,T30,T40



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T24,T30,T40
0 1 Covered T24,T30,T40
0 0 Excluded T6,T1,T2 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T24,T30,T40
0 Covered T6,T1,T2


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T24,T30,T40
IdleSt 0 - - - - - - Covered T6,T1,T2
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T24,T30,T40
DebounceSt - 0 1 0 - - - Covered T153,T145
DebounceSt - 0 0 - - - - Covered T24,T30,T40
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T24,T30,T40
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T24,T40,T35
StableSt - - - - - - 0 Covered T24,T30,T40
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 9144370 96 0 0
CntIncr_A 9144370 2515 0 0
CntNoWrap_A 9144370 8508359 0 0
DetectStDropOut_A 9144370 0 0 0
DetectedOut_A 9144370 3112 0 0
DetectedPulseOut_A 9144370 47 0 0
DisabledIdleSt_A 9144370 8419353 0 0
DisabledNoDetection_A 9144370 8421591 0 0
EnterDebounceSt_A 9144370 49 0 0
EnterDetectSt_A 9144370 47 0 0
EnterStableSt_A 9144370 47 0 0
PulseIsPulse_A 9144370 47 0 0
StayInStableSt 9144370 3042 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 9144370 6438 0 0
gen_low_level_sva.LowLevelEvent_A 9144370 8510753 0 0
gen_not_sticky_sva.StableStDropOut_A 9144370 22 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 96 0 0
T24 247596 8 0 0
T25 1657 0 0 0
T30 0 2 0 0
T35 0 2 0 0
T39 0 2 0 0
T40 0 4 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 4 0 0
T160 0 2 0 0
T170 0 2 0 0
T175 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2515 0 0
T24 247596 197 0 0
T25 1657 0 0 0
T30 0 48 0 0
T35 0 30 0 0
T39 0 49 0 0
T40 0 164 0 0
T58 16125 0 0 0
T64 0 21 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 73 0 0
T160 0 21 0 0
T170 0 41 0 0
T175 0 79 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8508359 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 3112 0 0
T24 247596 390 0 0
T25 1657 0 0 0
T30 0 48 0 0
T35 0 20 0 0
T39 0 197 0 0
T40 0 268 0 0
T58 16125 0 0 0
T64 0 44 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 91 0 0
T160 0 38 0 0
T170 0 94 0 0
T175 0 74 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 47 0 0
T24 247596 4 0 0
T25 1657 0 0 0
T30 0 1 0 0
T35 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 2 0 0
T160 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8419353 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8421591 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 49 0 0
T24 247596 4 0 0
T25 1657 0 0 0
T30 0 1 0 0
T35 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 2 0 0
T160 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 47 0 0
T24 247596 4 0 0
T25 1657 0 0 0
T30 0 1 0 0
T35 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 2 0 0
T160 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 47 0 0
T24 247596 4 0 0
T25 1657 0 0 0
T30 0 1 0 0
T35 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 2 0 0
T160 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 47 0 0
T24 247596 4 0 0
T25 1657 0 0 0
T30 0 1 0 0
T35 0 1 0 0
T39 0 1 0 0
T40 0 2 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 2 0 0
T160 0 1 0 0
T170 0 1 0 0
T175 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 3042 0 0
T24 247596 384 0 0
T25 1657 0 0 0
T30 0 46 0 0
T35 0 19 0 0
T39 0 195 0 0
T40 0 265 0 0
T58 16125 0 0 0
T64 0 43 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T149 0 87 0 0
T160 0 36 0 0
T170 0 92 0 0
T175 0 72 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 6438 0 0
T1 11840 29 0 0
T2 15507 29 0 0
T4 0 9 0 0
T5 0 32 0 0
T6 507 6 0 0
T7 0 1 0 0
T12 443 1 0 0
T13 17092 10 0 0
T14 494 8 0 0
T15 16466 25 0 0
T16 515 0 0 0
T17 422 0 0 0
T18 672 0 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8510753 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 22 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T159 0 1 0 0
T161 0 1 0 0
T166 0 1 0 0
T177 0 1 0 0
T181 0 3 0 0
T188 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT6,T1,T2
10CoveredT6,T1,T2
11CoveredT6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT24,T38,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT6,T1,T2 VC_COV_UNR
1CoveredT24,T38,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT24,T38,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT24,T38,T40
10CoveredT6,T1,T2
11CoveredT24,T38,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT24,T38,T40
01CoveredT189
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT24,T38,T40
01CoveredT24,T38,T40
10CoveredT56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT24,T38,T40
1-CoveredT24,T38,T40

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T24,T38,T40
DetectSt 168 Covered T24,T38,T40
IdleSt 163 Covered T6,T1,T2
StableSt 191 Covered T24,T38,T40


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T24,T38,T40
DebounceSt->IdleSt 163 Covered T133,T190,T191
DetectSt->IdleSt 186 Covered T189
DetectSt->StableSt 191 Covered T24,T38,T40
IdleSt->DebounceSt 148 Covered T24,T38,T40
StableSt->IdleSt 206 Covered T24,T38,T40



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T24,T38,T40
0 1 Covered T24,T38,T40
0 0 Excluded T6,T1,T2 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T24,T38,T40
0 Covered T6,T1,T2


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T24,T38,T40
IdleSt 0 - - - - - - Covered T6,T1,T2
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T24,T38,T40
DebounceSt - 0 1 0 - - - Covered T133,T190,T191
DebounceSt - 0 0 - - - - Covered T24,T38,T40
DetectSt - - - - 1 - - Covered T189
DetectSt - - - - 0 1 - Covered T24,T38,T40
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T24,T38,T40
StableSt - - - - - - 0 Covered T24,T38,T40
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 9144370 135 0 0
CntIncr_A 9144370 37093 0 0
CntNoWrap_A 9144370 8508320 0 0
DetectStDropOut_A 9144370 1 0 0
DetectedOut_A 9144370 13819 0 0
DetectedPulseOut_A 9144370 65 0 0
DisabledIdleSt_A 9144370 8405813 0 0
DisabledNoDetection_A 9144370 8408057 0 0
EnterDebounceSt_A 9144370 69 0 0
EnterDetectSt_A 9144370 66 0 0
EnterStableSt_A 9144370 65 0 0
PulseIsPulse_A 9144370 65 0 0
StayInStableSt 9144370 13726 0 0
gen_high_level_sva.HighLevelEvent_A 9144370 8510753 0 0
gen_not_sticky_sva.StableStDropOut_A 9144370 35 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 135 0 0
T24 247596 4 0 0
T25 1657 0 0 0
T35 0 4 0 0
T36 0 6 0 0
T37 0 2 0 0
T38 0 2 0 0
T40 0 2 0 0
T58 16125 0 0 0
T64 0 4 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 2 0 0
T120 0 2 0 0
T170 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 37093 0 0
T24 247596 88 0 0
T25 1657 0 0 0
T35 0 60 0 0
T36 0 24970 0 0
T37 0 81 0 0
T38 0 52 0 0
T40 0 82 0 0
T58 16125 0 0 0
T64 0 182 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 78 0 0
T120 0 66 0 0
T170 0 41 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8508320 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 1 0 0
T92 10774 0 0 0
T156 1013 0 0 0
T189 644 1 0 0
T192 948 0 0 0
T193 503 0 0 0
T194 739 0 0 0
T195 735 0 0 0
T196 61607 0 0 0
T197 703 0 0 0
T198 422 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 13819 0 0
T24 247596 42 0 0
T25 1657 0 0 0
T35 0 227 0 0
T36 0 257 0 0
T37 0 39 0 0
T38 0 43 0 0
T40 0 126 0 0
T58 16125 0 0 0
T64 0 335 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 41 0 0
T120 0 38 0 0
T170 0 39 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 65 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 3 0 0
T37 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 1 0 0
T120 0 1 0 0
T170 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8405813 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8408057 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 69 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 3 0 0
T37 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 1 0 0
T120 0 1 0 0
T170 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 66 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 3 0 0
T37 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 1 0 0
T120 0 1 0 0
T170 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 65 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 3 0 0
T37 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 1 0 0
T120 0 1 0 0
T170 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 65 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 2 0 0
T36 0 3 0 0
T37 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 2 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 1 0 0
T120 0 1 0 0
T170 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 13726 0 0
T24 247596 40 0 0
T25 1657 0 0 0
T35 0 224 0 0
T36 0 252 0 0
T37 0 37 0 0
T38 0 42 0 0
T40 0 125 0 0
T58 16125 0 0 0
T64 0 332 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T86 0 39 0 0
T120 0 36 0 0
T170 0 38 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8510753 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 35 0 0
T24 247596 2 0 0
T25 1657 0 0 0
T35 0 1 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T58 16125 0 0 0
T64 0 1 0 0
T65 449 0 0 0
T66 522 0 0 0
T67 1309 0 0 0
T68 413 0 0 0
T69 494 0 0 0
T70 502 0 0 0
T71 402 0 0 0
T159 0 1 0 0
T161 0 1 0 0
T170 0 1 0 0
T199 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464291.30
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322887.50
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT6,T1,T2
10CoveredT6,T1,T2
11CoveredT6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT10,T38,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT6,T1,T2 VC_COV_UNR
1CoveredT10,T38,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT6,T1,T2
1CoveredT10,T38,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T10,T38
10CoveredT6,T1,T2
11CoveredT10,T38,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT10,T38,T30
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT10,T38,T30
01CoveredT64,T149,T161
10CoveredT56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT10,T38,T30
1-CoveredT64,T149,T161

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10,T38,T30
DetectSt 168 Covered T10,T38,T30
IdleSt 163 Covered T6,T1,T2
StableSt 191 Covered T10,T38,T30


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T10,T38,T30
DebounceSt->IdleSt 163 Covered T36,T200,T158
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T10,T38,T30
IdleSt->DebounceSt 148 Covered T10,T38,T30
StableSt->IdleSt 206 Covered T30,T40,T64



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T10,T38,T30
0 1 Covered T10,T38,T30
0 0 Excluded T6,T1,T2 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T10,T38,T30
0 Covered T6,T1,T2


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T10,T38,T30
IdleSt 0 - - - - - - Covered T6,T1,T2
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T10,T38,T30
DebounceSt - 0 1 0 - - - Covered T36,T158,T201
DebounceSt - 0 0 - - - - Covered T10,T38,T30
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T10,T38,T30
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T64,T149,T161
StableSt - - - - - - 0 Covered T10,T38,T30
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T6,T1,T2
0 Covered T6,T1,T2


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 9144370 83 0 0
CntIncr_A 9144370 8781 0 0
CntNoWrap_A 9144370 8508372 0 0
DetectStDropOut_A 9144370 0 0 0
DetectedOut_A 9144370 2839 0 0
DetectedPulseOut_A 9144370 40 0 0
DisabledIdleSt_A 9144370 8465998 0 0
DisabledNoDetection_A 9144370 8468236 0 0
EnterDebounceSt_A 9144370 44 0 0
EnterDetectSt_A 9144370 40 0 0
EnterStableSt_A 9144370 40 0 0
PulseIsPulse_A 9144370 40 0 0
StayInStableSt 9144370 2777 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 9144370 6011 0 0
gen_low_level_sva.LowLevelEvent_A 9144370 8510753 0 0
gen_not_sticky_sva.StableStDropOut_A 9144370 16 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 83 0 0
T10 828 2 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 2 0 0
T34 14374 0 0 0
T36 0 1 0 0
T38 0 2 0 0
T40 0 2 0 0
T64 0 4 0 0
T77 527 0 0 0
T149 0 2 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T161 0 2 0 0
T170 0 2 0 0
T176 0 2 0 0
T187 422 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8781 0 0
T10 828 38 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 48 0 0
T34 14374 0 0 0
T36 0 66 0 0
T38 0 52 0 0
T40 0 82 0 0
T64 0 169 0 0
T77 527 0 0 0
T149 0 48 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T161 0 35 0 0
T170 0 41 0 0
T176 0 26 0 0
T187 422 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8508372 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2839 0 0
T10 828 44 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 186 0 0
T34 14374 0 0 0
T38 0 121 0 0
T40 0 43 0 0
T64 0 254 0 0
T77 527 0 0 0
T149 0 135 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T159 0 169 0 0
T161 0 85 0 0
T170 0 180 0 0
T176 0 40 0 0
T187 422 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 40 0 0
T10 828 1 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 1 0 0
T34 14374 0 0 0
T38 0 1 0 0
T40 0 1 0 0
T64 0 2 0 0
T77 527 0 0 0
T149 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T159 0 1 0 0
T161 0 1 0 0
T170 0 1 0 0
T176 0 1 0 0
T187 422 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8465998 0 0
T1 11840 11427 0 0
T2 15507 15082 0 0
T6 507 106 0 0
T12 443 42 0 0
T13 17092 16645 0 0
T14 494 93 0 0
T15 16466 16065 0 0
T16 515 114 0 0
T17 422 21 0 0
T18 672 271 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8468236 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 44 0 0
T10 828 1 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 1 0 0
T34 14374 0 0 0
T36 0 1 0 0
T38 0 1 0 0
T40 0 1 0 0
T64 0 2 0 0
T77 527 0 0 0
T149 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T161 0 1 0 0
T170 0 1 0 0
T176 0 1 0 0
T187 422 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 40 0 0
T10 828 1 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 1 0 0
T34 14374 0 0 0
T38 0 1 0 0
T40 0 1 0 0
T64 0 2 0 0
T77 527 0 0 0
T149 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T159 0 1 0 0
T161 0 1 0 0
T170 0 1 0 0
T176 0 1 0 0
T187 422 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 40 0 0
T10 828 1 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 1 0 0
T34 14374 0 0 0
T38 0 1 0 0
T40 0 1 0 0
T64 0 2 0 0
T77 527 0 0 0
T149 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T159 0 1 0 0
T161 0 1 0 0
T170 0 1 0 0
T176 0 1 0 0
T187 422 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 40 0 0
T10 828 1 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 1 0 0
T34 14374 0 0 0
T38 0 1 0 0
T40 0 1 0 0
T64 0 2 0 0
T77 527 0 0 0
T149 0 1 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T159 0 1 0 0
T161 0 1 0 0
T170 0 1 0 0
T176 0 1 0 0
T187 422 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 2777 0 0
T10 828 42 0 0
T11 889 0 0 0
T28 502 0 0 0
T29 502 0 0 0
T30 0 184 0 0
T34 14374 0 0 0
T38 0 119 0 0
T40 0 41 0 0
T64 0 252 0 0
T77 527 0 0 0
T149 0 134 0 0
T150 408 0 0 0
T151 639 0 0 0
T152 422 0 0 0
T159 0 167 0 0
T161 0 84 0 0
T170 0 178 0 0
T176 0 38 0 0
T187 422 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 6011 0 0
T1 11840 27 0 0
T2 15507 27 0 0
T4 0 10 0 0
T5 0 28 0 0
T6 507 4 0 0
T12 443 5 0 0
T13 17092 6 0 0
T14 494 6 0 0
T15 16466 24 0 0
T16 515 0 0 0
T17 422 3 0 0
T18 672 0 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 8510753 0 0
T1 11840 11430 0 0
T2 15507 15086 0 0
T6 507 107 0 0
T12 443 43 0 0
T13 17092 16651 0 0
T14 494 94 0 0
T15 16466 16066 0 0
T16 515 115 0 0
T17 422 22 0 0
T18 672 272 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9144370 16 0 0
T64 173148 2 0 0
T136 0 1 0 0
T149 0 1 0 0
T156 0 2 0 0
T157 0 1 0 0
T161 0 1 0 0
T164 0 1 0 0
T168 0 1 0 0
T178 0 1 0 0
T190 0 2 0 0
T202 714 0 0 0
T203 480 0 0 0
T204 846 0 0 0
T205 502 0 0 0
T206 502 0 0 0
T207 424 0 0 0
T208 507 0 0 0
T209 425 0 0 0
T210 27480 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%